2 * cpufreq driver for Enhanced SpeedStep, as found in Intel's Pentium
3 * M (part of the Centrino chipset).
5 * Despite the "SpeedStep" in the name, this is almost entirely unlike
6 * traditional SpeedStep.
8 * Modelled on speedstep.c
10 * Copyright (C) 2003 Jeremy Fitzhardinge <jeremy@goop.org>
12 * WARNING WARNING WARNING
14 * This driver manipulates the PERF_CTL MSR, which is only somewhat
15 * documented. While it seems to work on my laptop, it has not been
16 * tested anywhere else, and it may not work for you, do strange
17 * things or simply crash.
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/init.h>
23 #include <linux/cpufreq.h>
24 #include <linux/config.h>
25 #include <linux/sched.h> /* current */
26 #include <linux/delay.h>
27 #include <linux/compiler.h>
29 #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
30 #include <linux/acpi.h>
31 #include <acpi/processor.h>
35 #include <asm/processor.h>
36 #include <asm/cpufeature.h>
38 #define PFX "speedstep-centrino: "
39 #define MAINTAINER "Jeremy Fitzhardinge <jeremy@goop.org>"
41 #define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "speedstep-centrino", msg)
46 __u8 x86; /* CPU family */
47 __u8 x86_model; /* model */
48 __u8 x86_mask; /* stepping */
60 static const struct cpu_id cpu_ids[] = {
61 [CPU_BANIAS] = { 6, 9, 5 },
62 [CPU_DOTHAN_A1] = { 6, 13, 1 },
63 [CPU_DOTHAN_A2] = { 6, 13, 2 },
64 [CPU_DOTHAN_B0] = { 6, 13, 6 },
65 [CPU_MP4HT_D0] = {15, 3, 4 },
66 [CPU_MP4HT_E0] = {15, 4, 1 },
68 #define N_IDS ARRAY_SIZE(cpu_ids)
72 const struct cpu_id *cpu_id;
73 const char *model_name;
74 unsigned max_freq; /* max clock in kHz */
76 struct cpufreq_frequency_table *op_points; /* clock/voltage pairs */
78 static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c, const struct cpu_id *x);
80 /* Operating points for current CPU */
81 static struct cpu_model *centrino_model[NR_CPUS];
82 static const struct cpu_id *centrino_cpu[NR_CPUS];
84 static struct cpufreq_driver centrino_driver;
86 #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE
88 /* Computes the correct form for IA32_PERF_CTL MSR for a particular
89 frequency/voltage operating point; frequency in MHz, volts in mV.
90 This is stored as "index" in the structure. */
93 .frequency = (mhz) * 1000, \
94 .index = (((mhz)/100) << 8) | ((mv - 700) / 16) \
98 * These voltage tables were derived from the Intel Pentium M
99 * datasheet, document 25261202.pdf, Table 5. I have verified they
100 * are consistent with my IBM ThinkPad X31, which has a 1.3GHz Pentium
104 /* Ultra Low Voltage Intel Pentium M processor 900MHz (Banias) */
105 static struct cpufreq_frequency_table banias_900[] =
110 { .frequency = CPUFREQ_TABLE_END }
113 /* Ultra Low Voltage Intel Pentium M processor 1000MHz (Banias) */
114 static struct cpufreq_frequency_table banias_1000[] =
120 { .frequency = CPUFREQ_TABLE_END }
123 /* Low Voltage Intel Pentium M processor 1.10GHz (Banias) */
124 static struct cpufreq_frequency_table banias_1100[] =
131 { .frequency = CPUFREQ_TABLE_END }
135 /* Low Voltage Intel Pentium M processor 1.20GHz (Banias) */
136 static struct cpufreq_frequency_table banias_1200[] =
144 { .frequency = CPUFREQ_TABLE_END }
147 /* Intel Pentium M processor 1.30GHz (Banias) */
148 static struct cpufreq_frequency_table banias_1300[] =
155 { .frequency = CPUFREQ_TABLE_END }
158 /* Intel Pentium M processor 1.40GHz (Banias) */
159 static struct cpufreq_frequency_table banias_1400[] =
166 { .frequency = CPUFREQ_TABLE_END }
169 /* Intel Pentium M processor 1.50GHz (Banias) */
170 static struct cpufreq_frequency_table banias_1500[] =
178 { .frequency = CPUFREQ_TABLE_END }
181 /* Intel Pentium M processor 1.60GHz (Banias) */
182 static struct cpufreq_frequency_table banias_1600[] =
190 { .frequency = CPUFREQ_TABLE_END }
193 /* Intel Pentium M processor 1.70GHz (Banias) */
194 static struct cpufreq_frequency_table banias_1700[] =
202 { .frequency = CPUFREQ_TABLE_END }
206 #define _BANIAS(cpuid, max, name) \
208 .model_name = "Intel(R) Pentium(R) M processor " name "MHz", \
209 .max_freq = (max)*1000, \
210 .op_points = banias_##max, \
212 #define BANIAS(max) _BANIAS(&cpu_ids[CPU_BANIAS], max, #max)
214 /* CPU models, their operating frequency range, and freq/voltage
216 static struct cpu_model models[] =
218 _BANIAS(&cpu_ids[CPU_BANIAS], 900, " 900"),
228 /* NULL model_name is a wildcard */
229 { &cpu_ids[CPU_DOTHAN_A1], NULL, 0, NULL },
230 { &cpu_ids[CPU_DOTHAN_A2], NULL, 0, NULL },
231 { &cpu_ids[CPU_DOTHAN_B0], NULL, 0, NULL },
232 { &cpu_ids[CPU_MP4HT_D0], NULL, 0, NULL },
233 { &cpu_ids[CPU_MP4HT_E0], NULL, 0, NULL },
240 static int centrino_cpu_init_table(struct cpufreq_policy *policy)
242 struct cpuinfo_x86 *cpu = &cpu_data[policy->cpu];
243 struct cpu_model *model;
245 for(model = models; model->cpu_id != NULL; model++)
246 if (centrino_verify_cpu_id(cpu, model->cpu_id) &&
247 (model->model_name == NULL ||
248 strcmp(cpu->x86_model_id, model->model_name) == 0))
251 if (model->cpu_id == NULL) {
252 /* No match at all */
253 dprintk(KERN_INFO PFX "no support for CPU model \"%s\": "
254 "send /proc/cpuinfo to " MAINTAINER "\n",
259 if (model->op_points == NULL) {
260 /* Matched a non-match */
261 dprintk(KERN_INFO PFX "no table support for CPU model \"%s\"\n",
263 #ifndef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
264 dprintk(KERN_INFO PFX "try compiling with CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI enabled\n");
269 centrino_model[policy->cpu] = model;
271 dprintk("found \"%s\": max frequency: %dkHz\n",
272 model->model_name, model->max_freq);
278 static inline int centrino_cpu_init_table(struct cpufreq_policy *policy) { return -ENODEV; }
279 #endif /* CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE */
281 static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c, const struct cpu_id *x)
283 if ((c->x86 == x->x86) &&
284 (c->x86_model == x->x86_model) &&
285 (c->x86_mask == x->x86_mask))
290 /* To be called only after centrino_model is initialized */
291 static unsigned extract_clock(unsigned msr, unsigned int cpu, int failsafe)
296 * Extract clock in kHz from PERF_CTL value
297 * for centrino, as some DSDTs are buggy.
298 * Ideally, this can be done using the acpi_data structure.
300 if ((centrino_cpu[cpu] == &cpu_ids[CPU_BANIAS]) ||
301 (centrino_cpu[cpu] == &cpu_ids[CPU_DOTHAN_A1]) ||
302 (centrino_cpu[cpu] == &cpu_ids[CPU_DOTHAN_B0])) {
303 msr = (msr >> 8) & 0xff;
307 if ((!centrino_model[cpu]) || (!centrino_model[cpu]->op_points))
311 for (i=0;centrino_model[cpu]->op_points[i].frequency != CPUFREQ_TABLE_END; i++) {
312 if (msr == centrino_model[cpu]->op_points[i].index)
313 return centrino_model[cpu]->op_points[i].frequency;
316 return centrino_model[cpu]->op_points[i-1].frequency;
321 /* Return the current CPU frequency in kHz */
322 static unsigned int get_cur_freq(unsigned int cpu)
326 cpumask_t saved_mask;
328 saved_mask = current->cpus_allowed;
329 set_cpus_allowed(current, cpumask_of_cpu(cpu));
330 if (smp_processor_id() != cpu)
333 rdmsr(MSR_IA32_PERF_STATUS, l, h);
334 clock_freq = extract_clock(l, cpu, 0);
336 if (unlikely(clock_freq == 0)) {
338 * On some CPUs, we can see transient MSR values (which are
339 * not present in _PSS), while CPU is doing some automatic
340 * P-state transition (like TM2). Get the last freq set
343 rdmsr(MSR_IA32_PERF_CTL, l, h);
344 clock_freq = extract_clock(l, cpu, 1);
347 set_cpus_allowed(current, saved_mask);
352 #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
354 static struct acpi_processor_performance p;
357 * centrino_cpu_init_acpi - register with ACPI P-States library
359 * Register with the ACPI P-States library (part of drivers/acpi/processor.c)
360 * in order to determine correct frequency and voltage pairings by reading
361 * the _PSS of the ACPI DSDT or SSDT tables.
363 static int centrino_cpu_init_acpi(struct cpufreq_policy *policy)
365 union acpi_object arg0 = {ACPI_TYPE_BUFFER};
367 struct acpi_object_list arg_list = {1, &arg0};
368 unsigned long cur_freq;
370 unsigned int cpu = policy->cpu;
373 arg0.buffer.length = 12;
374 arg0.buffer.pointer = (u8 *) arg0_buf;
375 arg0_buf[0] = ACPI_PDC_REVISION_ID;
377 arg0_buf[2] = ACPI_PDC_EST_CAPABILITY_SMP_MSR;
381 /* register with ACPI core */
382 if (acpi_processor_register_performance(&p, cpu)) {
383 dprintk(KERN_INFO PFX "obtaining ACPI data failed\n");
387 /* verify the acpi_data */
388 if (p.state_count <= 1) {
389 dprintk("No P-States\n");
394 if ((p.control_register.space_id != ACPI_ADR_SPACE_FIXED_HARDWARE) ||
395 (p.status_register.space_id != ACPI_ADR_SPACE_FIXED_HARDWARE)) {
396 dprintk("Invalid control/status registers (%x - %x)\n",
397 p.control_register.space_id, p.status_register.space_id);
402 for (i=0; i<p.state_count; i++) {
403 if (p.states[i].control != p.states[i].status) {
404 dprintk("Different control (%llu) and status values (%llu)\n",
405 p.states[i].control, p.states[i].status);
410 if (!p.states[i].core_frequency) {
411 dprintk("Zero core frequency for state %u\n", i);
416 if (p.states[i].core_frequency > p.states[0].core_frequency) {
417 dprintk("P%u has larger frequency (%llu) than P0 (%llu), skipping\n", i,
418 p.states[i].core_frequency, p.states[0].core_frequency);
419 p.states[i].core_frequency = 0;
424 centrino_model[cpu] = kzalloc(sizeof(struct cpu_model), GFP_KERNEL);
425 if (!centrino_model[cpu]) {
430 centrino_model[cpu]->model_name=NULL;
431 centrino_model[cpu]->max_freq = p.states[0].core_frequency * 1000;
432 centrino_model[cpu]->op_points = kmalloc(sizeof(struct cpufreq_frequency_table) *
433 (p.state_count + 1), GFP_KERNEL);
434 if (!centrino_model[cpu]->op_points) {
439 for (i=0; i<p.state_count; i++) {
440 centrino_model[cpu]->op_points[i].index = p.states[i].control;
441 centrino_model[cpu]->op_points[i].frequency = p.states[i].core_frequency * 1000;
442 dprintk("adding state %i with frequency %u and control value %04x\n",
443 i, centrino_model[cpu]->op_points[i].frequency, centrino_model[cpu]->op_points[i].index);
445 centrino_model[cpu]->op_points[p.state_count].frequency = CPUFREQ_TABLE_END;
447 cur_freq = get_cur_freq(cpu);
449 for (i=0; i<p.state_count; i++) {
450 if (!p.states[i].core_frequency) {
451 dprintk("skipping state %u\n", i);
452 centrino_model[cpu]->op_points[i].frequency = CPUFREQ_ENTRY_INVALID;
456 if (extract_clock(centrino_model[cpu]->op_points[i].index, cpu, 0) !=
457 (centrino_model[cpu]->op_points[i].frequency)) {
458 dprintk("Invalid encoded frequency (%u vs. %u)\n",
459 extract_clock(centrino_model[cpu]->op_points[i].index, cpu, 0),
460 centrino_model[cpu]->op_points[i].frequency);
465 if (cur_freq == centrino_model[cpu]->op_points[i].frequency)
469 /* notify BIOS that we exist */
470 acpi_processor_notify_smm(THIS_MODULE);
475 kfree(centrino_model[cpu]->op_points);
477 kfree(centrino_model[cpu]);
479 acpi_processor_unregister_performance(&p, cpu);
480 dprintk(KERN_INFO PFX "invalid ACPI data\n");
484 static inline int centrino_cpu_init_acpi(struct cpufreq_policy *policy) { return -ENODEV; }
487 static int centrino_cpu_init(struct cpufreq_policy *policy)
489 struct cpuinfo_x86 *cpu = &cpu_data[policy->cpu];
494 struct cpuinfo_x86 *c = &cpu_data[policy->cpu];
496 /* Only Intel makes Enhanced Speedstep-capable CPUs */
497 if (cpu->x86_vendor != X86_VENDOR_INTEL || !cpu_has(cpu, X86_FEATURE_EST))
500 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) {
501 centrino_driver.flags |= CPUFREQ_CONST_LOOPS;
504 if (centrino_cpu_init_acpi(policy)) {
505 if (policy->cpu != 0)
508 for (i = 0; i < N_IDS; i++)
509 if (centrino_verify_cpu_id(cpu, &cpu_ids[i]))
513 centrino_cpu[policy->cpu] = &cpu_ids[i];
515 if (!centrino_cpu[policy->cpu]) {
516 dprintk(KERN_INFO PFX "found unsupported CPU with "
517 "Enhanced SpeedStep: send /proc/cpuinfo to "
522 if (centrino_cpu_init_table(policy)) {
527 /* Check to see if Enhanced SpeedStep is enabled, and try to
529 rdmsr(MSR_IA32_MISC_ENABLE, l, h);
531 if (!(l & (1<<16))) {
533 dprintk("trying to enable Enhanced SpeedStep (%x)\n", l);
534 wrmsr(MSR_IA32_MISC_ENABLE, l, h);
536 /* check to see if it stuck */
537 rdmsr(MSR_IA32_MISC_ENABLE, l, h);
538 if (!(l & (1<<16))) {
539 printk(KERN_INFO PFX "couldn't enable Enhanced SpeedStep\n");
544 freq = get_cur_freq(policy->cpu);
546 policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
547 policy->cpuinfo.transition_latency = 10000; /* 10uS transition latency */
550 dprintk("centrino_cpu_init: cur=%dkHz\n", policy->cur);
552 ret = cpufreq_frequency_table_cpuinfo(policy, centrino_model[policy->cpu]->op_points);
556 cpufreq_frequency_table_get_attr(centrino_model[policy->cpu]->op_points, policy->cpu);
561 static int centrino_cpu_exit(struct cpufreq_policy *policy)
563 unsigned int cpu = policy->cpu;
565 if (!centrino_model[cpu])
568 cpufreq_frequency_table_put_attr(cpu);
570 #ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_ACPI
571 if (!centrino_model[cpu]->model_name) {
572 dprintk("unregistering and freeing ACPI data\n");
573 acpi_processor_unregister_performance(&p, cpu);
574 kfree(centrino_model[cpu]->op_points);
575 kfree(centrino_model[cpu]);
579 centrino_model[cpu] = NULL;
585 * centrino_verify - verifies a new CPUFreq policy
586 * @policy: new policy
588 * Limit must be within this model's frequency range at least one
591 static int centrino_verify (struct cpufreq_policy *policy)
593 return cpufreq_frequency_table_verify(policy, centrino_model[policy->cpu]->op_points);
597 * centrino_setpolicy - set a new CPUFreq policy
598 * @policy: new policy
599 * @target_freq: the target frequency
600 * @relation: how that frequency relates to achieved frequency (CPUFREQ_RELATION_L or CPUFREQ_RELATION_H)
602 * Sets a new CPUFreq policy.
604 static int centrino_target (struct cpufreq_policy *policy,
605 unsigned int target_freq,
606 unsigned int relation)
608 unsigned int newstate = 0;
609 unsigned int msr, oldmsr, h, cpu = policy->cpu;
610 struct cpufreq_freqs freqs;
611 cpumask_t saved_mask;
614 if (centrino_model[cpu] == NULL)
618 * Support for SMP systems.
619 * Make sure we are running on the CPU that wants to change frequency
621 saved_mask = current->cpus_allowed;
622 set_cpus_allowed(current, policy->cpus);
623 if (!cpu_isset(smp_processor_id(), policy->cpus)) {
624 dprintk("couldn't limit to CPUs in this domain\n");
628 if (cpufreq_frequency_table_target(policy, centrino_model[cpu]->op_points, target_freq,
629 relation, &newstate)) {
634 msr = centrino_model[cpu]->op_points[newstate].index;
635 rdmsr(MSR_IA32_PERF_CTL, oldmsr, h);
637 if (msr == (oldmsr & 0xffff)) {
639 dprintk("no change needed - msr was and needs to be %x\n", oldmsr);
644 freqs.old = extract_clock(oldmsr, cpu, 0);
645 freqs.new = extract_clock(msr, cpu, 0);
647 dprintk("target=%dkHz old=%d new=%d msr=%04x\n",
648 target_freq, freqs.old, freqs.new, msr);
650 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
652 /* all but 16 LSB are "reserved", so treat them with
658 wrmsr(MSR_IA32_PERF_CTL, oldmsr, h);
660 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
664 set_cpus_allowed(current, saved_mask);
668 static struct freq_attr* centrino_attr[] = {
669 &cpufreq_freq_attr_scaling_available_freqs,
673 static struct cpufreq_driver centrino_driver = {
674 .name = "centrino", /* should be speedstep-centrino,
675 but there's a 16 char limit */
676 .init = centrino_cpu_init,
677 .exit = centrino_cpu_exit,
678 .verify = centrino_verify,
679 .target = centrino_target,
681 .attr = centrino_attr,
682 .owner = THIS_MODULE,
687 * centrino_init - initializes the Enhanced SpeedStep CPUFreq driver
689 * Initializes the Enhanced SpeedStep support. Returns -ENODEV on
690 * unsupported devices, -ENOENT if there's no voltage table for this
691 * particular CPU model, -EINVAL on problems during initiatization,
692 * and zero on success.
694 * This is quite picky. Not only does the CPU have to advertise the
695 * "est" flag in the cpuid capability flags, we look for a specific
696 * CPU model and stepping, and we need to have the exact model name in
697 * our voltage tables. That is, be paranoid about not releasing
698 * someone's valuable magic smoke.
700 static int __init centrino_init(void)
702 struct cpuinfo_x86 *cpu = cpu_data;
704 if (!cpu_has(cpu, X86_FEATURE_EST))
707 return cpufreq_register_driver(¢rino_driver);
710 static void __exit centrino_exit(void)
712 cpufreq_unregister_driver(¢rino_driver);
715 MODULE_AUTHOR ("Jeremy Fitzhardinge <jeremy@goop.org>");
716 MODULE_DESCRIPTION ("Enhanced SpeedStep driver for Intel Pentium M processors.");
717 MODULE_LICENSE ("GPL");
719 late_initcall(centrino_init);
720 module_exit(centrino_exit);