2 * Blackfin power management
4 * Copyright 2006-2009 Analog Devices Inc.
6 * Licensed under the GPL-2
7 * based on arm/mach-omap/pm.c
8 * Copyright 2001, Cliff Brake <cbrake@accelent.com> and others
11 #include <linux/suspend.h>
12 #include <linux/sched.h>
13 #include <linux/proc_fs.h>
14 #include <linux/slab.h>
16 #include <linux/irq.h>
24 void bfin_pm_suspend_standby_enter(void)
28 flags = hard_local_irq_save();
29 bfin_pm_standby_setup();
31 #ifdef CONFIG_PM_BFIN_SLEEP_DEEPER
32 sleep_deeper(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]);
34 sleep_mode(bfin_sic_iwr[0], bfin_sic_iwr[1], bfin_sic_iwr[2]);
37 bfin_pm_standby_restore();
40 bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
42 /* BF52x system reset does not properly reset SIC_IWR1 which
43 * will screw up the bootrom as it relies on MDMA0/1 waking it
44 * up from IDLE instructions. See this report for more info:
45 * http://blackfin.uclinux.org/gf/tracker/4323
48 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
50 bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
53 bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
56 bfin_write_SIC_IWR(IWR_DISABLE_ALL);
59 hard_local_irq_restore(flags);
62 int bf53x_suspend_l1_mem(unsigned char *memptr)
64 dma_memcpy_nocache(memptr, (const void *) L1_CODE_START,
66 dma_memcpy_nocache(memptr + L1_CODE_LENGTH,
67 (const void *) L1_DATA_A_START, L1_DATA_A_LENGTH);
68 dma_memcpy_nocache(memptr + L1_CODE_LENGTH + L1_DATA_A_LENGTH,
69 (const void *) L1_DATA_B_START, L1_DATA_B_LENGTH);
70 memcpy(memptr + L1_CODE_LENGTH + L1_DATA_A_LENGTH +
71 L1_DATA_B_LENGTH, (const void *) L1_SCRATCH_START,
77 int bf53x_resume_l1_mem(unsigned char *memptr)
79 dma_memcpy_nocache((void *) L1_CODE_START, memptr, L1_CODE_LENGTH);
80 dma_memcpy_nocache((void *) L1_DATA_A_START, memptr + L1_CODE_LENGTH,
82 dma_memcpy_nocache((void *) L1_DATA_B_START, memptr + L1_CODE_LENGTH +
83 L1_DATA_A_LENGTH, L1_DATA_B_LENGTH);
84 memcpy((void *) L1_SCRATCH_START, memptr + L1_CODE_LENGTH +
85 L1_DATA_A_LENGTH + L1_DATA_B_LENGTH, L1_SCRATCH_LENGTH);
90 #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
91 static void flushinv_all_dcache(void)
93 u32 way, bank, subbank, set;
95 u32 dmem_ctl = bfin_read_DMEM_CONTROL();
97 for (bank = 0; bank < 2; ++bank) {
98 if (!(dmem_ctl & (1 << (DMC1_P - bank))))
101 for (way = 0; way < 2; ++way)
102 for (subbank = 0; subbank < 4; ++subbank)
103 for (set = 0; set < 64; ++set) {
105 bfin_write_DTEST_COMMAND(
112 status = bfin_read_DTEST_DATA0();
114 /* only worry about valid/dirty entries */
115 if ((status & 0x3) != 0x3)
118 /* construct the address using the tag */
119 addr = (status & 0xFFFFC800) | (subbank << 12) | (set << 5);
122 __asm__ __volatile__("FLUSHINV[%0];" : : "a"(addr));
128 int bfin_pm_suspend_mem_enter(void)
133 unsigned char *memptr = kmalloc(L1_CODE_LENGTH + L1_DATA_A_LENGTH
134 + L1_DATA_B_LENGTH + L1_SCRATCH_LENGTH,
137 if (memptr == NULL) {
138 panic("bf53x_suspend_l1_mem malloc failed");
142 wakeup = bfin_read_VR_CTL() & ~FREQ;
145 #ifdef CONFIG_PM_BFIN_WAKE_PH6
148 #ifdef CONFIG_PM_BFIN_WAKE_GP
152 flags = hard_local_irq_save();
154 ret = blackfin_dma_suspend();
157 hard_local_irq_restore(flags);
162 bfin_gpio_pm_hibernate_suspend();
164 #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
165 flushinv_all_dcache();
169 bf53x_suspend_l1_mem(memptr);
171 do_hibernate(wakeup | vr_wakeup); /* See you later! */
173 bf53x_resume_l1_mem(memptr);
178 bfin_gpio_pm_hibernate_restore();
179 blackfin_dma_resume();
181 hard_local_irq_restore(flags);
188 * bfin_pm_valid - Tell the PM core that we only support the standby sleep
190 * @state: suspend state we're checking.
193 static int bfin_pm_valid(suspend_state_t state)
195 return (state == PM_SUSPEND_STANDBY
196 #if !(defined(BF533_FAMILY) || defined(CONFIG_BF561))
199 * If we enter Hibernate the SCKE Pin is driven Low,
200 * so that the SDRAM enters Self Refresh Mode.
201 * However when the reset sequence that follows hibernate
202 * state is executed, SCKE is driven High, taking the
203 * SDRAM out of Self Refresh.
205 * If you reconfigure and access the SDRAM "very quickly",
206 * you are likely to avoid errors, otherwise the SDRAM
207 * start losing its contents.
208 * An external HW workaround is possible using logic gates.
210 || state == PM_SUSPEND_MEM
216 * bfin_pm_enter - Actually enter a sleep state.
217 * @state: State we're entering.
220 static int bfin_pm_enter(suspend_state_t state)
223 case PM_SUSPEND_STANDBY:
224 bfin_pm_suspend_standby_enter();
227 bfin_pm_suspend_mem_enter();
236 struct platform_suspend_ops bfin_pm_ops = {
237 .enter = bfin_pm_enter,
238 .valid = bfin_pm_valid,
241 static int __init bfin_pm_init(void)
243 suspend_set_ops(&bfin_pm_ops);
247 __initcall(bfin_pm_init);