arch/blackfin/mach-bf561/smp.c

   1 /*
   2  * Copyright 2007-2009 Analog Devices Inc.
   3  *               Philippe Gerum <rpm@xenomai.org>
   4  *
   5  * Licensed under the GPL-2 or later.
   6  */
   7
   8 #include <linux/init.h>
   9 #include <linux/kernel.h>
  10 #include <linux/sched.h>
  11 #include <linux/delay.h>
  12 #include <asm/smp.h>
  13 #include <asm/dma.h>
  14
  15 static DEFINE_SPINLOCK(boot_lock);
  16
  17 /*
  18  * platform_init_cpus() - Tell the world about how many cores we
  19  * have. This is called while setting up the architecture support
  20  * (setup_arch()), so don't be too demanding here with respect to
  21  * available kernel services.
  22  */
  23
  24 void __init platform_init_cpus(void)
  25 {
  26         cpu_set(0, cpu_possible_map); /* CoreA */
  27         cpu_set(1, cpu_possible_map); /* CoreB */
  28 }
  29
  30 void __init platform_prepare_cpus(unsigned int max_cpus)
  31 {
  32         int len;
  33
  34         len = &coreb_trampoline_end - &coreb_trampoline_start + 1;
  35         BUG_ON(len > L1_CODE_LENGTH);
  36
  37         dma_memcpy((void *)COREB_L1_CODE_START, &coreb_trampoline_start, len);
  38
  39         /* Both cores ought to be present on a bf561! */
  40         cpu_set(0, cpu_present_map); /* CoreA */
  41         cpu_set(1, cpu_present_map); /* CoreB */
  42
  43         printk(KERN_INFO "CoreB bootstrap code to SRAM %p via DMA.\n", (void *)COREB_L1_CODE_START);
  44 }
  45
  46 int __init setup_profiling_timer(unsigned int multiplier) /* not supported */
  47 {
  48         return -EINVAL;
  49 }
  50
  51 void __cpuinit platform_secondary_init(unsigned int cpu)
  52 {
  53         /* Clone setup for peripheral interrupt sources from CoreA. */
  54         bfin_write_SICB_IMASK0(bfin_read_SICA_IMASK0());
  55         bfin_write_SICB_IMASK1(bfin_read_SICA_IMASK1());
  56         SSYNC();
  57
  58         /* Clone setup for IARs from CoreA. */
  59         bfin_write_SICB_IAR0(bfin_read_SICA_IAR0());
  60         bfin_write_SICB_IAR1(bfin_read_SICA_IAR1());
  61         bfin_write_SICB_IAR2(bfin_read_SICA_IAR2());
  62         bfin_write_SICB_IAR3(bfin_read_SICA_IAR3());
  63         bfin_write_SICB_IAR4(bfin_read_SICA_IAR4());
  64         bfin_write_SICB_IAR5(bfin_read_SICA_IAR5());
  65         bfin_write_SICB_IAR6(bfin_read_SICA_IAR6());
  66         bfin_write_SICB_IAR7(bfin_read_SICA_IAR7());
  67         SSYNC();
  68
  69         /* Store CPU-private information to the cpu_data array. */
  70         bfin_setup_cpudata(cpu);
  71
  72         /* We are done with local CPU inits, unblock the boot CPU. */
  73         set_cpu_online(cpu, true);
  74         spin_lock(&boot_lock);
  75         spin_unlock(&boot_lock);
  76 }
  77
  78 int __cpuinit platform_boot_secondary(unsigned int cpu, struct task_struct *idle)
  79 {
  80         unsigned long timeout;
  81
  82         /* CoreB already running?! */
  83         BUG_ON((bfin_read_SICA_SYSCR() & COREB_SRAM_INIT) == 0);
  84
  85         printk(KERN_INFO "Booting Core B.\n");
  86
  87         spin_lock(&boot_lock);
  88
  89         /* Kick CoreB, which should start execution from CORE_SRAM_BASE. */
  90         SSYNC();
  91         bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() & ~COREB_SRAM_INIT);
  92         SSYNC();
  93
  94         timeout = jiffies + 1 * HZ;
  95         while (time_before(jiffies, timeout)) {
  96                 if (cpu_online(cpu))
  97                         break;
  98                 udelay(100);
  99                 barrier();
 100         }
 101
 102         if (cpu_online(cpu)) {
 103                 /* release the lock and let coreb run */
 104                 spin_unlock(&boot_lock);
 105                 return 0;
 106         } else
 107                 panic("CPU%u: processor failed to boot\n", cpu);
 108 }
 109
 110 void __init platform_request_ipi(irq_handler_t handler)
 111 {
 112         int ret;
 113
 114         ret = request_irq(IRQ_SUPPLE_0, handler, IRQF_DISABLED,
 115                           "Supplemental Interrupt0", handler);
 116         if (ret)
 117                 panic("Cannot request supplemental interrupt 0 for IPI service");
 118 }
 119
 120 void platform_send_ipi(cpumask_t callmap)
 121 {
 122         unsigned int cpu;
 123
 124         for_each_cpu_mask(cpu, callmap) {
 125                 BUG_ON(cpu >= 2);
 126                 SSYNC();
 127                 bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (6 + cpu)));
 128                 SSYNC();
 129         }
 130 }
 131
 132 void platform_send_ipi_cpu(unsigned int cpu)
 133 {
 134         BUG_ON(cpu >= 2);
 135         SSYNC();
 136         bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (6 + cpu)));
 137         SSYNC();
 138 }
 139
 140 void platform_clear_ipi(unsigned int cpu)
 141 {
 142         BUG_ON(cpu >= 2);
 143         SSYNC();
 144         bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (10 + cpu)));
 145         SSYNC();
 146 }