arch/blackfin/mach-bf561/boards/acvilon.c

   1 /*
   2  * File:         arch/blackfin/mach-bf561/acvilon.c
   3  * Based on:     arch/blackfin/mach-bf561/ezkit.c
   4  * Author:
   5  *
   6  * Created:
   7  * Description:
   8  *
   9  * Modified:
  10  *               Copyright 2004-2006 Analog Devices Inc.
  11  *               Copyright 2009 CJSC "NII STT"
  12  *
  13  * Bugs:
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License as published by
  17  * the Free Software Foundation; either version 2 of the License, or
  18  * (at your option) any later version.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  *
  25  * You should have received a copy of the GNU General Public License
  26  * along with this program; if not, see the file COPYING, or write
  27  * to the Free Software Foundation, Inc.,
  28  * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  29  *
  30  *
  31  * For more information about Acvilon BF561 SoM please
  32  * go to http://www.niistt.ru/
  33  *
  34  */
  35
  36 #include <linux/device.h>
  37 #include <linux/platform_device.h>
  38 #include <linux/mtd/mtd.h>
  39 #include <linux/mtd/partitions.h>
  40 #include <linux/mtd/physmap.h>
  41 #include <linux/mtd/nand.h>
  42 #include <linux/mtd/plat-ram.h>
  43 #include <linux/spi/spi.h>
  44 #include <linux/spi/flash.h>
  45 #include <linux/irq.h>
  46 #include <linux/interrupt.h>
  47 #include <linux/jiffies.h>
  48 #include <linux/i2c-pca-platform.h>
  49 #include <linux/delay.h>
  50 #include <linux/io.h>
  51 #include <asm/dma.h>
  52 #include <asm/bfin5xx_spi.h>
  53 #include <asm/portmux.h>
  54 #include <asm/dpmc.h>
  55 #include <asm/cacheflush.h>
  56 #include <linux/i2c.h>
  57
  58 /*
  59  * Name the Board for the /proc/cpuinfo
  60  */
  61 const char bfin_board_name[] = "Acvilon board";
  62
  63 #if defined(CONFIG_USB_ISP1760_HCD) || defined(CONFIG_USB_ISP1760_HCD_MODULE)
  64 #include <linux/usb/isp1760.h>
  65 static struct resource bfin_isp1760_resources[] = {
  66         [0] = {
  67                .start = 0x20000000,
  68                .end = 0x20000000 + 0x000fffff,
  69                .flags = IORESOURCE_MEM,
  70                },
  71         [1] = {
  72                .start = IRQ_PF15,
  73                .end = IRQ_PF15,
  74                .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
  75                },
  76 };
  77
  78 static struct isp1760_platform_data isp1760_priv = {
  79         .is_isp1761 = 0,
  80         .port1_disable = 0,
  81         .bus_width_16 = 1,
  82         .port1_otg = 0,
  83         .analog_oc = 0,
  84         .dack_polarity_high = 0,
  85         .dreq_polarity_high = 0,
  86 };
  87
  88 static struct platform_device bfin_isp1760_device = {
  89         .name = "isp1760-hcd",
  90         .id = 0,
  91         .dev = {
  92                 .platform_data = &isp1760_priv,
  93                 },
  94         .num_resources = ARRAY_SIZE(bfin_isp1760_resources),
  95         .resource = bfin_isp1760_resources,
  96 };
  97 #endif
  98
  99 static struct resource bfin_i2c_pca_resources[] = {
 100         {
 101          .name = "pca9564-regs",
 102          .start = 0x2C000000,
 103          .end = 0x2C000000 + 16,
 104          .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
 105          }, {
 106
 107              .start = IRQ_PF8,
 108              .end = IRQ_PF8,
 109              .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
 110              },
 111 };
 112
 113 struct i2c_pca9564_pf_platform_data pca9564_platform_data = {
 114         .gpio = -1,
 115         .i2c_clock_speed = 330000,
 116         .timeout = HZ,
 117 };
 118
 119 /* PCA9564 I2C Bus driver */
 120 static struct platform_device bfin_i2c_pca_device = {
 121         .name = "i2c-pca-platform",
 122         .id = 0,
 123         .num_resources = ARRAY_SIZE(bfin_i2c_pca_resources),
 124         .resource = bfin_i2c_pca_resources,
 125         .dev = {
 126                 .platform_data = &pca9564_platform_data,
 127                 }
 128 };
 129
 130 /* I2C devices fitted. */
 131 static struct i2c_board_info acvilon_i2c_devs[] __initdata = {
 132         {
 133          I2C_BOARD_INFO("ds1339", 0x68),
 134          },
 135         {
 136          I2C_BOARD_INFO("tcn75", 0x49),
 137          },
 138 };
 139
 140 #if defined(CONFIG_MTD_PLATRAM) || defined(CONFIG_MTD_PLATRAM_MODULE)
 141 static struct platdata_mtd_ram mtd_ram_data = {
 142         .mapname = "rootfs(RAM)",
 143         .bankwidth = 4,
 144 };
 145
 146 static struct resource mtd_ram_resource = {
 147         .start = 0x4000000,
 148         .end = 0x5ffffff,
 149         .flags = IORESOURCE_MEM,
 150 };
 151
 152 static struct platform_device mtd_ram_device = {
 153         .name = "mtd-ram",
 154         .id = 0,
 155         .dev = {
 156                 .platform_data = &mtd_ram_data,
 157                 },
 158         .num_resources = 1,
 159         .resource = &mtd_ram_resource,
 160 };
 161 #endif
 162
 163 #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
 164 #include <linux/smsc911x.h>
 165 static struct resource smsc911x_resources[] = {
 166         {
 167          .name = "smsc911x-memory",
 168          .start = 0x28000000,
 169          .end = 0x28000000 + 0xFF,
 170          .flags = IORESOURCE_MEM,
 171          },
 172         {
 173          .start = IRQ_PF7,
 174          .end = IRQ_PF7,
 175          .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
 176          },
 177 };
 178
 179 static struct smsc911x_platform_config smsc911x_config = {
 180         .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
 181         .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
 182         .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
 183         .phy_interface = PHY_INTERFACE_MODE_MII,
 184 };
 185
 186 static struct platform_device smsc911x_device = {
 187         .name = "smsc911x",
 188         .id = 0,
 189         .num_resources = ARRAY_SIZE(smsc911x_resources),
 190         .resource = smsc911x_resources,
 191         .dev = {
 192                 .platform_data = &smsc911x_config,
 193                 },
 194 };
 195 #endif
 196
 197 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
 198 #ifdef CONFIG_SERIAL_BFIN_UART0
 199 static struct resource bfin_uart0_resources[] = {
 200         {
 201          .start = BFIN_UART_THR,
 202          .end = BFIN_UART_GCTL + 2,
 203          .flags = IORESOURCE_MEM,
 204          },
 205         {
 206          .start = IRQ_UART_RX,
 207          .end = IRQ_UART_RX + 1,
 208          .flags = IORESOURCE_IRQ,
 209          },
 210         {
 211          .start = IRQ_UART_ERROR,
 212          .end = IRQ_UART_ERROR,
 213          .flags = IORESOURCE_IRQ,
 214          },
 215         {
 216          .start = CH_UART_TX,
 217          .end = CH_UART_TX,
 218          .flags = IORESOURCE_DMA,
 219          },
 220         {
 221          .start = CH_UART_RX,
 222          .end = CH_UART_RX,
 223          .flags = IORESOURCE_DMA,
 224          },
 225 };
 226
 227 static unsigned short bfin_uart0_peripherals[] = {
 228         P_UART0_TX, P_UART0_RX, 0
 229 };
 230
 231 static struct platform_device bfin_uart0_device = {
 232         .name = "bfin-uart",
 233         .id = 0,
 234         .num_resources = ARRAY_SIZE(bfin_uart0_resources),
 235         .resource = bfin_uart0_resources,
 236         .dev = {
 237                 /* Passed to driver */
 238                 .platform_data = &bfin_uart0_peripherals,
 239                 },
 240 };
 241 #endif
 242 #endif
 243
 244 #if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
 245
 246 const char *part_probes[] = { "cmdlinepart", NULL };
 247
 248 static struct mtd_partition bfin_plat_nand_partitions[] = {
 249         {
 250          .name = "params(nand)",
 251          .size = 32 * 1024 * 1024,
 252          .offset = 0,
 253          }, {
 254              .name = "userfs(nand)",
 255              .size = MTDPART_SIZ_FULL,
 256              .offset = MTDPART_OFS_APPEND,
 257              },
 258 };
 259
 260 #define BFIN_NAND_PLAT_CLE 2
 261 #define BFIN_NAND_PLAT_ALE 3
 262
 263 static void bfin_plat_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
 264                                     unsigned int ctrl)
 265 {
 266         struct nand_chip *this = mtd->priv;
 267
 268         if (cmd == NAND_CMD_NONE)
 269                 return;
 270
 271         if (ctrl & NAND_CLE)
 272                 writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_CLE));
 273         else
 274                 writeb(cmd, this->IO_ADDR_W + (1 << BFIN_NAND_PLAT_ALE));
 275 }
 276
 277 #define BFIN_NAND_PLAT_READY GPIO_PF10
 278 static int bfin_plat_nand_dev_ready(struct mtd_info *mtd)
 279 {
 280         return gpio_get_value(BFIN_NAND_PLAT_READY);
 281 }
 282
 283 static struct platform_nand_data bfin_plat_nand_data = {
 284         .chip = {
 285                  .nr_chips = 1,
 286                  .chip_delay = 30,
 287                  .part_probe_types = part_probes,
 288                  .partitions = bfin_plat_nand_partitions,
 289                  .nr_partitions = ARRAY_SIZE(bfin_plat_nand_partitions),
 290                  },
 291         .ctrl = {
 292                  .cmd_ctrl = bfin_plat_nand_cmd_ctrl,
 293                  .dev_ready = bfin_plat_nand_dev_ready,
 294                  },
 295 };
 296
 297 #define MAX(x, y) (x > y ? x : y)
 298 static struct resource bfin_plat_nand_resources = {
 299         .start = 0x24000000,
 300         .end = 0x24000000 + (1 << MAX(BFIN_NAND_PLAT_CLE, BFIN_NAND_PLAT_ALE)),
 301         .flags = IORESOURCE_MEM,
 302 };
 303
 304 static struct platform_device bfin_async_nand_device = {
 305         .name = "gen_nand",
 306         .id = -1,
 307         .num_resources = 1,
 308         .resource = &bfin_plat_nand_resources,
 309         .dev = {
 310                 .platform_data = &bfin_plat_nand_data,
 311                 },
 312 };
 313
 314 static void bfin_plat_nand_init(void)
 315 {
 316         gpio_request(BFIN_NAND_PLAT_READY, "bfin_nand_plat");
 317 }
 318 #else
 319 static void bfin_plat_nand_init(void)
 320 {
 321 }
 322 #endif
 323
 324 #if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE)
 325 static struct mtd_partition bfin_spi_dataflash_partitions[] = {
 326         {
 327          .name = "bootloader",
 328          .size = 0x4200,
 329          .offset = 0,
 330          .mask_flags = MTD_CAP_ROM},
 331         {
 332          .name = "u-boot",
 333          .size = 0x42000,
 334          .offset = MTDPART_OFS_APPEND,
 335          },
 336         {
 337          .name = "u-boot(params)",
 338          .size = 0x4200,
 339          .offset = MTDPART_OFS_APPEND,
 340          },
 341         {
 342          .name = "kernel",
 343          .size = 0x294000,
 344          .offset = MTDPART_OFS_APPEND,
 345          },
 346         {
 347          .name = "params",
 348          .size = 0x42000,
 349          .offset = MTDPART_OFS_APPEND,
 350          },
 351         {
 352          .name = "rootfs",
 353          .size = MTDPART_SIZ_FULL,
 354          .offset = MTDPART_OFS_APPEND,
 355          }
 356 };
 357
 358 static struct flash_platform_data bfin_spi_dataflash_data = {
 359         .name = "SPI Dataflash",
 360         .parts = bfin_spi_dataflash_partitions,
 361         .nr_parts = ARRAY_SIZE(bfin_spi_dataflash_partitions),
 362 };
 363
 364 /* DataFlash chip */
 365 static struct bfin5xx_spi_chip data_flash_chip_info = {
 366         .enable_dma = 0,        /* use dma transfer with this chip */
 367 };
 368 #endif
 369
 370 #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
 371 /* SPI (0) */
 372 static struct resource bfin_spi0_resource[] = {
 373         [0] = {
 374                .start = SPI0_REGBASE,
 375                .end = SPI0_REGBASE + 0xFF,
 376                .flags = IORESOURCE_MEM,
 377                },
 378         [1] = {
 379                .start = CH_SPI,
 380                .end = CH_SPI,
 381                .flags = IORESOURCE_DMA,
 382                },
 383         [2] = {
 384                .start = IRQ_SPI,
 385                .end = IRQ_SPI,
 386                .flags = IORESOURCE_IRQ,
 387                },
 388 };
 389
 390 /* SPI controller data */
 391 static struct bfin5xx_spi_master bfin_spi0_info = {
 392         .num_chipselect = 8,
 393         .enable_dma = 1,        /* master has the ability to do dma transfer */
 394         .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
 395 };
 396
 397 static struct platform_device bfin_spi0_device = {
 398         .name = "bfin-spi",
 399         .id = 0,                /* Bus number */
 400         .num_resources = ARRAY_SIZE(bfin_spi0_resource),
 401         .resource = bfin_spi0_resource,
 402         .dev = {
 403                 .platform_data = &bfin_spi0_info,       /* Passed to driver */
 404                 },
 405 };
 406 #endif
 407
 408 static struct spi_board_info bfin_spi_board_info[] __initdata = {
 409 #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
 410         {
 411          .modalias = "spidev",
 412          .max_speed_hz = 3125000,       /* max spi clock (SCK) speed in HZ */
 413          .bus_num = 0,
 414          .chip_select = 3,
 415          },
 416 #endif
 417 #if defined(CONFIG_MTD_DATAFLASH) || defined(CONFIG_MTD_DATAFLASH_MODULE)
 418         {                       /* DataFlash chip */
 419          .modalias = "mtd_dataflash",
 420          .max_speed_hz = 33250000,      /* max spi clock (SCK) speed in HZ */
 421          .bus_num = 0,          /* Framework bus number */
 422          .chip_select = 2,      /* Framework chip select */
 423          .platform_data = &bfin_spi_dataflash_data,
 424          .controller_data = &data_flash_chip_info,
 425          .mode = SPI_MODE_3,
 426          },
 427 #endif
 428 };
 429
 430 static struct resource bfin_gpios_resources = {
 431         .start = 31,
 432 /*      .end   = MAX_BLACKFIN_GPIOS - 1, */
 433         .end = 32,
 434         .flags = IORESOURCE_IRQ,
 435 };
 436
 437 static struct platform_device bfin_gpios_device = {
 438         .name = "simple-gpio",
 439         .id = -1,
 440         .num_resources = 1,
 441         .resource = &bfin_gpios_resources,
 442 };
 443
 444 static const unsigned int cclk_vlev_datasheet[] = {
 445         VRPAIR(VLEV_085, 250000000),
 446         VRPAIR(VLEV_090, 300000000),
 447         VRPAIR(VLEV_095, 313000000),
 448         VRPAIR(VLEV_100, 350000000),
 449         VRPAIR(VLEV_105, 400000000),
 450         VRPAIR(VLEV_110, 444000000),
 451         VRPAIR(VLEV_115, 450000000),
 452         VRPAIR(VLEV_120, 475000000),
 453         VRPAIR(VLEV_125, 500000000),
 454         VRPAIR(VLEV_130, 600000000),
 455 };
 456
 457 static struct bfin_dpmc_platform_data bfin_dmpc_vreg_data = {
 458         .tuple_tab = cclk_vlev_datasheet,
 459         .tabsize = ARRAY_SIZE(cclk_vlev_datasheet),
 460         .vr_settling_time = 25 /* us */ ,
 461 };
 462
 463 static struct platform_device bfin_dpmc = {
 464         .name = "bfin dpmc",
 465         .dev = {
 466                 .platform_data = &bfin_dmpc_vreg_data,
 467                 },
 468 };
 469
 470 static struct platform_device *acvilon_devices[] __initdata = {
 471         &bfin_dpmc,
 472
 473 #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
 474         &bfin_spi0_device,
 475 #endif
 476
 477 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
 478 #ifdef CONFIG_SERIAL_BFIN_UART0
 479         &bfin_uart0_device,
 480 #endif
 481 #endif
 482
 483         &bfin_gpios_device,
 484
 485 #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
 486         &smsc911x_device,
 487 #endif
 488
 489         &bfin_i2c_pca_device,
 490
 491 #if defined(CONFIG_MTD_NAND_PLATFORM) || defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
 492         &bfin_async_nand_device,
 493 #endif
 494
 495 #if defined(CONFIG_MTD_PLATRAM) || defined(CONFIG_MTD_PLATRAM_MODULE)
 496         &mtd_ram_device,
 497 #endif
 498
 499 };
 500
 501 static int __init acvilon_init(void)
 502 {
 503         int ret;
 504
 505         printk(KERN_INFO "%s(): registering device resources\n", __func__);
 506
 507         bfin_plat_nand_init();
 508         ret =
 509             platform_add_devices(acvilon_devices, ARRAY_SIZE(acvilon_devices));
 510         if (ret < 0)
 511                 return ret;
 512
 513         i2c_register_board_info(0, acvilon_i2c_devs,
 514                                 ARRAY_SIZE(acvilon_i2c_devs));
 515
 516         bfin_write_FIO0_FLAG_C(1 << 14);
 517         msleep(5);
 518         bfin_write_FIO0_FLAG_S(1 << 14);
 519
 520         spi_register_board_info(bfin_spi_board_info,
 521                                 ARRAY_SIZE(bfin_spi_board_info));
 522         return 0;
 523 }
 524
 525 arch_initcall(acvilon_init);
 526
 527 static struct platform_device *acvilon_early_devices[] __initdata = {
 528 #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
 529 #ifdef CONFIG_SERIAL_BFIN_UART0
 530         &bfin_uart0_device,
 531 #endif
 532 #endif
 533 };
 534
 535 void __init native_machine_early_platform_add_devices(void)
 536 {
 537         printk(KERN_INFO "register early platform devices\n");
 538         early_platform_add_devices(acvilon_early_devices,
 539                                    ARRAY_SIZE(acvilon_early_devices));
 540 }