2 * Copyright 2007-2008 Analog Devices Inc.
4 * Licensed under the GPL-2 or later.
10 #include <asm/blackfin.h>
11 #include <asm/irqflags.h>
13 /* Writing to PLL_CTL initiates a PLL relock sequence. */
14 static __inline__ void bfin_write_PLL_CTL(unsigned int val)
16 unsigned long flags, iwr0, iwr1, iwr2;
18 if (val == bfin_read_PLL_CTL())
21 flags = hard_local_irq_save();
22 /* Enable the PLL Wakeup bit in SIC IWR */
23 iwr0 = bfin_read32(SIC_IWR0);
24 iwr1 = bfin_read32(SIC_IWR1);
25 iwr2 = bfin_read32(SIC_IWR2);
26 /* Only allow PPL Wakeup) */
27 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
28 bfin_write32(SIC_IWR1, 0);
29 bfin_write32(SIC_IWR2, 0);
31 bfin_write16(PLL_CTL, val);
35 bfin_write32(SIC_IWR0, iwr0);
36 bfin_write32(SIC_IWR1, iwr1);
37 bfin_write32(SIC_IWR2, iwr2);
38 hard_local_irq_restore(flags);
41 /* Writing to VR_CTL initiates a PLL relock sequence. */
42 static __inline__ void bfin_write_VR_CTL(unsigned int val)
44 unsigned long flags, iwr0, iwr1, iwr2;
46 if (val == bfin_read_VR_CTL())
49 flags = hard_local_irq_save();
50 /* Enable the PLL Wakeup bit in SIC IWR */
51 iwr0 = bfin_read32(SIC_IWR0);
52 iwr1 = bfin_read32(SIC_IWR1);
53 iwr2 = bfin_read32(SIC_IWR2);
54 /* Only allow PPL Wakeup) */
55 bfin_write32(SIC_IWR0, IWR_ENABLE(0));
56 bfin_write32(SIC_IWR1, 0);
57 bfin_write32(SIC_IWR2, 0);
59 bfin_write16(VR_CTL, val);
63 bfin_write32(SIC_IWR0, iwr0);
64 bfin_write32(SIC_IWR1, iwr1);
65 bfin_write32(SIC_IWR2, iwr2);
66 hard_local_irq_restore(flags);
69 #endif /* _MACH_PLL_H */