arch/blackfin/mach-bf548/include/mach/pll.h

   1 /*
   2  * Copyright 2007-2008 Analog Devices Inc.
   3  *
   4  * Licensed under the GPL-2 or later.
   5  */
   6
   7 #ifndef _MACH_PLL_H
   8 #define _MACH_PLL_H
   9
  10 #include <asm/blackfin.h>
  11 #include <asm/irqflags.h>
  12
  13 /* Writing to PLL_CTL initiates a PLL relock sequence. */
  14 static __inline__ void bfin_write_PLL_CTL(unsigned int val)
  15 {
  16         unsigned long flags, iwr0, iwr1, iwr2;
  17
  18         if (val == bfin_read_PLL_CTL())
  19                 return;
  20
  21         flags = hard_local_irq_save();
  22         /* Enable the PLL Wakeup bit in SIC IWR */
  23         iwr0 = bfin_read32(SIC_IWR0);
  24         iwr1 = bfin_read32(SIC_IWR1);
  25         iwr2 = bfin_read32(SIC_IWR2);
  26         /* Only allow PPL Wakeup) */
  27         bfin_write32(SIC_IWR0, IWR_ENABLE(0));
  28         bfin_write32(SIC_IWR1, 0);
  29         bfin_write32(SIC_IWR2, 0);
  30
  31         bfin_write16(PLL_CTL, val);
  32         SSYNC();
  33         asm("IDLE;");
  34
  35         bfin_write32(SIC_IWR0, iwr0);
  36         bfin_write32(SIC_IWR1, iwr1);
  37         bfin_write32(SIC_IWR2, iwr2);
  38         hard_local_irq_restore(flags);
  39 }
  40
  41 /* Writing to VR_CTL initiates a PLL relock sequence. */
  42 static __inline__ void bfin_write_VR_CTL(unsigned int val)
  43 {
  44         unsigned long flags, iwr0, iwr1, iwr2;
  45
  46         if (val == bfin_read_VR_CTL())
  47                 return;
  48
  49         flags = hard_local_irq_save();
  50         /* Enable the PLL Wakeup bit in SIC IWR */
  51         iwr0 = bfin_read32(SIC_IWR0);
  52         iwr1 = bfin_read32(SIC_IWR1);
  53         iwr2 = bfin_read32(SIC_IWR2);
  54         /* Only allow PPL Wakeup) */
  55         bfin_write32(SIC_IWR0, IWR_ENABLE(0));
  56         bfin_write32(SIC_IWR1, 0);
  57         bfin_write32(SIC_IWR2, 0);
  58
  59         bfin_write16(VR_CTL, val);
  60         SSYNC();
  61         asm("IDLE;");
  62
  63         bfin_write32(SIC_IWR0, iwr0);
  64         bfin_write32(SIC_IWR1, iwr1);
  65         bfin_write32(SIC_IWR2, iwr2);
  66         hard_local_irq_restore(flags);
  67 }
  68
  69 #endif /* _MACH_PLL_H */