arch/blackfin/kernel/setup.c

   1 /*
   2  * Copyright 2004-2010 Analog Devices Inc.
   3  *
   4  * Licensed under the GPL-2 or later.
   5  */
   6
   7 #include <linux/delay.h>
   8 #include <linux/console.h>
   9 #include <linux/bootmem.h>
  10 #include <linux/seq_file.h>
  11 #include <linux/cpu.h>
  12 #include <linux/mm.h>
  13 #include <linux/module.h>
  14 #include <linux/tty.h>
  15 #include <linux/pfn.h>
  16
  17 #ifdef CONFIG_MTD_UCLINUX
  18 #include <linux/mtd/map.h>
  19 #include <linux/ext2_fs.h>
  20 #include <linux/cramfs_fs.h>
  21 #include <linux/romfs_fs.h>
  22 #endif
  23
  24 #include <asm/cplb.h>
  25 #include <asm/cacheflush.h>
  26 #include <asm/blackfin.h>
  27 #include <asm/cplbinit.h>
  28 #include <asm/div64.h>
  29 #include <asm/cpu.h>
  30 #include <asm/fixed_code.h>
  31 #include <asm/early_printk.h>
  32
  33 u16 _bfin_swrst;
  34 EXPORT_SYMBOL(_bfin_swrst);
  35
  36 unsigned long memory_start, memory_end, physical_mem_end;
  37 unsigned long _rambase, _ramstart, _ramend;
  38 unsigned long reserved_mem_dcache_on;
  39 unsigned long reserved_mem_icache_on;
  40 EXPORT_SYMBOL(memory_start);
  41 EXPORT_SYMBOL(memory_end);
  42 EXPORT_SYMBOL(physical_mem_end);
  43 EXPORT_SYMBOL(_ramend);
  44 EXPORT_SYMBOL(reserved_mem_dcache_on);
  45
  46 #ifdef CONFIG_MTD_UCLINUX
  47 extern struct map_info uclinux_ram_map;
  48 unsigned long memory_mtd_end, memory_mtd_start, mtd_size;
  49 unsigned long _ebss;
  50 EXPORT_SYMBOL(memory_mtd_end);
  51 EXPORT_SYMBOL(memory_mtd_start);
  52 EXPORT_SYMBOL(mtd_size);
  53 #endif
  54
  55 char __initdata command_line[COMMAND_LINE_SIZE];
  56 void __initdata *init_retx, *init_saved_retx, *init_saved_seqstat,
  57         *init_saved_icplb_fault_addr, *init_saved_dcplb_fault_addr;
  58
  59 /* boot memmap, for parsing "memmap=" */
  60 #define BFIN_MEMMAP_MAX         128 /* number of entries in bfin_memmap */
  61 #define BFIN_MEMMAP_RAM         1
  62 #define BFIN_MEMMAP_RESERVED    2
  63 static struct bfin_memmap {
  64         int nr_map;
  65         struct bfin_memmap_entry {
  66                 unsigned long long addr; /* start of memory segment */
  67                 unsigned long long size;
  68                 unsigned long type;
  69         } map[BFIN_MEMMAP_MAX];
  70 } bfin_memmap __initdata;
  71
  72 /* for memmap sanitization */
  73 struct change_member {
  74         struct bfin_memmap_entry *pentry; /* pointer to original entry */
  75         unsigned long long addr; /* address for this change point */
  76 };
  77 static struct change_member change_point_list[2*BFIN_MEMMAP_MAX] __initdata;
  78 static struct change_member *change_point[2*BFIN_MEMMAP_MAX] __initdata;
  79 static struct bfin_memmap_entry *overlap_list[BFIN_MEMMAP_MAX] __initdata;
  80 static struct bfin_memmap_entry new_map[BFIN_MEMMAP_MAX] __initdata;
  81
  82 DEFINE_PER_CPU(struct blackfin_cpudata, cpu_data);
  83
  84 static int early_init_clkin_hz(char *buf);
  85
  86 #if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
  87 void __init generate_cplb_tables(void)
  88 {
  89         unsigned int cpu;
  90
  91         generate_cplb_tables_all();
  92         /* Generate per-CPU I&D CPLB tables */
  93         for (cpu = 0; cpu < num_possible_cpus(); ++cpu)
  94                 generate_cplb_tables_cpu(cpu);
  95 }
  96 #endif
  97
  98 void __cpuinit bfin_setup_caches(unsigned int cpu)
  99 {
 100 #ifdef CONFIG_BFIN_ICACHE
 101         bfin_icache_init(icplb_tbl[cpu]);
 102 #endif
 103
 104 #ifdef CONFIG_BFIN_DCACHE
 105         bfin_dcache_init(dcplb_tbl[cpu]);
 106 #endif
 107
 108         /*
 109          * In cache coherence emulation mode, we need to have the
 110          * D-cache enabled before running any atomic operation which
 111          * might involve cache invalidation (i.e. spinlock, rwlock).
 112          * So printk's are deferred until then.
 113          */
 114 #ifdef CONFIG_BFIN_ICACHE
 115         printk(KERN_INFO "Instruction Cache Enabled for CPU%u\n", cpu);
 116         printk(KERN_INFO "  External memory:"
 117 # ifdef CONFIG_BFIN_EXTMEM_ICACHEABLE
 118                " cacheable"
 119 # else
 120                " uncacheable"
 121 # endif
 122                " in instruction cache\n");
 123         if (L2_LENGTH)
 124                 printk(KERN_INFO "  L2 SRAM        :"
 125 # ifdef CONFIG_BFIN_L2_ICACHEABLE
 126                        " cacheable"
 127 # else
 128                        " uncacheable"
 129 # endif
 130                        " in instruction cache\n");
 131
 132 #else
 133         printk(KERN_INFO "Instruction Cache Disabled for CPU%u\n", cpu);
 134 #endif
 135
 136 #ifdef CONFIG_BFIN_DCACHE
 137         printk(KERN_INFO "Data Cache Enabled for CPU%u\n", cpu);
 138         printk(KERN_INFO "  External memory:"
 139 # if defined CONFIG_BFIN_EXTMEM_WRITEBACK
 140                " cacheable (write-back)"
 141 # elif defined CONFIG_BFIN_EXTMEM_WRITETHROUGH
 142                " cacheable (write-through)"
 143 # else
 144                " uncacheable"
 145 # endif
 146                " in data cache\n");
 147         if (L2_LENGTH)
 148                 printk(KERN_INFO "  L2 SRAM        :"
 149 # if defined CONFIG_BFIN_L2_WRITEBACK
 150                        " cacheable (write-back)"
 151 # elif defined CONFIG_BFIN_L2_WRITETHROUGH
 152                        " cacheable (write-through)"
 153 # else
 154                        " uncacheable"
 155 # endif
 156                        " in data cache\n");
 157 #else
 158         printk(KERN_INFO "Data Cache Disabled for CPU%u\n", cpu);
 159 #endif
 160 }
 161
 162 void __cpuinit bfin_setup_cpudata(unsigned int cpu)
 163 {
 164         struct blackfin_cpudata *cpudata = &per_cpu(cpu_data, cpu);
 165
 166         cpudata->idle = current;
 167         cpudata->imemctl = bfin_read_IMEM_CONTROL();
 168         cpudata->dmemctl = bfin_read_DMEM_CONTROL();
 169 }
 170
 171 void __init bfin_cache_init(void)
 172 {
 173 #if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
 174         generate_cplb_tables();
 175 #endif
 176         bfin_setup_caches(0);
 177 }
 178
 179 void __init bfin_relocate_l1_mem(void)
 180 {
 181         unsigned long text_l1_len = (unsigned long)_text_l1_len;
 182         unsigned long data_l1_len = (unsigned long)_data_l1_len;
 183         unsigned long data_b_l1_len = (unsigned long)_data_b_l1_len;
 184         unsigned long l2_len = (unsigned long)_l2_len;
 185
 186         early_shadow_stamp();
 187
 188         /*
 189          * due to the ALIGN(4) in the arch/blackfin/kernel/vmlinux.lds.S
 190          * we know that everything about l1 text/data is nice and aligned,
 191          * so copy by 4 byte chunks, and don't worry about overlapping
 192          * src/dest.
 193          *
 194          * We can't use the dma_memcpy functions, since they can call
 195          * scheduler functions which might be in L1 :( and core writes
 196          * into L1 instruction cause bad access errors, so we are stuck,
 197          * we are required to use DMA, but can't use the common dma
 198          * functions. We can't use memcpy either - since that might be
 199          * going to be in the relocated L1
 200          */
 201
 202         blackfin_dma_early_init();
 203
 204         /* if necessary, copy L1 text to L1 instruction SRAM */
 205         if (L1_CODE_LENGTH && text_l1_len)
 206                 early_dma_memcpy(_stext_l1, _text_l1_lma, text_l1_len);
 207
 208         /* if necessary, copy L1 data to L1 data bank A SRAM */
 209         if (L1_DATA_A_LENGTH && data_l1_len)
 210                 early_dma_memcpy(_sdata_l1, _data_l1_lma, data_l1_len);
 211
 212         /* if necessary, copy L1 data B to L1 data bank B SRAM */
 213         if (L1_DATA_B_LENGTH && data_b_l1_len)
 214                 early_dma_memcpy(_sdata_b_l1, _data_b_l1_lma, data_b_l1_len);
 215
 216         early_dma_memcpy_done();
 217
 218 #if defined(CONFIG_SMP) && defined(CONFIG_ICACHE_FLUSH_L1)
 219         blackfin_iflush_l1_entry[0] = (unsigned long)blackfin_icache_flush_range_l1;
 220 #endif
 221
 222         /* if necessary, copy L2 text/data to L2 SRAM */
 223         if (L2_LENGTH && l2_len)
 224                 memcpy(_stext_l2, _l2_lma, l2_len);
 225 }
 226
 227 #ifdef CONFIG_SMP
 228 void __init bfin_relocate_coreb_l1_mem(void)
 229 {
 230         unsigned long text_l1_len = (unsigned long)_text_l1_len;
 231         unsigned long data_l1_len = (unsigned long)_data_l1_len;
 232         unsigned long data_b_l1_len = (unsigned long)_data_b_l1_len;
 233
 234         blackfin_dma_early_init();
 235
 236         /* if necessary, copy L1 text to L1 instruction SRAM */
 237         if (L1_CODE_LENGTH && text_l1_len)
 238                 early_dma_memcpy((void *)COREB_L1_CODE_START, _text_l1_lma,
 239                                 text_l1_len);
 240
 241         /* if necessary, copy L1 data to L1 data bank A SRAM */
 242         if (L1_DATA_A_LENGTH && data_l1_len)
 243                 early_dma_memcpy((void *)COREB_L1_DATA_A_START, _data_l1_lma,
 244                                 data_l1_len);
 245
 246         /* if necessary, copy L1 data B to L1 data bank B SRAM */
 247         if (L1_DATA_B_LENGTH && data_b_l1_len)
 248                 early_dma_memcpy((void *)COREB_L1_DATA_B_START, _data_b_l1_lma,
 249                                 data_b_l1_len);
 250
 251         early_dma_memcpy_done();
 252
 253 #ifdef CONFIG_ICACHE_FLUSH_L1
 254         blackfin_iflush_l1_entry[1] = (unsigned long)blackfin_icache_flush_range_l1 -
 255                         (unsigned long)_stext_l1 + COREB_L1_CODE_START;
 256 #endif
 257 }
 258 #endif
 259
 260 #ifdef CONFIG_ROMKERNEL
 261 void __init bfin_relocate_xip_data(void)
 262 {
 263         early_shadow_stamp();
 264
 265         memcpy(_sdata, _data_lma, (unsigned long)_data_len - THREAD_SIZE + sizeof(struct thread_info));
 266         memcpy(_sinitdata, _init_data_lma, (unsigned long)_init_data_len);
 267 }
 268 #endif
 269
 270 /* add_memory_region to memmap */
 271 static void __init add_memory_region(unsigned long long start,
 272                               unsigned long long size, int type)
 273 {
 274         int i;
 275
 276         i = bfin_memmap.nr_map;
 277
 278         if (i == BFIN_MEMMAP_MAX) {
 279                 printk(KERN_ERR "Ooops! Too many entries in the memory map!\n");
 280                 return;
 281         }
 282
 283         bfin_memmap.map[i].addr = start;
 284         bfin_memmap.map[i].size = size;
 285         bfin_memmap.map[i].type = type;
 286         bfin_memmap.nr_map++;
 287 }
 288
 289 /*
 290  * Sanitize the boot memmap, removing overlaps.
 291  */
 292 static int __init sanitize_memmap(struct bfin_memmap_entry *map, int *pnr_map)
 293 {
 294         struct change_member *change_tmp;
 295         unsigned long current_type, last_type;
 296         unsigned long long last_addr;
 297         int chgidx, still_changing;
 298         int overlap_entries;
 299         int new_entry;
 300         int old_nr, new_nr, chg_nr;
 301         int i;
 302
 303         /*
 304                 Visually we're performing the following (1,2,3,4 = memory types)
 305
 306                 Sample memory map (w/overlaps):
 307                    ____22__________________
 308                    ______________________4_
 309                    ____1111________________
 310                    _44_____________________
 311                    11111111________________
 312                    ____________________33__
 313                    ___________44___________
 314                    __________33333_________
 315                    ______________22________
 316                    ___________________2222_
 317                    _________111111111______
 318                    _____________________11_
 319                    _________________4______
 320
 321                 Sanitized equivalent (no overlap):
 322                    1_______________________
 323                    _44_____________________
 324                    ___1____________________
 325                    ____22__________________
 326                    ______11________________
 327                    _________1______________
 328                    __________3_____________
 329                    ___________44___________
 330                    _____________33_________
 331                    _______________2________
 332                    ________________1_______
 333                    _________________4______
 334                    ___________________2____
 335                    ____________________33__
 336                    ______________________4_
 337         */
 338         /* if there's only one memory region, don't bother */
 339         if (*pnr_map < 2)
 340                 return -1;
 341
 342         old_nr = *pnr_map;
 343
 344         /* bail out if we find any unreasonable addresses in memmap */
 345         for (i = 0; i < old_nr; i++)
 346                 if (map[i].addr + map[i].size < map[i].addr)
 347                         return -1;
 348
 349         /* create pointers for initial change-point information (for sorting) */
 350         for (i = 0; i < 2*old_nr; i++)
 351                 change_point[i] = &change_point_list[i];
 352
 353         /* record all known change-points (starting and ending addresses),
 354            omitting those that are for empty memory regions */
 355         chgidx = 0;
 356         for (i = 0; i < old_nr; i++) {
 357                 if (map[i].size != 0) {
 358                         change_point[chgidx]->addr = map[i].addr;
 359                         change_point[chgidx++]->pentry = &map[i];
 360                         change_point[chgidx]->addr = map[i].addr + map[i].size;
 361                         change_point[chgidx++]->pentry = &map[i];
 362                 }
 363         }
 364         chg_nr = chgidx;        /* true number of change-points */
 365
 366         /* sort change-point list by memory addresses (low -> high) */
 367         still_changing = 1;
 368         while (still_changing) {
 369                 still_changing = 0;
 370                 for (i = 1; i < chg_nr; i++) {
 371                         /* if <current_addr> > <last_addr>, swap */
 372                         /* or, if current=<start_addr> & last=<end_addr>, swap */
 373                         if ((change_point[i]->addr < change_point[i-1]->addr) ||
 374                                 ((change_point[i]->addr == change_point[i-1]->addr) &&
 375                                  (change_point[i]->addr == change_point[i]->pentry->addr) &&
 376                                  (change_point[i-1]->addr != change_point[i-1]->pentry->addr))
 377                            ) {
 378                                 change_tmp = change_point[i];
 379                                 change_point[i] = change_point[i-1];
 380                                 change_point[i-1] = change_tmp;
 381                                 still_changing = 1;
 382                         }
 383                 }
 384         }
 385
 386         /* create a new memmap, removing overlaps */
 387         overlap_entries = 0;    /* number of entries in the overlap table */
 388         new_entry = 0;          /* index for creating new memmap entries */
 389         last_type = 0;          /* start with undefined memory type */
 390         last_addr = 0;          /* start with 0 as last starting address */
 391         /* loop through change-points, determining affect on the new memmap */
 392         for (chgidx = 0; chgidx < chg_nr; chgidx++) {
 393                 /* keep track of all overlapping memmap entries */
 394                 if (change_point[chgidx]->addr == change_point[chgidx]->pentry->addr) {
 395                         /* add map entry to overlap list (> 1 entry implies an overlap) */
 396                         overlap_list[overlap_entries++] = change_point[chgidx]->pentry;
 397                 } else {
 398                         /* remove entry from list (order independent, so swap with last) */
 399                         for (i = 0; i < overlap_entries; i++) {
 400                                 if (overlap_list[i] == change_point[chgidx]->pentry)
 401                                         overlap_list[i] = overlap_list[overlap_entries-1];
 402                         }
 403                         overlap_entries--;
 404                 }
 405                 /* if there are overlapping entries, decide which "type" to use */
 406                 /* (larger value takes precedence -- 1=usable, 2,3,4,4+=unusable) */
 407                 current_type = 0;
 408                 for (i = 0; i < overlap_entries; i++)
 409                         if (overlap_list[i]->type > current_type)
 410                                 current_type = overlap_list[i]->type;
 411                 /* continue building up new memmap based on this information */
 412                 if (current_type != last_type) {
 413                         if (last_type != 0) {
 414                                 new_map[new_entry].size =
 415                                         change_point[chgidx]->addr - last_addr;
 416                                 /* move forward only if the new size was non-zero */
 417                                 if (new_map[new_entry].size != 0)
 418                                         if (++new_entry >= BFIN_MEMMAP_MAX)
 419                                                 break;  /* no more space left for new entries */
 420                         }
 421                         if (current_type != 0) {
 422                                 new_map[new_entry].addr = change_point[chgidx]->addr;
 423                                 new_map[new_entry].type = current_type;
 424                                 last_addr = change_point[chgidx]->addr;
 425                         }
 426                         last_type = current_type;
 427                 }
 428         }
 429         new_nr = new_entry;     /* retain count for new entries */
 430
 431         /* copy new mapping into original location */
 432         memcpy(map, new_map, new_nr*sizeof(struct bfin_memmap_entry));
 433         *pnr_map = new_nr;
 434
 435         return 0;
 436 }
 437
 438 static void __init print_memory_map(char *who)
 439 {
 440         int i;
 441
 442         for (i = 0; i < bfin_memmap.nr_map; i++) {
 443                 printk(KERN_DEBUG " %s: %016Lx - %016Lx ", who,
 444                         bfin_memmap.map[i].addr,
 445                         bfin_memmap.map[i].addr + bfin_memmap.map[i].size);
 446                 switch (bfin_memmap.map[i].type) {
 447                 case BFIN_MEMMAP_RAM:
 448                         printk(KERN_CONT "(usable)\n");
 449                         break;
 450                 case BFIN_MEMMAP_RESERVED:
 451                         printk(KERN_CONT "(reserved)\n");
 452                         break;
 453                 default:
 454                         printk(KERN_CONT "type %lu\n", bfin_memmap.map[i].type);
 455                         break;
 456                 }
 457         }
 458 }
 459
 460 static __init int parse_memmap(char *arg)
 461 {
 462         unsigned long long start_at, mem_size;
 463
 464         if (!arg)
 465                 return -EINVAL;
 466
 467         mem_size = memparse(arg, &arg);
 468         if (*arg == '@') {
 469                 start_at = memparse(arg+1, &arg);
 470                 add_memory_region(start_at, mem_size, BFIN_MEMMAP_RAM);
 471         } else if (*arg == '$') {
 472                 start_at = memparse(arg+1, &arg);
 473                 add_memory_region(start_at, mem_size, BFIN_MEMMAP_RESERVED);
 474         }
 475
 476         return 0;
 477 }
 478
 479 /*
 480  * Initial parsing of the command line.  Currently, we support:
 481  *  - Controlling the linux memory size: mem=xxx[KMG]
 482  *  - Controlling the physical memory size: max_mem=xxx[KMG][$][#]
 483  *       $ -> reserved memory is dcacheable
 484  *       # -> reserved memory is icacheable
 485  *  - "memmap=XXX[KkmM][@][$]XXX[KkmM]" defines a memory region
 486  *       @ from <start> to <start>+<mem>, type RAM
 487  *       $ from <start> to <start>+<mem>, type RESERVED
 488  */
 489 static __init void parse_cmdline_early(char *cmdline_p)
 490 {
 491         char c = ' ', *to = cmdline_p;
 492         unsigned int memsize;
 493         for (;;) {
 494                 if (c == ' ') {
 495                         if (!memcmp(to, "mem=", 4)) {
 496                                 to += 4;
 497                                 memsize = memparse(to, &to);
 498                                 if (memsize)
 499                                         _ramend = memsize;
 500
 501                         } else if (!memcmp(to, "max_mem=", 8)) {
 502                                 to += 8;
 503                                 memsize = memparse(to, &to);
 504                                 if (memsize) {
 505                                         physical_mem_end = memsize;
 506                                         if (*to != ' ') {
 507                                                 if (*to == '$'
 508                                                     || *(to + 1) == '$')
 509                                                         reserved_mem_dcache_on = 1;
 510                                                 if (*to == '#'
 511                                                     || *(to + 1) == '#')
 512                                                         reserved_mem_icache_on = 1;
 513                                         }
 514                                 }
 515                         } else if (!memcmp(to, "clkin_hz=", 9)) {
 516                                 to += 9;
 517                                 early_init_clkin_hz(to);
 518 #ifdef CONFIG_EARLY_PRINTK
 519                         } else if (!memcmp(to, "earlyprintk=", 12)) {
 520                                 to += 12;
 521                                 setup_early_printk(to);
 522 #endif
 523                         } else if (!memcmp(to, "memmap=", 7)) {
 524                                 to += 7;
 525                                 parse_memmap(to);
 526                         }
 527                 }
 528                 c = *(to++);
 529                 if (!c)
 530                         break;
 531         }
 532 }
 533
 534 /*
 535  * Setup memory defaults from user config.
 536  * The physical memory layout looks like:
 537  *
 538  *  [_rambase, _ramstart]:              kernel image
 539  *  [memory_start, memory_end]:         dynamic memory managed by kernel
 540  *  [memory_end, _ramend]:              reserved memory
 541  *      [memory_mtd_start(memory_end),
 542  *              memory_mtd_start + mtd_size]:   rootfs (if any)
 543  *      [_ramend - DMA_UNCACHED_REGION,
 544  *              _ramend]:                       uncached DMA region
 545  *  [_ramend, physical_mem_end]:        memory not managed by kernel
 546  */
 547 static __init void memory_setup(void)
 548 {
 549 #ifdef CONFIG_MTD_UCLINUX
 550         unsigned long mtd_phys = 0;
 551 #endif
 552         unsigned long max_mem;
 553
 554         _rambase = CONFIG_BOOT_LOAD;
 555         _ramstart = (unsigned long)_end;
 556
 557         if (DMA_UNCACHED_REGION > (_ramend - _ramstart)) {
 558                 console_init();
 559                 panic("DMA region exceeds memory limit: %lu.",
 560                         _ramend - _ramstart);
 561         }
 562         max_mem = memory_end = _ramend - DMA_UNCACHED_REGION;
 563
 564 #if (defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) && ANOMALY_05000263)
 565         /* Due to a Hardware Anomaly we need to limit the size of usable
 566          * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on
 567          * 05000263 - Hardware loop corrupted when taking an ICPLB exception
 568          */
 569 # if (defined(CONFIG_DEBUG_HUNT_FOR_ZERO))
 570         if (max_mem >= 56 * 1024 * 1024)
 571                 max_mem = 56 * 1024 * 1024;
 572 # else
 573         if (max_mem >= 60 * 1024 * 1024)
 574                 max_mem = 60 * 1024 * 1024;
 575 # endif                         /* CONFIG_DEBUG_HUNT_FOR_ZERO */
 576 #endif                          /* ANOMALY_05000263 */
 577
 578
 579 #ifdef CONFIG_MPU
 580         /* Round up to multiple of 4MB */
 581         memory_start = (_ramstart + 0x3fffff) & ~0x3fffff;
 582 #else
 583         memory_start = PAGE_ALIGN(_ramstart);
 584 #endif
 585
 586 #if defined(CONFIG_MTD_UCLINUX)
 587         /* generic memory mapped MTD driver */
 588         memory_mtd_end = memory_end;
 589
 590         mtd_phys = _ramstart;
 591         mtd_size = PAGE_ALIGN(*((unsigned long *)(mtd_phys + 8)));
 592
 593 # if defined(CONFIG_EXT2_FS) || defined(CONFIG_EXT3_FS)
 594         if (*((unsigned short *)(mtd_phys + 0x438)) == EXT2_SUPER_MAGIC)
 595                 mtd_size =
 596                     PAGE_ALIGN(*((unsigned long *)(mtd_phys + 0x404)) << 10);
 597 # endif
 598
 599 # if defined(CONFIG_CRAMFS)
 600         if (*((unsigned long *)(mtd_phys)) == CRAMFS_MAGIC)
 601                 mtd_size = PAGE_ALIGN(*((unsigned long *)(mtd_phys + 0x4)));
 602 # endif
 603
 604 # if defined(CONFIG_ROMFS_FS)
 605         if (((unsigned long *)mtd_phys)[0] == ROMSB_WORD0
 606             && ((unsigned long *)mtd_phys)[1] == ROMSB_WORD1) {
 607                 mtd_size =
 608                     PAGE_ALIGN(be32_to_cpu(((unsigned long *)mtd_phys)[2]));
 609
 610                 /* ROM_FS is XIP, so if we found it, we need to limit memory */
 611                 if (memory_end > max_mem) {
 612                         pr_info("Limiting kernel memory to %liMB due to anomaly 05000263\n", max_mem >> 20);
 613                         memory_end = max_mem;
 614                 }
 615         }
 616 # endif                         /* CONFIG_ROMFS_FS */
 617
 618         /* Since the default MTD_UCLINUX has no magic number, we just blindly
 619          * read 8 past the end of the kernel's image, and look at it.
 620          * When no image is attached, mtd_size is set to a random number
 621          * Do some basic sanity checks before operating on things
 622          */
 623         if (mtd_size == 0 || memory_end <= mtd_size) {
 624                 pr_emerg("Could not find valid ram mtd attached.\n");
 625         } else {
 626                 memory_end -= mtd_size;
 627
 628                 /* Relocate MTD image to the top of memory after the uncached memory area */
 629                 uclinux_ram_map.phys = memory_mtd_start = memory_end;
 630                 uclinux_ram_map.size = mtd_size;
 631                 pr_info("Found mtd parition at 0x%p, (len=0x%lx), moving to 0x%p\n",
 632                         _end, mtd_size, (void *)memory_mtd_start);
 633                 dma_memcpy((void *)uclinux_ram_map.phys, _end, uclinux_ram_map.size);
 634         }
 635 #endif                          /* CONFIG_MTD_UCLINUX */
 636
 637         /* We need lo limit memory, since everything could have a text section
 638          * of userspace in it, and expose anomaly 05000263. If the anomaly
 639          * doesn't exist, or we don't need to - then dont.
 640          */
 641         if (memory_end > max_mem) {
 642                 pr_info("Limiting kernel memory to %liMB due to anomaly 05000263\n", max_mem >> 20);
 643                 memory_end = max_mem;
 644         }
 645
 646 #ifdef CONFIG_MPU
 647 #if defined(CONFIG_ROMFS_ON_MTD) && defined(CONFIG_MTD_ROM)
 648         page_mask_nelts = (((_ramend + ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE -
 649                                         ASYNC_BANK0_BASE) >> PAGE_SHIFT) + 31) / 32;
 650 #else
 651         page_mask_nelts = ((_ramend >> PAGE_SHIFT) + 31) / 32;
 652 #endif
 653         page_mask_order = get_order(3 * page_mask_nelts * sizeof(long));
 654 #endif
 655
 656         init_mm.start_code = (unsigned long)_stext;
 657         init_mm.end_code = (unsigned long)_etext;
 658         init_mm.end_data = (unsigned long)_edata;
 659         init_mm.brk = (unsigned long)0;
 660
 661         printk(KERN_INFO "Board Memory: %ldMB\n", physical_mem_end >> 20);
 662         printk(KERN_INFO "Kernel Managed Memory: %ldMB\n", _ramend >> 20);
 663
 664         printk(KERN_INFO "Memory map:\n"
 665                "  fixedcode = 0x%p-0x%p\n"
 666                "  text      = 0x%p-0x%p\n"
 667                "  rodata    = 0x%p-0x%p\n"
 668                "  bss       = 0x%p-0x%p\n"
 669                "  data      = 0x%p-0x%p\n"
 670                "    stack   = 0x%p-0x%p\n"
 671                "  init      = 0x%p-0x%p\n"
 672                "  available = 0x%p-0x%p\n"
 673 #ifdef CONFIG_MTD_UCLINUX
 674                "  rootfs    = 0x%p-0x%p\n"
 675 #endif
 676 #if DMA_UNCACHED_REGION > 0
 677                "  DMA Zone  = 0x%p-0x%p\n"
 678 #endif
 679                 , (void *)FIXED_CODE_START, (void *)FIXED_CODE_END,
 680                 _stext, _etext,
 681                 __start_rodata, __end_rodata,
 682                 __bss_start, __bss_stop,
 683                 _sdata, _edata,
 684                 (void *)&init_thread_union,
 685                 (void *)((int)(&init_thread_union) + THREAD_SIZE),
 686                 __init_begin, __init_end,
 687                 (void *)_ramstart, (void *)memory_end
 688 #ifdef CONFIG_MTD_UCLINUX
 689                 , (void *)memory_mtd_start, (void *)(memory_mtd_start + mtd_size)
 690 #endif
 691 #if DMA_UNCACHED_REGION > 0
 692                 , (void *)(_ramend - DMA_UNCACHED_REGION), (void *)(_ramend)
 693 #endif
 694                 );
 695 }
 696
 697 /*
 698  * Find the lowest, highest page frame number we have available
 699  */
 700 void __init find_min_max_pfn(void)
 701 {
 702         int i;
 703
 704         max_pfn = 0;
 705         min_low_pfn = memory_end;
 706
 707         for (i = 0; i < bfin_memmap.nr_map; i++) {
 708                 unsigned long start, end;
 709                 /* RAM? */
 710                 if (bfin_memmap.map[i].type != BFIN_MEMMAP_RAM)
 711                         continue;
 712                 start = PFN_UP(bfin_memmap.map[i].addr);
 713                 end = PFN_DOWN(bfin_memmap.map[i].addr +
 714                                 bfin_memmap.map[i].size);
 715                 if (start >= end)
 716                         continue;
 717                 if (end > max_pfn)
 718                         max_pfn = end;
 719                 if (start < min_low_pfn)
 720                         min_low_pfn = start;
 721         }
 722 }
 723
 724 static __init void setup_bootmem_allocator(void)
 725 {
 726         int bootmap_size;
 727         int i;
 728         unsigned long start_pfn, end_pfn;
 729         unsigned long curr_pfn, last_pfn, size;
 730
 731         /* mark memory between memory_start and memory_end usable */
 732         add_memory_region(memory_start,
 733                 memory_end - memory_start, BFIN_MEMMAP_RAM);
 734         /* sanity check for overlap */
 735         sanitize_memmap(bfin_memmap.map, &bfin_memmap.nr_map);
 736         print_memory_map("boot memmap");
 737
 738         /* initialize globals in linux/bootmem.h */
 739         find_min_max_pfn();
 740         /* pfn of the last usable page frame */
 741         if (max_pfn > memory_end >> PAGE_SHIFT)
 742                 max_pfn = memory_end >> PAGE_SHIFT;
 743         /* pfn of last page frame directly mapped by kernel */
 744         max_low_pfn = max_pfn;
 745         /* pfn of the first usable page frame after kernel image*/
 746         if (min_low_pfn < memory_start >> PAGE_SHIFT)
 747                 min_low_pfn = memory_start >> PAGE_SHIFT;
 748
 749         start_pfn = PAGE_OFFSET >> PAGE_SHIFT;
 750         end_pfn = memory_end >> PAGE_SHIFT;
 751
 752         /*
 753          * give all the memory to the bootmap allocator, tell it to put the
 754          * boot mem_map at the start of memory.
 755          */
 756         bootmap_size = init_bootmem_node(NODE_DATA(0),
 757                         memory_start >> PAGE_SHIFT,     /* map goes here */
 758                         start_pfn, end_pfn);
 759
 760         /* register the memmap regions with the bootmem allocator */
 761         for (i = 0; i < bfin_memmap.nr_map; i++) {
 762                 /*
 763                  * Reserve usable memory
 764                  */
 765                 if (bfin_memmap.map[i].type != BFIN_MEMMAP_RAM)
 766                         continue;
 767                 /*
 768                  * We are rounding up the start address of usable memory:
 769                  */
 770                 curr_pfn = PFN_UP(bfin_memmap.map[i].addr);
 771                 if (curr_pfn >= end_pfn)
 772                         continue;
 773                 /*
 774                  * ... and at the end of the usable range downwards:
 775                  */
 776                 last_pfn = PFN_DOWN(bfin_memmap.map[i].addr +
 777                                          bfin_memmap.map[i].size);
 778
 779                 if (last_pfn > end_pfn)
 780                         last_pfn = end_pfn;
 781
 782                 /*
 783                  * .. finally, did all the rounding and playing
 784                  * around just make the area go away?
 785                  */
 786                 if (last_pfn <= curr_pfn)
 787                         continue;
 788
 789                 size = last_pfn - curr_pfn;
 790                 free_bootmem(PFN_PHYS(curr_pfn), PFN_PHYS(size));
 791         }
 792
 793         /* reserve memory before memory_start, including bootmap */
 794         reserve_bootmem(PAGE_OFFSET,
 795                 memory_start + bootmap_size + PAGE_SIZE - 1 - PAGE_OFFSET,
 796                 BOOTMEM_DEFAULT);
 797 }
 798
 799 #define EBSZ_TO_MEG(ebsz) \
 800 ({ \
 801         int meg = 0; \
 802         switch (ebsz & 0xf) { \
 803                 case 0x1: meg =  16; break; \
 804                 case 0x3: meg =  32; break; \
 805                 case 0x5: meg =  64; break; \
 806                 case 0x7: meg = 128; break; \
 807                 case 0x9: meg = 256; break; \
 808                 case 0xb: meg = 512; break; \
 809         } \
 810         meg; \
 811 })
 812 static inline int __init get_mem_size(void)
 813 {
 814 #if defined(EBIU_SDBCTL)
 815 # if defined(BF561_FAMILY)
 816         int ret = 0;
 817         u32 sdbctl = bfin_read_EBIU_SDBCTL();
 818         ret += EBSZ_TO_MEG(sdbctl >>  0);
 819         ret += EBSZ_TO_MEG(sdbctl >>  8);
 820         ret += EBSZ_TO_MEG(sdbctl >> 16);
 821         ret += EBSZ_TO_MEG(sdbctl >> 24);
 822         return ret;
 823 # else
 824         return EBSZ_TO_MEG(bfin_read_EBIU_SDBCTL());
 825 # endif
 826 #elif defined(EBIU_DDRCTL1)
 827         u32 ddrctl = bfin_read_EBIU_DDRCTL1();
 828         int ret = 0;
 829         switch (ddrctl & 0xc0000) {
 830                 case DEVSZ_64:  ret = 64 / 8;
 831                 case DEVSZ_128: ret = 128 / 8;
 832                 case DEVSZ_256: ret = 256 / 8;
 833                 case DEVSZ_512: ret = 512 / 8;
 834         }
 835         switch (ddrctl & 0x30000) {
 836                 case DEVWD_4:  ret *= 2;
 837                 case DEVWD_8:  ret *= 2;
 838                 case DEVWD_16: break;
 839         }
 840         if ((ddrctl & 0xc000) == 0x4000)
 841                 ret *= 2;
 842         return ret;
 843 #endif
 844         BUG();
 845 }
 846
 847 __attribute__((weak))
 848 void __init native_machine_early_platform_add_devices(void)
 849 {
 850 }
 851
 852 void __init setup_arch(char **cmdline_p)
 853 {
 854         unsigned long sclk, cclk;
 855
 856         native_machine_early_platform_add_devices();
 857
 858         enable_shadow_console();
 859
 860         /* Check to make sure we are running on the right processor */
 861         if (unlikely(CPUID != bfin_cpuid()))
 862                 printk(KERN_ERR "ERROR: Not running on ADSP-%s: unknown CPUID 0x%04x Rev 0.%d\n",
 863                         CPU, bfin_cpuid(), bfin_revid());
 864
 865 #ifdef CONFIG_DUMMY_CONSOLE
 866         conswitchp = &dummy_con;
 867 #endif
 868
 869 #if defined(CONFIG_CMDLINE_BOOL)
 870         strncpy(&command_line[0], CONFIG_CMDLINE, sizeof(command_line));
 871         command_line[sizeof(command_line) - 1] = 0;
 872 #endif
 873
 874         /* Keep a copy of command line */
 875         *cmdline_p = &command_line[0];
 876         memcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
 877         boot_command_line[COMMAND_LINE_SIZE - 1] = '\0';
 878
 879         memset(&bfin_memmap, 0, sizeof(bfin_memmap));
 880
 881         /* If the user does not specify things on the command line, use
 882          * what the bootloader set things up as
 883          */
 884         physical_mem_end = 0;
 885         parse_cmdline_early(&command_line[0]);
 886
 887         if (_ramend == 0)
 888                 _ramend = get_mem_size() * 1024 * 1024;
 889
 890         if (physical_mem_end == 0)
 891                 physical_mem_end = _ramend;
 892
 893         memory_setup();
 894
 895         /* Initialize Async memory banks */
 896         bfin_write_EBIU_AMBCTL0(AMBCTL0VAL);
 897         bfin_write_EBIU_AMBCTL1(AMBCTL1VAL);
 898         bfin_write_EBIU_AMGCTL(AMGCTLVAL);
 899 #ifdef CONFIG_EBIU_MBSCTLVAL
 900         bfin_write_EBIU_MBSCTL(CONFIG_EBIU_MBSCTLVAL);
 901         bfin_write_EBIU_MODE(CONFIG_EBIU_MODEVAL);
 902         bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTLVAL);
 903 #endif
 904 #ifdef CONFIG_BFIN_HYSTERESIS_CONTROL
 905         bfin_write_PORTF_HYSTERISIS(HYST_PORTF_0_15);
 906         bfin_write_PORTG_HYSTERISIS(HYST_PORTG_0_15);
 907         bfin_write_PORTH_HYSTERISIS(HYST_PORTH_0_15);
 908         bfin_write_MISCPORT_HYSTERISIS((bfin_read_MISCPORT_HYSTERISIS() &
 909                                         ~HYST_NONEGPIO_MASK) | HYST_NONEGPIO);
 910 #endif
 911
 912         cclk = get_cclk();
 913         sclk = get_sclk();
 914
 915         if ((ANOMALY_05000273 || ANOMALY_05000274) && (cclk >> 1) < sclk)
 916                 panic("ANOMALY 05000273 or 05000274: CCLK must be >= 2*SCLK");
 917
 918 #ifdef BF561_FAMILY
 919         if (ANOMALY_05000266) {
 920                 bfin_read_IMDMA_D0_IRQ_STATUS();
 921                 bfin_read_IMDMA_D1_IRQ_STATUS();
 922         }
 923 #endif
 924         printk(KERN_INFO "Hardware Trace ");
 925         if (bfin_read_TBUFCTL() & 0x1)
 926                 printk(KERN_CONT "Active ");
 927         else
 928                 printk(KERN_CONT "Off ");
 929         if (bfin_read_TBUFCTL() & 0x2)
 930                 printk(KERN_CONT "and Enabled\n");
 931         else
 932                 printk(KERN_CONT "and Disabled\n");
 933
 934         printk(KERN_INFO "Boot Mode: %i\n", bfin_read_SYSCR() & 0xF);
 935
 936         /* Newer parts mirror SWRST bits in SYSCR */
 937 #if defined(CONFIG_BF53x) || defined(CONFIG_BF561) || \
 938     defined(CONFIG_BF538) || defined(CONFIG_BF539)
 939         _bfin_swrst = bfin_read_SWRST();
 940 #else
 941         /* Clear boot mode field */
 942         _bfin_swrst = bfin_read_SYSCR() & ~0xf;
 943 #endif
 944
 945 #ifdef CONFIG_DEBUG_DOUBLEFAULT_PRINT
 946         bfin_write_SWRST(_bfin_swrst & ~DOUBLE_FAULT);
 947 #endif
 948 #ifdef CONFIG_DEBUG_DOUBLEFAULT_RESET
 949         bfin_write_SWRST(_bfin_swrst | DOUBLE_FAULT);
 950 #endif
 951
 952 #ifdef CONFIG_SMP
 953         if (_bfin_swrst & SWRST_DBL_FAULT_A) {
 954 #else
 955         if (_bfin_swrst & RESET_DOUBLE) {
 956 #endif
 957                 printk(KERN_EMERG "Recovering from DOUBLE FAULT event\n");
 958 #ifdef CONFIG_DEBUG_DOUBLEFAULT
 959                 /* We assume the crashing kernel, and the current symbol table match */
 960                 printk(KERN_EMERG " While handling exception (EXCAUSE = 0x%x) at %pF\n",
 961                         (int)init_saved_seqstat & SEQSTAT_EXCAUSE, init_saved_retx);
 962                 printk(KERN_NOTICE "   DCPLB_FAULT_ADDR: %pF\n", init_saved_dcplb_fault_addr);
 963                 printk(KERN_NOTICE "   ICPLB_FAULT_ADDR: %pF\n", init_saved_icplb_fault_addr);
 964 #endif
 965                 printk(KERN_NOTICE " The instruction at %pF caused a double exception\n",
 966                         init_retx);
 967         } else if (_bfin_swrst & RESET_WDOG)
 968                 printk(KERN_INFO "Recovering from Watchdog event\n");
 969         else if (_bfin_swrst & RESET_SOFTWARE)
 970                 printk(KERN_NOTICE "Reset caused by Software reset\n");
 971
 972         printk(KERN_INFO "Blackfin support (C) 2004-2010 Analog Devices, Inc.\n");
 973         if (bfin_compiled_revid() == 0xffff)
 974                 printk(KERN_INFO "Compiled for ADSP-%s Rev any, running on 0.%d\n", CPU, bfin_revid());
 975         else if (bfin_compiled_revid() == -1)
 976                 printk(KERN_INFO "Compiled for ADSP-%s Rev none\n", CPU);
 977         else
 978                 printk(KERN_INFO "Compiled for ADSP-%s Rev 0.%d\n", CPU, bfin_compiled_revid());
 979
 980         if (likely(CPUID == bfin_cpuid())) {
 981                 if (bfin_revid() != bfin_compiled_revid()) {
 982                         if (bfin_compiled_revid() == -1)
 983                                 printk(KERN_ERR "Warning: Compiled for Rev none, but running on Rev %d\n",
 984                                        bfin_revid());
 985                         else if (bfin_compiled_revid() != 0xffff) {
 986                                 printk(KERN_ERR "Warning: Compiled for Rev %d, but running on Rev %d\n",
 987                                        bfin_compiled_revid(), bfin_revid());
 988                                 if (bfin_compiled_revid() > bfin_revid())
 989                                         panic("Error: you are missing anomaly workarounds for this rev");
 990                         }
 991                 }
 992                 if (bfin_revid() < CONFIG_BF_REV_MIN || bfin_revid() > CONFIG_BF_REV_MAX)
 993                         printk(KERN_ERR "Warning: Unsupported Chip Revision ADSP-%s Rev 0.%d detected\n",
 994                                CPU, bfin_revid());
 995         }
 996
 997         printk(KERN_INFO "Blackfin Linux support by http://blackfin.uclinux.org/\n");
 998
 999         printk(KERN_INFO "Processor Speed: %lu MHz core clock and %lu MHz System Clock\n",
1000                cclk / 1000000, sclk / 1000000);
1001
1002         setup_bootmem_allocator();
1003
1004         paging_init();
1005
1006         /* Copy atomic sequences to their fixed location, and sanity check that
1007            these locations are the ones that we advertise to userspace.  */
1008         memcpy((void *)FIXED_CODE_START, &fixed_code_start,
1009                FIXED_CODE_END - FIXED_CODE_START);
1010         BUG_ON((char *)&sigreturn_stub - (char *)&fixed_code_start
1011                != SIGRETURN_STUB - FIXED_CODE_START);
1012         BUG_ON((char *)&atomic_xchg32 - (char *)&fixed_code_start
1013                != ATOMIC_XCHG32 - FIXED_CODE_START);
1014         BUG_ON((char *)&atomic_cas32 - (char *)&fixed_code_start
1015                != ATOMIC_CAS32 - FIXED_CODE_START);
1016         BUG_ON((char *)&atomic_add32 - (char *)&fixed_code_start
1017                != ATOMIC_ADD32 - FIXED_CODE_START);
1018         BUG_ON((char *)&atomic_sub32 - (char *)&fixed_code_start
1019                != ATOMIC_SUB32 - FIXED_CODE_START);
1020         BUG_ON((char *)&atomic_ior32 - (char *)&fixed_code_start
1021                != ATOMIC_IOR32 - FIXED_CODE_START);
1022         BUG_ON((char *)&atomic_and32 - (char *)&fixed_code_start
1023                != ATOMIC_AND32 - FIXED_CODE_START);
1024         BUG_ON((char *)&atomic_xor32 - (char *)&fixed_code_start
1025                != ATOMIC_XOR32 - FIXED_CODE_START);
1026         BUG_ON((char *)&safe_user_instruction - (char *)&fixed_code_start
1027                 != SAFE_USER_INSTRUCTION - FIXED_CODE_START);
1028
1029 #ifdef CONFIG_SMP
1030         platform_init_cpus();
1031 #endif
1032         init_exception_vectors();
1033         bfin_cache_init();      /* Initialize caches for the boot CPU */
1034 }
1035
1036 static int __init topology_init(void)
1037 {
1038         unsigned int cpu;
1039         /* Record CPU-private information for the boot processor. */
1040         bfin_setup_cpudata(0);
1041
1042         for_each_possible_cpu(cpu) {
1043                 register_cpu(&per_cpu(cpu_data, cpu).cpu, cpu);
1044         }
1045
1046         return 0;
1047 }
1048
1049 subsys_initcall(topology_init);
1050
1051 /* Get the input clock frequency */
1052 static u_long cached_clkin_hz = CONFIG_CLKIN_HZ;
1053 static u_long get_clkin_hz(void)
1054 {
1055         return cached_clkin_hz;
1056 }
1057 static int __init early_init_clkin_hz(char *buf)
1058 {
1059         cached_clkin_hz = simple_strtoul(buf, NULL, 0);
1060 #ifdef BFIN_KERNEL_CLOCK
1061         if (cached_clkin_hz != CONFIG_CLKIN_HZ)
1062                 panic("cannot change clkin_hz when reprogramming clocks");
1063 #endif
1064         return 1;
1065 }
1066 early_param("clkin_hz=", early_init_clkin_hz);
1067
1068 /* Get the voltage input multiplier */
1069 static u_long get_vco(void)
1070 {
1071         static u_long cached_vco;
1072         u_long msel, pll_ctl;
1073
1074         /* The assumption here is that VCO never changes at runtime.
1075          * If, someday, we support that, then we'll have to change this.
1076          */
1077         if (cached_vco)
1078                 return cached_vco;
1079
1080         pll_ctl = bfin_read_PLL_CTL();
1081         msel = (pll_ctl >> 9) & 0x3F;
1082         if (0 == msel)
1083                 msel = 64;
1084
1085         cached_vco = get_clkin_hz();
1086         cached_vco >>= (1 & pll_ctl);   /* DF bit */
1087         cached_vco *= msel;
1088         return cached_vco;
1089 }
1090
1091 /* Get the Core clock */
1092 u_long get_cclk(void)
1093 {
1094         static u_long cached_cclk_pll_div, cached_cclk;
1095         u_long csel, ssel;
1096
1097         if (bfin_read_PLL_STAT() & 0x1)
1098                 return get_clkin_hz();
1099
1100         ssel = bfin_read_PLL_DIV();
1101         if (ssel == cached_cclk_pll_div)
1102                 return cached_cclk;
1103         else
1104                 cached_cclk_pll_div = ssel;
1105
1106         csel = ((ssel >> 4) & 0x03);
1107         ssel &= 0xf;
1108         if (ssel && ssel < (1 << csel)) /* SCLK > CCLK */
1109                 cached_cclk = get_vco() / ssel;
1110         else
1111                 cached_cclk = get_vco() >> csel;
1112         return cached_cclk;
1113 }
1114 EXPORT_SYMBOL(get_cclk);
1115
1116 /* Get the System clock */
1117 u_long get_sclk(void)
1118 {
1119         static u_long cached_sclk;
1120         u_long ssel;
1121
1122         /* The assumption here is that SCLK never changes at runtime.
1123          * If, someday, we support that, then we'll have to change this.
1124          */
1125         if (cached_sclk)
1126                 return cached_sclk;
1127
1128         if (bfin_read_PLL_STAT() & 0x1)
1129                 return get_clkin_hz();
1130
1131         ssel = bfin_read_PLL_DIV() & 0xf;
1132         if (0 == ssel) {
1133                 printk(KERN_WARNING "Invalid System Clock\n");
1134                 ssel = 1;
1135         }
1136
1137         cached_sclk = get_vco() / ssel;
1138         return cached_sclk;
1139 }
1140 EXPORT_SYMBOL(get_sclk);
1141
1142 unsigned long sclk_to_usecs(unsigned long sclk)
1143 {
1144         u64 tmp = USEC_PER_SEC * (u64)sclk;
1145         do_div(tmp, get_sclk());
1146         return tmp;
1147 }
1148 EXPORT_SYMBOL(sclk_to_usecs);
1149
1150 unsigned long usecs_to_sclk(unsigned long usecs)
1151 {
1152         u64 tmp = get_sclk() * (u64)usecs;
1153         do_div(tmp, USEC_PER_SEC);
1154         return tmp;
1155 }
1156 EXPORT_SYMBOL(usecs_to_sclk);
1157
1158 /*
1159  *      Get CPU information for use by the procfs.
1160  */
1161 static int show_cpuinfo(struct seq_file *m, void *v)
1162 {
1163         char *cpu, *mmu, *fpu, *vendor, *cache;
1164         uint32_t revid;
1165         int cpu_num = *(unsigned int *)v;
1166         u_long sclk, cclk;
1167         u_int icache_size = BFIN_ICACHESIZE / 1024, dcache_size = 0, dsup_banks = 0;
1168         struct blackfin_cpudata *cpudata = &per_cpu(cpu_data, cpu_num);
1169
1170         cpu = CPU;
1171         mmu = "none";
1172         fpu = "none";
1173         revid = bfin_revid();
1174
1175         sclk = get_sclk();
1176         cclk = get_cclk();
1177
1178         switch (bfin_read_CHIPID() & CHIPID_MANUFACTURE) {
1179         case 0xca:
1180                 vendor = "Analog Devices";
1181                 break;
1182         default:
1183                 vendor = "unknown";
1184                 break;
1185         }
1186
1187         seq_printf(m, "processor\t: %d\n" "vendor_id\t: %s\n", cpu_num, vendor);
1188
1189         if (CPUID == bfin_cpuid())
1190                 seq_printf(m, "cpu family\t: 0x%04x\n", CPUID);
1191         else
1192                 seq_printf(m, "cpu family\t: Compiled for:0x%04x, running on:0x%04x\n",
1193                         CPUID, bfin_cpuid());
1194
1195         seq_printf(m, "model name\t: ADSP-%s %lu(MHz CCLK) %lu(MHz SCLK) (%s)\n"
1196                 "stepping\t: %d ",
1197                 cpu, cclk/1000000, sclk/1000000,
1198 #ifdef CONFIG_MPU
1199                 "mpu on",
1200 #else
1201                 "mpu off",
1202 #endif
1203                 revid);
1204
1205         if (bfin_revid() != bfin_compiled_revid()) {
1206                 if (bfin_compiled_revid() == -1)
1207                         seq_printf(m, "(Compiled for Rev none)");
1208                 else if (bfin_compiled_revid() == 0xffff)
1209                         seq_printf(m, "(Compiled for Rev any)");
1210                 else
1211                         seq_printf(m, "(Compiled for Rev %d)", bfin_compiled_revid());
1212         }
1213
1214         seq_printf(m, "\ncpu MHz\t\t: %lu.%03lu/%lu.%03lu\n",
1215                 cclk/1000000, cclk%1000000,
1216                 sclk/1000000, sclk%1000000);
1217         seq_printf(m, "bogomips\t: %lu.%02lu\n"
1218                 "Calibration\t: %lu loops\n",
1219                 (loops_per_jiffy * HZ) / 500000,
1220                 ((loops_per_jiffy * HZ) / 5000) % 100,
1221                 (loops_per_jiffy * HZ));
1222
1223         /* Check Cache configutation */
1224         switch (cpudata->dmemctl & (1 << DMC0_P | 1 << DMC1_P)) {
1225         case ACACHE_BSRAM:
1226                 cache = "dbank-A/B\t: cache/sram";
1227                 dcache_size = 16;
1228                 dsup_banks = 1;
1229                 break;
1230         case ACACHE_BCACHE:
1231                 cache = "dbank-A/B\t: cache/cache";
1232                 dcache_size = 32;
1233                 dsup_banks = 2;
1234                 break;
1235         case ASRAM_BSRAM:
1236                 cache = "dbank-A/B\t: sram/sram";
1237                 dcache_size = 0;
1238                 dsup_banks = 0;
1239                 break;
1240         default:
1241                 cache = "unknown";
1242                 dcache_size = 0;
1243                 dsup_banks = 0;
1244                 break;
1245         }
1246
1247         /* Is it turned on? */
1248         if ((cpudata->dmemctl & (ENDCPLB | DMC_ENABLE)) != (ENDCPLB | DMC_ENABLE))
1249                 dcache_size = 0;
1250
1251         if ((cpudata->imemctl & (IMC | ENICPLB)) != (IMC | ENICPLB))
1252                 icache_size = 0;
1253
1254         seq_printf(m, "cache size\t: %d KB(L1 icache) "
1255                 "%d KB(L1 dcache) %d KB(L2 cache)\n",
1256                 icache_size, dcache_size, 0);
1257         seq_printf(m, "%s\n", cache);
1258         seq_printf(m, "external memory\t: "
1259 #if defined(CONFIG_BFIN_EXTMEM_ICACHEABLE)
1260                    "cacheable"
1261 #else
1262                    "uncacheable"
1263 #endif
1264                    " in instruction cache\n");
1265         seq_printf(m, "external memory\t: "
1266 #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK)
1267                       "cacheable (write-back)"
1268 #elif defined(CONFIG_BFIN_EXTMEM_WRITETHROUGH)
1269                       "cacheable (write-through)"
1270 #else
1271                       "uncacheable"
1272 #endif
1273                       " in data cache\n");
1274
1275         if (icache_size)
1276                 seq_printf(m, "icache setup\t: %d Sub-banks/%d Ways, %d Lines/Way\n",
1277                            BFIN_ISUBBANKS, BFIN_IWAYS, BFIN_ILINES);
1278         else
1279                 seq_printf(m, "icache setup\t: off\n");
1280
1281         seq_printf(m,
1282                    "dcache setup\t: %d Super-banks/%d Sub-banks/%d Ways, %d Lines/Way\n",
1283                    dsup_banks, BFIN_DSUBBANKS, BFIN_DWAYS,
1284                    BFIN_DLINES);
1285 #ifdef __ARCH_SYNC_CORE_DCACHE
1286         seq_printf(m, "SMP Dcache Flushes\t: %lu\n\n", dcache_invld_count[cpu_num]);
1287 #endif
1288 #ifdef __ARCH_SYNC_CORE_ICACHE
1289         seq_printf(m, "SMP Icache Flushes\t: %lu\n\n", icache_invld_count[cpu_num]);
1290 #endif
1291
1292         if (cpu_num != num_possible_cpus() - 1)
1293                 return 0;
1294
1295         if (L2_LENGTH) {
1296                 seq_printf(m, "L2 SRAM\t\t: %dKB\n", L2_LENGTH/0x400);
1297                 seq_printf(m, "L2 SRAM\t\t: "
1298 #if defined(CONFIG_BFIN_L2_ICACHEABLE)
1299                               "cacheable"
1300 #else
1301                               "uncacheable"
1302 #endif
1303                               " in instruction cache\n");
1304                 seq_printf(m, "L2 SRAM\t\t: "
1305 #if defined(CONFIG_BFIN_L2_WRITEBACK)
1306                               "cacheable (write-back)"
1307 #elif defined(CONFIG_BFIN_L2_WRITETHROUGH)
1308                               "cacheable (write-through)"
1309 #else
1310                               "uncacheable"
1311 #endif
1312                               " in data cache\n");
1313         }
1314         seq_printf(m, "board name\t: %s\n", bfin_board_name);
1315         seq_printf(m, "board memory\t: %ld kB (0x%p -> 0x%p)\n",
1316                  physical_mem_end >> 10, (void *)0, (void *)physical_mem_end);
1317         seq_printf(m, "kernel memory\t: %d kB (0x%p -> 0x%p)\n",
1318                 ((int)memory_end - (int)_rambase) >> 10,
1319                 (void *)_rambase,
1320                 (void *)memory_end);
1321         seq_printf(m, "\n");
1322
1323         return 0;
1324 }
1325
1326 static void *c_start(struct seq_file *m, loff_t *pos)
1327 {
1328         if (*pos == 0)
1329                 *pos = first_cpu(cpu_online_map);
1330         if (*pos >= num_online_cpus())
1331                 return NULL;
1332
1333         return pos;
1334 }
1335
1336 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
1337 {
1338         *pos = next_cpu(*pos, cpu_online_map);
1339
1340         return c_start(m, pos);
1341 }
1342
1343 static void c_stop(struct seq_file *m, void *v)
1344 {
1345 }
1346
1347 const struct seq_operations cpuinfo_op = {
1348         .start = c_start,
1349         .next = c_next,
1350         .stop = c_stop,
1351         .show = show_cpuinfo,
1352 };
1353
1354 void __init cmdline_init(const char *r0)
1355 {
1356         early_shadow_stamp();
1357         if (r0)
1358                 strncpy(command_line, r0, COMMAND_LINE_SIZE);
1359 }