arch/blackfin/kernel/cplbinit.c

   1 /*
   2  * Blackfin CPLB initialization
   3  *
   4  *               Copyright 2004-2007 Analog Devices Inc.
   5  *
   6  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, see the file COPYING, or write
  20  * to the Free Software Foundation, Inc.,
  21  * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  22  */
  23 #include <linux/module.h>
  24
  25 #include <asm/blackfin.h>
  26 #include <asm/cplbinit.h>
  27
  28 u_long icplb_table[MAX_CPLBS+1];
  29 u_long dcplb_table[MAX_CPLBS+1];
  30
  31 #ifdef CONFIG_CPLB_SWITCH_TAB_L1
  32 u_long ipdt_table[MAX_SWITCH_I_CPLBS+1]__attribute__((l1_data));
  33 u_long dpdt_table[MAX_SWITCH_D_CPLBS+1]__attribute__((l1_data));
  34
  35 #ifdef CONFIG_CPLB_INFO
  36 u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS]__attribute__((l1_data));
  37 u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS]__attribute__((l1_data));
  38 #endif /* CONFIG_CPLB_INFO */
  39
  40 #else
  41
  42 u_long ipdt_table[MAX_SWITCH_I_CPLBS+1];
  43 u_long dpdt_table[MAX_SWITCH_D_CPLBS+1];
  44
  45 #ifdef CONFIG_CPLB_INFO
  46 u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS];
  47 u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS];
  48 #endif /* CONFIG_CPLB_INFO */
  49
  50 #endif /*CONFIG_CPLB_SWITCH_TAB_L1*/
  51
  52 struct s_cplb {
  53         struct cplb_tab init_i;
  54         struct cplb_tab init_d;
  55         struct cplb_tab switch_i;
  56         struct cplb_tab switch_d;
  57 };
  58
  59 #if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE)
  60 static struct cplb_desc cplb_data[] = {
  61         {
  62                 .start = 0,
  63                 .end = SIZE_1K,
  64                 .psize = SIZE_1K,
  65                 .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB,
  66                 .i_conf = SDRAM_OOPS,
  67                 .d_conf = SDRAM_OOPS,
  68 #if defined(CONFIG_DEBUG_HUNT_FOR_ZERO)
  69                 .valid = 1,
  70 #else
  71                 .valid = 0,
  72 #endif
  73                 .name = "ZERO Pointer Saveguard",
  74         },
  75         {
  76                 .start = L1_CODE_START,
  77                 .end = L1_CODE_START + L1_CODE_LENGTH,
  78                 .psize = SIZE_4M,
  79                 .attr = INITIAL_T | SWITCH_T | I_CPLB,
  80                 .i_conf = L1_IMEMORY,
  81                 .d_conf = 0,
  82                 .valid = 1,
  83                 .name = "L1 I-Memory",
  84         },
  85         {
  86                 .start = L1_DATA_A_START,
  87                 .end = L1_DATA_B_START + L1_DATA_B_LENGTH,
  88                 .psize = SIZE_4M,
  89                 .attr = INITIAL_T | SWITCH_T | D_CPLB,
  90                 .i_conf = 0,
  91                 .d_conf = L1_DMEMORY,
  92 #if ((L1_DATA_A_LENGTH > 0) || (L1_DATA_B_LENGTH > 0))
  93                 .valid = 1,
  94 #else
  95                 .valid = 0,
  96 #endif
  97                 .name = "L1 D-Memory",
  98         },
  99         {
 100                 .start = 0,
 101                 .end = 0,  /* dynamic */
 102                 .psize = 0,
 103                 .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB,
 104                 .i_conf =  SDRAM_IGENERIC,
 105                 .d_conf =  SDRAM_DGENERIC,
 106                 .valid = 1,
 107                 .name = "SDRAM Kernel",
 108         },
 109         {
 110                 .start = 0, /* dynamic */
 111                 .end = 0, /* dynamic */
 112                 .psize = 0,
 113                 .attr = INITIAL_T | SWITCH_T | D_CPLB,
 114                 .i_conf =  SDRAM_IGENERIC,
 115                 .d_conf =  SDRAM_DNON_CHBL,
 116                 .valid = 1,
 117                 .name = "SDRAM RAM MTD",
 118         },
 119         {
 120                 .start = 0, /* dynamic */
 121                 .end = 0,   /* dynamic */
 122                 .psize = SIZE_1M,
 123                 .attr = INITIAL_T | SWITCH_T | D_CPLB,
 124                 .d_conf = SDRAM_DNON_CHBL,
 125                 .valid = 1,
 126                 .name = "SDRAM Uncached DMA ZONE",
 127         },
 128         {
 129                 .start = 0, /* dynamic */
 130                 .end = 0, /* dynamic */
 131                 .psize = 0,
 132                 .attr = SWITCH_T | D_CPLB,
 133                 .i_conf = 0, /* dynamic */
 134                 .d_conf = 0, /* dynamic */
 135                 .valid = 1,
 136                 .name = "SDRAM Reserved Memory",
 137         },
 138         {
 139                 .start = ASYNC_BANK0_BASE,
 140                 .end = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE,
 141                 .psize = 0,
 142                 .attr = SWITCH_T | D_CPLB,
 143                 .d_conf = SDRAM_EBIU,
 144                 .valid = 1,
 145                 .name = "ASYNC Memory",
 146         },
 147         {
 148 #if defined(CONFIG_BF561)
 149                 .start = L2_SRAM,
 150                 .end = L2_SRAM_END,
 151                 .psize = SIZE_1M,
 152                 .attr = SWITCH_T | D_CPLB,
 153                 .i_conf = L2_MEMORY,
 154                 .d_conf = L2_MEMORY,
 155                 .valid = 1,
 156 #else
 157                 .valid = 0,
 158 #endif
 159                 .name = "L2 Memory",
 160         }
 161 };
 162
 163 static u16 __init lock_kernel_check(u32 start, u32 end)
 164 {
 165         if ((start <= (u32) _stext && end >= (u32) _end)
 166             || (start >= (u32) _stext && end <= (u32) _end))
 167                 return IN_KERNEL;
 168         return 0;
 169 }
 170
 171 static unsigned short __init
 172 fill_cplbtab(struct cplb_tab *table,
 173              unsigned long start, unsigned long end,
 174              unsigned long block_size, unsigned long cplb_data)
 175 {
 176         int i;
 177
 178         switch (block_size) {
 179         case SIZE_4M:
 180                 i = 3;
 181                 break;
 182         case SIZE_1M:
 183                 i = 2;
 184                 break;
 185         case SIZE_4K:
 186                 i = 1;
 187                 break;
 188         case SIZE_1K:
 189         default:
 190                 i = 0;
 191                 break;
 192         }
 193
 194         cplb_data = (cplb_data & ~(3 << 16)) | (i << 16);
 195
 196         while ((start < end) && (table->pos < table->size)) {
 197
 198                 table->tab[table->pos++] = start;
 199
 200                 if (lock_kernel_check(start, start + block_size) == IN_KERNEL)
 201                         table->tab[table->pos++] =
 202                             cplb_data | CPLB_LOCK | CPLB_DIRTY;
 203                 else
 204                         table->tab[table->pos++] = cplb_data;
 205
 206                 start += block_size;
 207         }
 208         return 0;
 209 }
 210
 211 static unsigned short __init
 212 close_cplbtab(struct cplb_tab *table)
 213 {
 214
 215         while (table->pos < table->size) {
 216
 217                 table->tab[table->pos++] = 0;
 218                 table->tab[table->pos++] = 0; /* !CPLB_VALID */
 219         }
 220         return 0;
 221 }
 222
 223 /* helper function */
 224 static void __fill_code_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_end)
 225 {
 226         if (cplb_data[i].psize) {
 227                 fill_cplbtab(t,
 228                                 cplb_data[i].start,
 229                                 cplb_data[i].end,
 230                                 cplb_data[i].psize,
 231                                 cplb_data[i].i_conf);
 232         } else {
 233 #if (defined(CONFIG_BLKFIN_CACHE) && defined(ANOMALY_05000263))
 234                 if (i == SDRAM_KERN) {
 235                         fill_cplbtab(t,
 236                                         cplb_data[i].start,
 237                                         cplb_data[i].end,
 238                                         SIZE_4M,
 239                                         cplb_data[i].i_conf);
 240                 } else
 241 #endif
 242                 {
 243                         fill_cplbtab(t,
 244                                         cplb_data[i].start,
 245                                         a_start,
 246                                         SIZE_1M,
 247                                         cplb_data[i].i_conf);
 248                         fill_cplbtab(t,
 249                                         a_start,
 250                                         a_end,
 251                                         SIZE_4M,
 252                                         cplb_data[i].i_conf);
 253                         fill_cplbtab(t, a_end,
 254                                         cplb_data[i].end,
 255                                         SIZE_1M,
 256                                         cplb_data[i].i_conf);
 257                 }
 258         }
 259 }
 260
 261 static void __fill_data_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_end)
 262 {
 263         if (cplb_data[i].psize) {
 264                 fill_cplbtab(t,
 265                                 cplb_data[i].start,
 266                                 cplb_data[i].end,
 267                                 cplb_data[i].psize,
 268                                 cplb_data[i].d_conf);
 269         } else {
 270                 fill_cplbtab(t,
 271                                 cplb_data[i].start,
 272                                 a_start, SIZE_1M,
 273                                 cplb_data[i].d_conf);
 274                 fill_cplbtab(t, a_start,
 275                                 a_end, SIZE_4M,
 276                                 cplb_data[i].d_conf);
 277                 fill_cplbtab(t, a_end,
 278                                 cplb_data[i].end,
 279                                 SIZE_1M,
 280                                 cplb_data[i].d_conf);
 281         }
 282 }
 283
 284 void __init generate_cpl_tables(void)
 285 {
 286
 287         u16 i, j, process;
 288         u32 a_start, a_end, as, ae, as_1m;
 289
 290         struct cplb_tab *t_i = NULL;
 291         struct cplb_tab *t_d = NULL;
 292         struct s_cplb cplb;
 293
 294         cplb.init_i.size = MAX_CPLBS;
 295         cplb.init_d.size = MAX_CPLBS;
 296         cplb.switch_i.size = MAX_SWITCH_I_CPLBS;
 297         cplb.switch_d.size = MAX_SWITCH_D_CPLBS;
 298
 299         cplb.init_i.pos = 0;
 300         cplb.init_d.pos = 0;
 301         cplb.switch_i.pos = 0;
 302         cplb.switch_d.pos = 0;
 303
 304         cplb.init_i.tab = icplb_table;
 305         cplb.init_d.tab = dcplb_table;
 306         cplb.switch_i.tab = ipdt_table;
 307         cplb.switch_d.tab = dpdt_table;
 308
 309         cplb_data[SDRAM_KERN].end = memory_end;
 310
 311 #ifdef CONFIG_MTD_UCLINUX
 312         cplb_data[SDRAM_RAM_MTD].start = memory_mtd_start;
 313         cplb_data[SDRAM_RAM_MTD].end = memory_mtd_start + mtd_size;
 314         cplb_data[SDRAM_RAM_MTD].valid = mtd_size > 0;
 315 # if defined(CONFIG_ROMFS_FS)
 316         cplb_data[SDRAM_RAM_MTD].attr |= I_CPLB;
 317
 318         /*
 319          * The ROMFS_FS size is often not multiple of 1MB.
 320          * This can cause multiple CPLB sets covering the same memory area.
 321          * This will then cause multiple CPLB hit exceptions.
 322          * Workaround: We ensure a contiguous memory area by extending the kernel
 323          * memory section over the mtd section.
 324          * For ROMFS_FS memory must be covered with ICPLBs anyways.
 325          * So there is no difference between kernel and mtd memory setup.
 326          */
 327
 328         cplb_data[SDRAM_KERN].end = memory_mtd_start + mtd_size;;
 329         cplb_data[SDRAM_RAM_MTD].valid = 0;
 330
 331 # endif
 332 #else
 333         cplb_data[SDRAM_RAM_MTD].valid = 0;
 334 #endif
 335
 336         cplb_data[SDRAM_DMAZ].start = _ramend - DMA_UNCACHED_REGION;
 337         cplb_data[SDRAM_DMAZ].end = _ramend;
 338
 339         cplb_data[RES_MEM].start = _ramend;
 340         cplb_data[RES_MEM].end = physical_mem_end;
 341
 342         if (reserved_mem_dcache_on)
 343                 cplb_data[RES_MEM].d_conf = SDRAM_DGENERIC;
 344         else
 345                 cplb_data[RES_MEM].d_conf = SDRAM_DNON_CHBL;
 346
 347         if (reserved_mem_icache_on)
 348                 cplb_data[RES_MEM].i_conf = SDRAM_IGENERIC;
 349         else
 350                 cplb_data[RES_MEM].i_conf = SDRAM_INON_CHBL;
 351
 352         for (i = ZERO_P; i <= L2_MEM; i++) {
 353                 if (!cplb_data[i].valid)
 354                         continue;
 355
 356                 as_1m = cplb_data[i].start % SIZE_1M;
 357
 358                 /* We need to make sure all sections are properly 1M aligned
 359                  * However between Kernel Memory and the Kernel mtd section, depending on the
 360                  * rootfs size, there can be overlapping memory areas.
 361                  */
 362
 363                 if (as_1m && i != L1I_MEM && i != L1D_MEM) {
 364 #ifdef CONFIG_MTD_UCLINUX
 365                         if (i == SDRAM_RAM_MTD) {
 366                                 if ((cplb_data[SDRAM_KERN].end + 1) > cplb_data[SDRAM_RAM_MTD].start)
 367                                         cplb_data[SDRAM_RAM_MTD].start = (cplb_data[i].start & (-2*SIZE_1M)) + SIZE_1M;
 368                                 else
 369                                         cplb_data[SDRAM_RAM_MTD].start = (cplb_data[i].start & (-2*SIZE_1M));
 370                         } else
 371 #endif
 372                                 printk(KERN_WARNING "Unaligned Start of %s at 0x%X\n",
 373                                        cplb_data[i].name, cplb_data[i].start);
 374                 }
 375
 376                 as = cplb_data[i].start % SIZE_4M;
 377                 ae = cplb_data[i].end % SIZE_4M;
 378
 379                 if (as)
 380                         a_start = cplb_data[i].start + (SIZE_4M - (as));
 381                 else
 382                         a_start = cplb_data[i].start;
 383
 384                 a_end = cplb_data[i].end - ae;
 385
 386                 for (j = INITIAL_T; j <= SWITCH_T; j++) {
 387
 388                         switch (j) {
 389                         case INITIAL_T:
 390                                 if (cplb_data[i].attr & INITIAL_T) {
 391                                         t_i = &cplb.init_i;
 392                                         t_d = &cplb.init_d;
 393                                         process = 1;
 394                                 } else
 395                                         process = 0;
 396                                 break;
 397                         case SWITCH_T:
 398                                 if (cplb_data[i].attr & SWITCH_T) {
 399                                         t_i = &cplb.switch_i;
 400                                         t_d = &cplb.switch_d;
 401                                         process = 1;
 402                                 } else
 403                                         process = 0;
 404                                 break;
 405                         default:
 406                                         process = 0;
 407                                 break;
 408                         }
 409
 410                         if (!process)
 411                                 continue;
 412                         if (cplb_data[i].attr & I_CPLB)
 413                                 __fill_code_cplbtab(t_i, i, a_start, a_end);
 414
 415                         if (cplb_data[i].attr & D_CPLB)
 416                                 __fill_data_cplbtab(t_d, i, a_start, a_end);
 417                 }
 418         }
 419
 420 /* close tables */
 421
 422         close_cplbtab(&cplb.init_i);
 423         close_cplbtab(&cplb.init_d);
 424
 425         cplb.init_i.tab[cplb.init_i.pos] = -1;
 426         cplb.init_d.tab[cplb.init_d.pos] = -1;
 427         cplb.switch_i.tab[cplb.switch_i.pos] = -1;
 428         cplb.switch_d.tab[cplb.switch_d.pos] = -1;
 429
 430 }
 431
 432 #endif
 433