2 * File: arch/blackfin/kernel/cplb-nompu-c/cplbmgr.c
3 * Based on: arch/blackfin/kernel/cplb-mpu/cplbmgr.c
4 * Author: Michael McTernan <mmcternan@airvana.com>
7 * Description: CPLB miss handler.
10 * Copyright 2008 Airvana Inc.
11 * Copyright 2004-2007 Analog Devices Inc.
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
26 #include <linux/kernel.h>
27 #include <asm/blackfin.h>
28 #include <asm/cplbinit.h>
30 #include <asm/mmu_context.h>
31 #include <asm/traps.h>
36 * This file is compiled with certain -ffixed-reg options. We have to
37 * make sure not to call any functions here that could clobber these
41 int nr_dcplb_miss[NR_CPUS], nr_icplb_miss[NR_CPUS];
42 int nr_dcplb_supv_miss[NR_CPUS], nr_icplb_supv_miss[NR_CPUS];
43 int nr_cplb_flush[NR_CPUS], nr_dcplb_prot[NR_CPUS];
45 #ifdef CONFIG_EXCPT_IRQ_SYSC_L1
46 #define MGR_ATTR __attribute__((l1_text))
51 static inline void write_dcplb_data(int cpu, int idx, unsigned long data,
55 bfin_write32(DCPLB_DATA0 + idx * 4, data);
56 bfin_write32(DCPLB_ADDR0 + idx * 4, addr);
59 #ifdef CONFIG_CPLB_INFO
60 dcplb_tbl[cpu][idx].addr = addr;
61 dcplb_tbl[cpu][idx].data = data;
65 static inline void write_icplb_data(int cpu, int idx, unsigned long data,
69 bfin_write32(ICPLB_DATA0 + idx * 4, data);
70 bfin_write32(ICPLB_ADDR0 + idx * 4, addr);
73 #ifdef CONFIG_CPLB_INFO
74 icplb_tbl[cpu][idx].addr = addr;
75 icplb_tbl[cpu][idx].data = data;
79 /* Counters to implement round-robin replacement. */
80 static int icplb_rr_index[NR_CPUS] PDT_ATTR;
81 static int dcplb_rr_index[NR_CPUS] PDT_ATTR;
84 * Find an ICPLB entry to be evicted and return its index.
86 static int evict_one_icplb(int cpu)
88 int i = first_switched_icplb + icplb_rr_index[cpu];
90 i -= MAX_CPLBS - first_switched_icplb;
91 icplb_rr_index[cpu] -= MAX_CPLBS - first_switched_icplb;
93 icplb_rr_index[cpu]++;
97 static int evict_one_dcplb(int cpu)
99 int i = first_switched_dcplb + dcplb_rr_index[cpu];
100 if (i >= MAX_CPLBS) {
101 i -= MAX_CPLBS - first_switched_dcplb;
102 dcplb_rr_index[cpu] -= MAX_CPLBS - first_switched_dcplb;
104 dcplb_rr_index[cpu]++;
108 MGR_ATTR static int icplb_miss(int cpu)
110 unsigned long addr = bfin_read_ICPLB_FAULT_ADDR();
111 int status = bfin_read_ICPLB_STATUS();
113 unsigned long i_data, base, addr1, eaddr;
115 nr_icplb_miss[cpu]++;
116 if (unlikely(status & FAULT_USERSUPV))
117 nr_icplb_supv_miss[cpu]++;
122 eaddr = icplb_bounds[idx].eaddr;
126 } while (++idx < icplb_nr_bounds);
128 if (unlikely(idx == icplb_nr_bounds))
129 return CPLB_NO_ADDR_MATCH;
131 i_data = icplb_bounds[idx].data;
132 if (unlikely(i_data == 0))
133 return CPLB_NO_ADDR_MATCH;
135 addr1 = addr & ~(SIZE_4M - 1);
136 addr &= ~(SIZE_1M - 1);
137 i_data |= PAGE_SIZE_1MB;
138 if (addr1 >= base && (addr1 + SIZE_4M) <= eaddr) {
141 * (PAGE_SIZE_4MB & PAGE_SIZE_1MB) == PAGE_SIZE_1MB.
143 i_data |= PAGE_SIZE_4MB;
147 /* Pick entry to evict */
148 idx = evict_one_icplb(cpu);
150 write_icplb_data(cpu, idx, i_data, addr);
152 return CPLB_RELOADED;
155 MGR_ATTR static int dcplb_miss(int cpu)
157 unsigned long addr = bfin_read_DCPLB_FAULT_ADDR();
158 int status = bfin_read_DCPLB_STATUS();
160 unsigned long d_data, base, addr1, eaddr;
162 nr_dcplb_miss[cpu]++;
163 if (unlikely(status & FAULT_USERSUPV))
164 nr_dcplb_supv_miss[cpu]++;
169 eaddr = dcplb_bounds[idx].eaddr;
173 } while (++idx < dcplb_nr_bounds);
175 if (unlikely(idx == dcplb_nr_bounds))
176 return CPLB_NO_ADDR_MATCH;
178 d_data = dcplb_bounds[idx].data;
179 if (unlikely(d_data == 0))
180 return CPLB_NO_ADDR_MATCH;
182 addr1 = addr & ~(SIZE_4M - 1);
183 addr &= ~(SIZE_1M - 1);
184 d_data |= PAGE_SIZE_1MB;
185 if (addr1 >= base && (addr1 + SIZE_4M) <= eaddr) {
188 * (PAGE_SIZE_4MB & PAGE_SIZE_1MB) == PAGE_SIZE_1MB.
190 d_data |= PAGE_SIZE_4MB;
194 /* Pick entry to evict */
195 idx = evict_one_dcplb(cpu);
197 write_dcplb_data(cpu, idx, d_data, addr);
199 return CPLB_RELOADED;
202 MGR_ATTR int cplb_hdr(int seqstat, struct pt_regs *regs)
204 int cause = seqstat & 0x3f;
205 unsigned int cpu = raw_smp_processor_id();
208 return icplb_miss(cpu);
210 return dcplb_miss(cpu);
212 return CPLB_UNKNOWN_ERR;