arch/avr32/mach-at32ap/at32ap700x.c

   1 /*
   2  * Copyright (C) 2005-2006 Atmel Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8 #include <linux/clk.h>
   9 #include <linux/delay.h>
  10 #include <linux/dw_dmac.h>
  11 #include <linux/fb.h>
  12 #include <linux/init.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/dma-mapping.h>
  15 #include <linux/gpio.h>
  16 #include <linux/spi/spi.h>
  17 #include <linux/usb/atmel_usba_udc.h>
  18 #include <linux/atmel-mci.h>
  19
  20 #include <asm/io.h>
  21 #include <asm/irq.h>
  22
  23 #include <mach/at32ap700x.h>
  24 #include <mach/board.h>
  25 #include <mach/hmatrix.h>
  26 #include <mach/portmux.h>
  27 #include <mach/sram.h>
  28
  29 #include <sound/atmel-abdac.h>
  30 #include <sound/atmel-ac97c.h>
  31
  32 #include <video/atmel_lcdc.h>
  33
  34 #include "clock.h"
  35 #include "pio.h"
  36 #include "pm.h"
  37
  38
  39 #define PBMEM(base)                                     \
  40         {                                               \
  41                 .start          = base,                 \
  42                 .end            = base + 0x3ff,         \
  43                 .flags          = IORESOURCE_MEM,       \
  44         }
  45 #define IRQ(num)                                        \
  46         {                                               \
  47                 .start          = num,                  \
  48                 .end            = num,                  \
  49                 .flags          = IORESOURCE_IRQ,       \
  50         }
  51 #define NAMED_IRQ(num, _name)                           \
  52         {                                               \
  53                 .start          = num,                  \
  54                 .end            = num,                  \
  55                 .name           = _name,                \
  56                 .flags          = IORESOURCE_IRQ,       \
  57         }
  58
  59 /* REVISIT these assume *every* device supports DMA, but several
  60  * don't ... tc, smc, pio, rtc, watchdog, pwm, ps2, and more.
  61  */
  62 #define DEFINE_DEV(_name, _id)                                  \
  63 static u64 _name##_id##_dma_mask = DMA_32BIT_MASK;              \
  64 static struct platform_device _name##_id##_device = {           \
  65         .name           = #_name,                               \
  66         .id             = _id,                                  \
  67         .dev            = {                                     \
  68                 .dma_mask = &_name##_id##_dma_mask,             \
  69                 .coherent_dma_mask = DMA_32BIT_MASK,            \
  70         },                                                      \
  71         .resource       = _name##_id##_resource,                \
  72         .num_resources  = ARRAY_SIZE(_name##_id##_resource),    \
  73 }
  74 #define DEFINE_DEV_DATA(_name, _id)                             \
  75 static u64 _name##_id##_dma_mask = DMA_32BIT_MASK;              \
  76 static struct platform_device _name##_id##_device = {           \
  77         .name           = #_name,                               \
  78         .id             = _id,                                  \
  79         .dev            = {                                     \
  80                 .dma_mask = &_name##_id##_dma_mask,             \
  81                 .platform_data  = &_name##_id##_data,           \
  82                 .coherent_dma_mask = DMA_32BIT_MASK,            \
  83         },                                                      \
  84         .resource       = _name##_id##_resource,                \
  85         .num_resources  = ARRAY_SIZE(_name##_id##_resource),    \
  86 }
  87
  88 #define select_peripheral(port, pin_mask, periph, flags)        \
  89         at32_select_periph(GPIO_##port##_BASE, pin_mask,        \
  90                            GPIO_##periph, flags)
  91
  92 #define DEV_CLK(_name, devname, bus, _index)                    \
  93 static struct clk devname##_##_name = {                         \
  94         .name           = #_name,                               \
  95         .dev            = &devname##_device.dev,                \
  96         .parent         = &bus##_clk,                           \
  97         .mode           = bus##_clk_mode,                       \
  98         .get_rate       = bus##_clk_get_rate,                   \
  99         .index          = _index,                               \
 100 }
 101
 102 static DEFINE_SPINLOCK(pm_lock);
 103
 104 static struct clk osc0;
 105 static struct clk osc1;
 106
 107 static unsigned long osc_get_rate(struct clk *clk)
 108 {
 109         return at32_board_osc_rates[clk->index];
 110 }
 111
 112 static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
 113 {
 114         unsigned long div, mul, rate;
 115
 116         div = PM_BFEXT(PLLDIV, control) + 1;
 117         mul = PM_BFEXT(PLLMUL, control) + 1;
 118
 119         rate = clk->parent->get_rate(clk->parent);
 120         rate = (rate + div / 2) / div;
 121         rate *= mul;
 122
 123         return rate;
 124 }
 125
 126 static long pll_set_rate(struct clk *clk, unsigned long rate,
 127                          u32 *pll_ctrl)
 128 {
 129         unsigned long mul;
 130         unsigned long mul_best_fit = 0;
 131         unsigned long div;
 132         unsigned long div_min;
 133         unsigned long div_max;
 134         unsigned long div_best_fit = 0;
 135         unsigned long base;
 136         unsigned long pll_in;
 137         unsigned long actual = 0;
 138         unsigned long rate_error;
 139         unsigned long rate_error_prev = ~0UL;
 140         u32 ctrl;
 141
 142         /* Rate must be between 80 MHz and 200 Mhz. */
 143         if (rate < 80000000UL || rate > 200000000UL)
 144                 return -EINVAL;
 145
 146         ctrl = PM_BF(PLLOPT, 4);
 147         base = clk->parent->get_rate(clk->parent);
 148
 149         /* PLL input frequency must be between 6 MHz and 32 MHz. */
 150         div_min = DIV_ROUND_UP(base, 32000000UL);
 151         div_max = base / 6000000UL;
 152
 153         if (div_max < div_min)
 154                 return -EINVAL;
 155
 156         for (div = div_min; div <= div_max; div++) {
 157                 pll_in = (base + div / 2) / div;
 158                 mul = (rate + pll_in / 2) / pll_in;
 159
 160                 if (mul == 0)
 161                         continue;
 162
 163                 actual = pll_in * mul;
 164                 rate_error = abs(actual - rate);
 165
 166                 if (rate_error < rate_error_prev) {
 167                         mul_best_fit = mul;
 168                         div_best_fit = div;
 169                         rate_error_prev = rate_error;
 170                 }
 171
 172                 if (rate_error == 0)
 173                         break;
 174         }
 175
 176         if (div_best_fit == 0)
 177                 return -EINVAL;
 178
 179         ctrl |= PM_BF(PLLMUL, mul_best_fit - 1);
 180         ctrl |= PM_BF(PLLDIV, div_best_fit - 1);
 181         ctrl |= PM_BF(PLLCOUNT, 16);
 182
 183         if (clk->parent == &osc1)
 184                 ctrl |= PM_BIT(PLLOSC);
 185
 186         *pll_ctrl = ctrl;
 187
 188         return actual;
 189 }
 190
 191 static unsigned long pll0_get_rate(struct clk *clk)
 192 {
 193         u32 control;
 194
 195         control = pm_readl(PLL0);
 196
 197         return pll_get_rate(clk, control);
 198 }
 199
 200 static void pll1_mode(struct clk *clk, int enabled)
 201 {
 202         unsigned long timeout;
 203         u32 status;
 204         u32 ctrl;
 205
 206         ctrl = pm_readl(PLL1);
 207
 208         if (enabled) {
 209                 if (!PM_BFEXT(PLLMUL, ctrl) && !PM_BFEXT(PLLDIV, ctrl)) {
 210                         pr_debug("clk %s: failed to enable, rate not set\n",
 211                                         clk->name);
 212                         return;
 213                 }
 214
 215                 ctrl |= PM_BIT(PLLEN);
 216                 pm_writel(PLL1, ctrl);
 217
 218                 /* Wait for PLL lock. */
 219                 for (timeout = 10000; timeout; timeout--) {
 220                         status = pm_readl(ISR);
 221                         if (status & PM_BIT(LOCK1))
 222                                 break;
 223                         udelay(10);
 224                 }
 225
 226                 if (!(status & PM_BIT(LOCK1)))
 227                         printk(KERN_ERR "clk %s: timeout waiting for lock\n",
 228                                         clk->name);
 229         } else {
 230                 ctrl &= ~PM_BIT(PLLEN);
 231                 pm_writel(PLL1, ctrl);
 232         }
 233 }
 234
 235 static unsigned long pll1_get_rate(struct clk *clk)
 236 {
 237         u32 control;
 238
 239         control = pm_readl(PLL1);
 240
 241         return pll_get_rate(clk, control);
 242 }
 243
 244 static long pll1_set_rate(struct clk *clk, unsigned long rate, int apply)
 245 {
 246         u32 ctrl = 0;
 247         unsigned long actual_rate;
 248
 249         actual_rate = pll_set_rate(clk, rate, &ctrl);
 250
 251         if (apply) {
 252                 if (actual_rate != rate)
 253                         return -EINVAL;
 254                 if (clk->users > 0)
 255                         return -EBUSY;
 256                 pr_debug(KERN_INFO "clk %s: new rate %lu (actual rate %lu)\n",
 257                                 clk->name, rate, actual_rate);
 258                 pm_writel(PLL1, ctrl);
 259         }
 260
 261         return actual_rate;
 262 }
 263
 264 static int pll1_set_parent(struct clk *clk, struct clk *parent)
 265 {
 266         u32 ctrl;
 267
 268         if (clk->users > 0)
 269                 return -EBUSY;
 270
 271         ctrl = pm_readl(PLL1);
 272         WARN_ON(ctrl & PM_BIT(PLLEN));
 273
 274         if (parent == &osc0)
 275                 ctrl &= ~PM_BIT(PLLOSC);
 276         else if (parent == &osc1)
 277                 ctrl |= PM_BIT(PLLOSC);
 278         else
 279                 return -EINVAL;
 280
 281         pm_writel(PLL1, ctrl);
 282         clk->parent = parent;
 283
 284         return 0;
 285 }
 286
 287 /*
 288  * The AT32AP7000 has five primary clock sources: One 32kHz
 289  * oscillator, two crystal oscillators and two PLLs.
 290  */
 291 static struct clk osc32k = {
 292         .name           = "osc32k",
 293         .get_rate       = osc_get_rate,
 294         .users          = 1,
 295         .index          = 0,
 296 };
 297 static struct clk osc0 = {
 298         .name           = "osc0",
 299         .get_rate       = osc_get_rate,
 300         .users          = 1,
 301         .index          = 1,
 302 };
 303 static struct clk osc1 = {
 304         .name           = "osc1",
 305         .get_rate       = osc_get_rate,
 306         .index          = 2,
 307 };
 308 static struct clk pll0 = {
 309         .name           = "pll0",
 310         .get_rate       = pll0_get_rate,
 311         .parent         = &osc0,
 312 };
 313 static struct clk pll1 = {
 314         .name           = "pll1",
 315         .mode           = pll1_mode,
 316         .get_rate       = pll1_get_rate,
 317         .set_rate       = pll1_set_rate,
 318         .set_parent     = pll1_set_parent,
 319         .parent         = &osc0,
 320 };
 321
 322 /*
 323  * The main clock can be either osc0 or pll0.  The boot loader may
 324  * have chosen one for us, so we don't really know which one until we
 325  * have a look at the SM.
 326  */
 327 static struct clk *main_clock;
 328
 329 /*
 330  * Synchronous clocks are generated from the main clock. The clocks
 331  * must satisfy the constraint
 332  *   fCPU >= fHSB >= fPB
 333  * i.e. each clock must not be faster than its parent.
 334  */
 335 static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift)
 336 {
 337         return main_clock->get_rate(main_clock) >> shift;
 338 };
 339
 340 static void cpu_clk_mode(struct clk *clk, int enabled)
 341 {
 342         unsigned long flags;
 343         u32 mask;
 344
 345         spin_lock_irqsave(&pm_lock, flags);
 346         mask = pm_readl(CPU_MASK);
 347         if (enabled)
 348                 mask |= 1 << clk->index;
 349         else
 350                 mask &= ~(1 << clk->index);
 351         pm_writel(CPU_MASK, mask);
 352         spin_unlock_irqrestore(&pm_lock, flags);
 353 }
 354
 355 static unsigned long cpu_clk_get_rate(struct clk *clk)
 356 {
 357         unsigned long cksel, shift = 0;
 358
 359         cksel = pm_readl(CKSEL);
 360         if (cksel & PM_BIT(CPUDIV))
 361                 shift = PM_BFEXT(CPUSEL, cksel) + 1;
 362
 363         return bus_clk_get_rate(clk, shift);
 364 }
 365
 366 static long cpu_clk_set_rate(struct clk *clk, unsigned long rate, int apply)
 367 {
 368         u32 control;
 369         unsigned long parent_rate, child_div, actual_rate, div;
 370
 371         parent_rate = clk->parent->get_rate(clk->parent);
 372         control = pm_readl(CKSEL);
 373
 374         if (control & PM_BIT(HSBDIV))
 375                 child_div = 1 << (PM_BFEXT(HSBSEL, control) + 1);
 376         else
 377                 child_div = 1;
 378
 379         if (rate > 3 * (parent_rate / 4) || child_div == 1) {
 380                 actual_rate = parent_rate;
 381                 control &= ~PM_BIT(CPUDIV);
 382         } else {
 383                 unsigned int cpusel;
 384                 div = (parent_rate + rate / 2) / rate;
 385                 if (div > child_div)
 386                         div = child_div;
 387                 cpusel = (div > 1) ? (fls(div) - 2) : 0;
 388                 control = PM_BIT(CPUDIV) | PM_BFINS(CPUSEL, cpusel, control);
 389                 actual_rate = parent_rate / (1 << (cpusel + 1));
 390         }
 391
 392         pr_debug("clk %s: new rate %lu (actual rate %lu)\n",
 393                         clk->name, rate, actual_rate);
 394
 395         if (apply)
 396                 pm_writel(CKSEL, control);
 397
 398         return actual_rate;
 399 }
 400
 401 static void hsb_clk_mode(struct clk *clk, int enabled)
 402 {
 403         unsigned long flags;
 404         u32 mask;
 405
 406         spin_lock_irqsave(&pm_lock, flags);
 407         mask = pm_readl(HSB_MASK);
 408         if (enabled)
 409                 mask |= 1 << clk->index;
 410         else
 411                 mask &= ~(1 << clk->index);
 412         pm_writel(HSB_MASK, mask);
 413         spin_unlock_irqrestore(&pm_lock, flags);
 414 }
 415
 416 static unsigned long hsb_clk_get_rate(struct clk *clk)
 417 {
 418         unsigned long cksel, shift = 0;
 419
 420         cksel = pm_readl(CKSEL);
 421         if (cksel & PM_BIT(HSBDIV))
 422                 shift = PM_BFEXT(HSBSEL, cksel) + 1;
 423
 424         return bus_clk_get_rate(clk, shift);
 425 }
 426
 427 void pba_clk_mode(struct clk *clk, int enabled)
 428 {
 429         unsigned long flags;
 430         u32 mask;
 431
 432         spin_lock_irqsave(&pm_lock, flags);
 433         mask = pm_readl(PBA_MASK);
 434         if (enabled)
 435                 mask |= 1 << clk->index;
 436         else
 437                 mask &= ~(1 << clk->index);
 438         pm_writel(PBA_MASK, mask);
 439         spin_unlock_irqrestore(&pm_lock, flags);
 440 }
 441
 442 unsigned long pba_clk_get_rate(struct clk *clk)
 443 {
 444         unsigned long cksel, shift = 0;
 445
 446         cksel = pm_readl(CKSEL);
 447         if (cksel & PM_BIT(PBADIV))
 448                 shift = PM_BFEXT(PBASEL, cksel) + 1;
 449
 450         return bus_clk_get_rate(clk, shift);
 451 }
 452
 453 static void pbb_clk_mode(struct clk *clk, int enabled)
 454 {
 455         unsigned long flags;
 456         u32 mask;
 457
 458         spin_lock_irqsave(&pm_lock, flags);
 459         mask = pm_readl(PBB_MASK);
 460         if (enabled)
 461                 mask |= 1 << clk->index;
 462         else
 463                 mask &= ~(1 << clk->index);
 464         pm_writel(PBB_MASK, mask);
 465         spin_unlock_irqrestore(&pm_lock, flags);
 466 }
 467
 468 static unsigned long pbb_clk_get_rate(struct clk *clk)
 469 {
 470         unsigned long cksel, shift = 0;
 471
 472         cksel = pm_readl(CKSEL);
 473         if (cksel & PM_BIT(PBBDIV))
 474                 shift = PM_BFEXT(PBBSEL, cksel) + 1;
 475
 476         return bus_clk_get_rate(clk, shift);
 477 }
 478
 479 static struct clk cpu_clk = {
 480         .name           = "cpu",
 481         .get_rate       = cpu_clk_get_rate,
 482         .set_rate       = cpu_clk_set_rate,
 483         .users          = 1,
 484 };
 485 static struct clk hsb_clk = {
 486         .name           = "hsb",
 487         .parent         = &cpu_clk,
 488         .get_rate       = hsb_clk_get_rate,
 489 };
 490 static struct clk pba_clk = {
 491         .name           = "pba",
 492         .parent         = &hsb_clk,
 493         .mode           = hsb_clk_mode,
 494         .get_rate       = pba_clk_get_rate,
 495         .index          = 1,
 496 };
 497 static struct clk pbb_clk = {
 498         .name           = "pbb",
 499         .parent         = &hsb_clk,
 500         .mode           = hsb_clk_mode,
 501         .get_rate       = pbb_clk_get_rate,
 502         .users          = 1,
 503         .index          = 2,
 504 };
 505
 506 /* --------------------------------------------------------------------
 507  *  Generic Clock operations
 508  * -------------------------------------------------------------------- */
 509
 510 static void genclk_mode(struct clk *clk, int enabled)
 511 {
 512         u32 control;
 513
 514         control = pm_readl(GCCTRL(clk->index));
 515         if (enabled)
 516                 control |= PM_BIT(CEN);
 517         else
 518                 control &= ~PM_BIT(CEN);
 519         pm_writel(GCCTRL(clk->index), control);
 520 }
 521
 522 static unsigned long genclk_get_rate(struct clk *clk)
 523 {
 524         u32 control;
 525         unsigned long div = 1;
 526
 527         control = pm_readl(GCCTRL(clk->index));
 528         if (control & PM_BIT(DIVEN))
 529                 div = 2 * (PM_BFEXT(DIV, control) + 1);
 530
 531         return clk->parent->get_rate(clk->parent) / div;
 532 }
 533
 534 static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
 535 {
 536         u32 control;
 537         unsigned long parent_rate, actual_rate, div;
 538
 539         parent_rate = clk->parent->get_rate(clk->parent);
 540         control = pm_readl(GCCTRL(clk->index));
 541
 542         if (rate > 3 * parent_rate / 4) {
 543                 actual_rate = parent_rate;
 544                 control &= ~PM_BIT(DIVEN);
 545         } else {
 546                 div = (parent_rate + rate) / (2 * rate) - 1;
 547                 control = PM_BFINS(DIV, div, control) | PM_BIT(DIVEN);
 548                 actual_rate = parent_rate / (2 * (div + 1));
 549         }
 550
 551         dev_dbg(clk->dev, "clk %s: new rate %lu (actual rate %lu)\n",
 552                 clk->name, rate, actual_rate);
 553
 554         if (apply)
 555                 pm_writel(GCCTRL(clk->index), control);
 556
 557         return actual_rate;
 558 }
 559
 560 int genclk_set_parent(struct clk *clk, struct clk *parent)
 561 {
 562         u32 control;
 563
 564         dev_dbg(clk->dev, "clk %s: new parent %s (was %s)\n",
 565                 clk->name, parent->name, clk->parent->name);
 566
 567         control = pm_readl(GCCTRL(clk->index));
 568
 569         if (parent == &osc1 || parent == &pll1)
 570                 control |= PM_BIT(OSCSEL);
 571         else if (parent == &osc0 || parent == &pll0)
 572                 control &= ~PM_BIT(OSCSEL);
 573         else
 574                 return -EINVAL;
 575
 576         if (parent == &pll0 || parent == &pll1)
 577                 control |= PM_BIT(PLLSEL);
 578         else
 579                 control &= ~PM_BIT(PLLSEL);
 580
 581         pm_writel(GCCTRL(clk->index), control);
 582         clk->parent = parent;
 583
 584         return 0;
 585 }
 586
 587 static void __init genclk_init_parent(struct clk *clk)
 588 {
 589         u32 control;
 590         struct clk *parent;
 591
 592         BUG_ON(clk->index > 7);
 593
 594         control = pm_readl(GCCTRL(clk->index));
 595         if (control & PM_BIT(OSCSEL))
 596                 parent = (control & PM_BIT(PLLSEL)) ? &pll1 : &osc1;
 597         else
 598                 parent = (control & PM_BIT(PLLSEL)) ? &pll0 : &osc0;
 599
 600         clk->parent = parent;
 601 }
 602
 603 static struct dw_dma_platform_data dw_dmac0_data = {
 604         .nr_channels    = 3,
 605 };
 606
 607 static struct resource dw_dmac0_resource[] = {
 608         PBMEM(0xff200000),
 609         IRQ(2),
 610 };
 611 DEFINE_DEV_DATA(dw_dmac, 0);
 612 DEV_CLK(hclk, dw_dmac0, hsb, 10);
 613
 614 /* --------------------------------------------------------------------
 615  *  System peripherals
 616  * -------------------------------------------------------------------- */
 617 static struct resource at32_pm0_resource[] = {
 618         {
 619                 .start  = 0xfff00000,
 620                 .end    = 0xfff0007f,
 621                 .flags  = IORESOURCE_MEM,
 622         },
 623         IRQ(20),
 624 };
 625
 626 static struct resource at32ap700x_rtc0_resource[] = {
 627         {
 628                 .start  = 0xfff00080,
 629                 .end    = 0xfff000af,
 630                 .flags  = IORESOURCE_MEM,
 631         },
 632         IRQ(21),
 633 };
 634
 635 static struct resource at32_wdt0_resource[] = {
 636         {
 637                 .start  = 0xfff000b0,
 638                 .end    = 0xfff000cf,
 639                 .flags  = IORESOURCE_MEM,
 640         },
 641 };
 642
 643 static struct resource at32_eic0_resource[] = {
 644         {
 645                 .start  = 0xfff00100,
 646                 .end    = 0xfff0013f,
 647                 .flags  = IORESOURCE_MEM,
 648         },
 649         IRQ(19),
 650 };
 651
 652 DEFINE_DEV(at32_pm, 0);
 653 DEFINE_DEV(at32ap700x_rtc, 0);
 654 DEFINE_DEV(at32_wdt, 0);
 655 DEFINE_DEV(at32_eic, 0);
 656
 657 /*
 658  * Peripheral clock for PM, RTC, WDT and EIC. PM will ensure that this
 659  * is always running.
 660  */
 661 static struct clk at32_pm_pclk = {
 662         .name           = "pclk",
 663         .dev            = &at32_pm0_device.dev,
 664         .parent         = &pbb_clk,
 665         .mode           = pbb_clk_mode,
 666         .get_rate       = pbb_clk_get_rate,
 667         .users          = 1,
 668         .index          = 0,
 669 };
 670
 671 static struct resource intc0_resource[] = {
 672         PBMEM(0xfff00400),
 673 };
 674 struct platform_device at32_intc0_device = {
 675         .name           = "intc",
 676         .id             = 0,
 677         .resource       = intc0_resource,
 678         .num_resources  = ARRAY_SIZE(intc0_resource),
 679 };
 680 DEV_CLK(pclk, at32_intc0, pbb, 1);
 681
 682 static struct clk ebi_clk = {
 683         .name           = "ebi",
 684         .parent         = &hsb_clk,
 685         .mode           = hsb_clk_mode,
 686         .get_rate       = hsb_clk_get_rate,
 687         .users          = 1,
 688 };
 689 static struct clk hramc_clk = {
 690         .name           = "hramc",
 691         .parent         = &hsb_clk,
 692         .mode           = hsb_clk_mode,
 693         .get_rate       = hsb_clk_get_rate,
 694         .users          = 1,
 695         .index          = 3,
 696 };
 697 static struct clk sdramc_clk = {
 698         .name           = "sdramc_clk",
 699         .parent         = &pbb_clk,
 700         .mode           = pbb_clk_mode,
 701         .get_rate       = pbb_clk_get_rate,
 702         .users          = 1,
 703         .index          = 14,
 704 };
 705
 706 static struct resource smc0_resource[] = {
 707         PBMEM(0xfff03400),
 708 };
 709 DEFINE_DEV(smc, 0);
 710 DEV_CLK(pclk, smc0, pbb, 13);
 711 DEV_CLK(mck, smc0, hsb, 0);
 712
 713 static struct platform_device pdc_device = {
 714         .name           = "pdc",
 715         .id             = 0,
 716 };
 717 DEV_CLK(hclk, pdc, hsb, 4);
 718 DEV_CLK(pclk, pdc, pba, 16);
 719
 720 static struct clk pico_clk = {
 721         .name           = "pico",
 722         .parent         = &cpu_clk,
 723         .mode           = cpu_clk_mode,
 724         .get_rate       = cpu_clk_get_rate,
 725         .users          = 1,
 726 };
 727
 728 /* --------------------------------------------------------------------
 729  * HMATRIX
 730  * -------------------------------------------------------------------- */
 731
 732 struct clk at32_hmatrix_clk = {
 733         .name           = "hmatrix_clk",
 734         .parent         = &pbb_clk,
 735         .mode           = pbb_clk_mode,
 736         .get_rate       = pbb_clk_get_rate,
 737         .index          = 2,
 738         .users          = 1,
 739 };
 740
 741 /*
 742  * Set bits in the HMATRIX Special Function Register (SFR) used by the
 743  * External Bus Interface (EBI). This can be used to enable special
 744  * features like CompactFlash support, NAND Flash support, etc. on
 745  * certain chipselects.
 746  */
 747 static inline void set_ebi_sfr_bits(u32 mask)
 748 {
 749         hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, mask);
 750 }
 751
 752 /* --------------------------------------------------------------------
 753  *  Timer/Counter (TC)
 754  * -------------------------------------------------------------------- */
 755
 756 static struct resource at32_tcb0_resource[] = {
 757         PBMEM(0xfff00c00),
 758         IRQ(22),
 759 };
 760 static struct platform_device at32_tcb0_device = {
 761         .name           = "atmel_tcb",
 762         .id             = 0,
 763         .resource       = at32_tcb0_resource,
 764         .num_resources  = ARRAY_SIZE(at32_tcb0_resource),
 765 };
 766 DEV_CLK(t0_clk, at32_tcb0, pbb, 3);
 767
 768 static struct resource at32_tcb1_resource[] = {
 769         PBMEM(0xfff01000),
 770         IRQ(23),
 771 };
 772 static struct platform_device at32_tcb1_device = {
 773         .name           = "atmel_tcb",
 774         .id             = 1,
 775         .resource       = at32_tcb1_resource,
 776         .num_resources  = ARRAY_SIZE(at32_tcb1_resource),
 777 };
 778 DEV_CLK(t0_clk, at32_tcb1, pbb, 4);
 779
 780 /* --------------------------------------------------------------------
 781  *  PIO
 782  * -------------------------------------------------------------------- */
 783
 784 static struct resource pio0_resource[] = {
 785         PBMEM(0xffe02800),
 786         IRQ(13),
 787 };
 788 DEFINE_DEV(pio, 0);
 789 DEV_CLK(mck, pio0, pba, 10);
 790
 791 static struct resource pio1_resource[] = {
 792         PBMEM(0xffe02c00),
 793         IRQ(14),
 794 };
 795 DEFINE_DEV(pio, 1);
 796 DEV_CLK(mck, pio1, pba, 11);
 797
 798 static struct resource pio2_resource[] = {
 799         PBMEM(0xffe03000),
 800         IRQ(15),
 801 };
 802 DEFINE_DEV(pio, 2);
 803 DEV_CLK(mck, pio2, pba, 12);
 804
 805 static struct resource pio3_resource[] = {
 806         PBMEM(0xffe03400),
 807         IRQ(16),
 808 };
 809 DEFINE_DEV(pio, 3);
 810 DEV_CLK(mck, pio3, pba, 13);
 811
 812 static struct resource pio4_resource[] = {
 813         PBMEM(0xffe03800),
 814         IRQ(17),
 815 };
 816 DEFINE_DEV(pio, 4);
 817 DEV_CLK(mck, pio4, pba, 14);
 818
 819 static int __init system_device_init(void)
 820 {
 821         platform_device_register(&at32_pm0_device);
 822         platform_device_register(&at32_intc0_device);
 823         platform_device_register(&at32ap700x_rtc0_device);
 824         platform_device_register(&at32_wdt0_device);
 825         platform_device_register(&at32_eic0_device);
 826         platform_device_register(&smc0_device);
 827         platform_device_register(&pdc_device);
 828         platform_device_register(&dw_dmac0_device);
 829
 830         platform_device_register(&at32_tcb0_device);
 831         platform_device_register(&at32_tcb1_device);
 832
 833         platform_device_register(&pio0_device);
 834         platform_device_register(&pio1_device);
 835         platform_device_register(&pio2_device);
 836         platform_device_register(&pio3_device);
 837         platform_device_register(&pio4_device);
 838
 839         return 0;
 840 }
 841 core_initcall(system_device_init);
 842
 843 /* --------------------------------------------------------------------
 844  *  PSIF
 845  * -------------------------------------------------------------------- */
 846 static struct resource atmel_psif0_resource[] __initdata = {
 847         {
 848                 .start  = 0xffe03c00,
 849                 .end    = 0xffe03cff,
 850                 .flags  = IORESOURCE_MEM,
 851         },
 852         IRQ(18),
 853 };
 854 static struct clk atmel_psif0_pclk = {
 855         .name           = "pclk",
 856         .parent         = &pba_clk,
 857         .mode           = pba_clk_mode,
 858         .get_rate       = pba_clk_get_rate,
 859         .index          = 15,
 860 };
 861
 862 static struct resource atmel_psif1_resource[] __initdata = {
 863         {
 864                 .start  = 0xffe03d00,
 865                 .end    = 0xffe03dff,
 866                 .flags  = IORESOURCE_MEM,
 867         },
 868         IRQ(18),
 869 };
 870 static struct clk atmel_psif1_pclk = {
 871         .name           = "pclk",
 872         .parent         = &pba_clk,
 873         .mode           = pba_clk_mode,
 874         .get_rate       = pba_clk_get_rate,
 875         .index          = 15,
 876 };
 877
 878 struct platform_device *__init at32_add_device_psif(unsigned int id)
 879 {
 880         struct platform_device *pdev;
 881         u32 pin_mask;
 882
 883         if (!(id == 0 || id == 1))
 884                 return NULL;
 885
 886         pdev = platform_device_alloc("atmel_psif", id);
 887         if (!pdev)
 888                 return NULL;
 889
 890         switch (id) {
 891         case 0:
 892                 pin_mask  = (1 << 8) | (1 << 9); /* CLOCK & DATA */
 893
 894                 if (platform_device_add_resources(pdev, atmel_psif0_resource,
 895                                         ARRAY_SIZE(atmel_psif0_resource)))
 896                         goto err_add_resources;
 897                 atmel_psif0_pclk.dev = &pdev->dev;
 898                 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
 899                 break;
 900         case 1:
 901                 pin_mask  = (1 << 11) | (1 << 12); /* CLOCK & DATA */
 902
 903                 if (platform_device_add_resources(pdev, atmel_psif1_resource,
 904                                         ARRAY_SIZE(atmel_psif1_resource)))
 905                         goto err_add_resources;
 906                 atmel_psif1_pclk.dev = &pdev->dev;
 907                 select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
 908                 break;
 909         default:
 910                 return NULL;
 911         }
 912
 913         platform_device_add(pdev);
 914         return pdev;
 915
 916 err_add_resources:
 917         platform_device_put(pdev);
 918         return NULL;
 919 }
 920
 921 /* --------------------------------------------------------------------
 922  *  USART
 923  * -------------------------------------------------------------------- */
 924
 925 static struct atmel_uart_data atmel_usart0_data = {
 926         .use_dma_tx     = 1,
 927         .use_dma_rx     = 1,
 928 };
 929 static struct resource atmel_usart0_resource[] = {
 930         PBMEM(0xffe00c00),
 931         IRQ(6),
 932 };
 933 DEFINE_DEV_DATA(atmel_usart, 0);
 934 DEV_CLK(usart, atmel_usart0, pba, 3);
 935
 936 static struct atmel_uart_data atmel_usart1_data = {
 937         .use_dma_tx     = 1,
 938         .use_dma_rx     = 1,
 939 };
 940 static struct resource atmel_usart1_resource[] = {
 941         PBMEM(0xffe01000),
 942         IRQ(7),
 943 };
 944 DEFINE_DEV_DATA(atmel_usart, 1);
 945 DEV_CLK(usart, atmel_usart1, pba, 4);
 946
 947 static struct atmel_uart_data atmel_usart2_data = {
 948         .use_dma_tx     = 1,
 949         .use_dma_rx     = 1,
 950 };
 951 static struct resource atmel_usart2_resource[] = {
 952         PBMEM(0xffe01400),
 953         IRQ(8),
 954 };
 955 DEFINE_DEV_DATA(atmel_usart, 2);
 956 DEV_CLK(usart, atmel_usart2, pba, 5);
 957
 958 static struct atmel_uart_data atmel_usart3_data = {
 959         .use_dma_tx     = 1,
 960         .use_dma_rx     = 1,
 961 };
 962 static struct resource atmel_usart3_resource[] = {
 963         PBMEM(0xffe01800),
 964         IRQ(9),
 965 };
 966 DEFINE_DEV_DATA(atmel_usart, 3);
 967 DEV_CLK(usart, atmel_usart3, pba, 6);
 968
 969 static inline void configure_usart0_pins(int flags)
 970 {
 971         u32 pin_mask = (1 << 8) | (1 << 9); /* RXD & TXD */
 972         if (flags & ATMEL_USART_RTS)    pin_mask |= (1 << 6);
 973         if (flags & ATMEL_USART_CTS)    pin_mask |= (1 << 7);
 974         if (flags & ATMEL_USART_CLK)    pin_mask |= (1 << 10);
 975
 976         select_peripheral(PIOA, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP);
 977 }
 978
 979 static inline void configure_usart1_pins(int flags)
 980 {
 981         u32 pin_mask = (1 << 17) | (1 << 18); /* RXD & TXD */
 982         if (flags & ATMEL_USART_RTS)    pin_mask |= (1 << 19);
 983         if (flags & ATMEL_USART_CTS)    pin_mask |= (1 << 20);
 984         if (flags & ATMEL_USART_CLK)    pin_mask |= (1 << 16);
 985
 986         select_peripheral(PIOA, pin_mask, PERIPH_A, AT32_GPIOF_PULLUP);
 987 }
 988
 989 static inline void configure_usart2_pins(int flags)
 990 {
 991         u32 pin_mask = (1 << 26) | (1 << 27); /* RXD & TXD */
 992         if (flags & ATMEL_USART_RTS)    pin_mask |= (1 << 30);
 993         if (flags & ATMEL_USART_CTS)    pin_mask |= (1 << 29);
 994         if (flags & ATMEL_USART_CLK)    pin_mask |= (1 << 28);
 995
 996         select_peripheral(PIOB, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP);
 997 }
 998
 999 static inline void configure_usart3_pins(int flags)
1000 {
1001         u32 pin_mask = (1 << 18) | (1 << 17); /* RXD & TXD */
1002         if (flags & ATMEL_USART_RTS)    pin_mask |= (1 << 16);
1003         if (flags & ATMEL_USART_CTS)    pin_mask |= (1 << 15);
1004         if (flags & ATMEL_USART_CLK)    pin_mask |= (1 << 19);
1005
1006         select_peripheral(PIOB, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP);
1007 }
1008
1009 static struct platform_device *__initdata at32_usarts[4];
1010
1011 void __init at32_map_usart(unsigned int hw_id, unsigned int line, int flags)
1012 {
1013         struct platform_device *pdev;
1014
1015         switch (hw_id) {
1016         case 0:
1017                 pdev = &atmel_usart0_device;
1018                 configure_usart0_pins(flags);
1019                 break;
1020         case 1:
1021                 pdev = &atmel_usart1_device;
1022                 configure_usart1_pins(flags);
1023                 break;
1024         case 2:
1025                 pdev = &atmel_usart2_device;
1026                 configure_usart2_pins(flags);
1027                 break;
1028         case 3:
1029                 pdev = &atmel_usart3_device;
1030                 configure_usart3_pins(flags);
1031                 break;
1032         default:
1033                 return;
1034         }
1035
1036         if (PXSEG(pdev->resource[0].start) == P4SEG) {
1037                 /* Addresses in the P4 segment are permanently mapped 1:1 */
1038                 struct atmel_uart_data *data = pdev->dev.platform_data;
1039                 data->regs = (void __iomem *)pdev->resource[0].start;
1040         }
1041
1042         pdev->id = line;
1043         at32_usarts[line] = pdev;
1044 }
1045
1046 struct platform_device *__init at32_add_device_usart(unsigned int id)
1047 {
1048         platform_device_register(at32_usarts[id]);
1049         return at32_usarts[id];
1050 }
1051
1052 struct platform_device *atmel_default_console_device;
1053
1054 void __init at32_setup_serial_console(unsigned int usart_id)
1055 {
1056         atmel_default_console_device = at32_usarts[usart_id];
1057 }
1058
1059 /* --------------------------------------------------------------------
1060  *  Ethernet
1061  * -------------------------------------------------------------------- */
1062
1063 #ifdef CONFIG_CPU_AT32AP7000
1064 static struct eth_platform_data macb0_data;
1065 static struct resource macb0_resource[] = {
1066         PBMEM(0xfff01800),
1067         IRQ(25),
1068 };
1069 DEFINE_DEV_DATA(macb, 0);
1070 DEV_CLK(hclk, macb0, hsb, 8);
1071 DEV_CLK(pclk, macb0, pbb, 6);
1072
1073 static struct eth_platform_data macb1_data;
1074 static struct resource macb1_resource[] = {
1075         PBMEM(0xfff01c00),
1076         IRQ(26),
1077 };
1078 DEFINE_DEV_DATA(macb, 1);
1079 DEV_CLK(hclk, macb1, hsb, 9);
1080 DEV_CLK(pclk, macb1, pbb, 7);
1081
1082 struct platform_device *__init
1083 at32_add_device_eth(unsigned int id, struct eth_platform_data *data)
1084 {
1085         struct platform_device *pdev;
1086         u32 pin_mask;
1087
1088         switch (id) {
1089         case 0:
1090                 pdev = &macb0_device;
1091
1092                 pin_mask  = (1 << 3);   /* TXD0 */
1093                 pin_mask |= (1 << 4);   /* TXD1 */
1094                 pin_mask |= (1 << 7);   /* TXEN */
1095                 pin_mask |= (1 << 8);   /* TXCK */
1096                 pin_mask |= (1 << 9);   /* RXD0 */
1097                 pin_mask |= (1 << 10);  /* RXD1 */
1098                 pin_mask |= (1 << 13);  /* RXER */
1099                 pin_mask |= (1 << 15);  /* RXDV */
1100                 pin_mask |= (1 << 16);  /* MDC  */
1101                 pin_mask |= (1 << 17);  /* MDIO */
1102
1103                 if (!data->is_rmii) {
1104                         pin_mask |= (1 << 0);   /* COL  */
1105                         pin_mask |= (1 << 1);   /* CRS  */
1106                         pin_mask |= (1 << 2);   /* TXER */
1107                         pin_mask |= (1 << 5);   /* TXD2 */
1108                         pin_mask |= (1 << 6);   /* TXD3 */
1109                         pin_mask |= (1 << 11);  /* RXD2 */
1110                         pin_mask |= (1 << 12);  /* RXD3 */
1111                         pin_mask |= (1 << 14);  /* RXCK */
1112 #ifndef CONFIG_BOARD_MIMC200
1113                         pin_mask |= (1 << 18);  /* SPD  */
1114 #endif
1115                 }
1116
1117                 select_peripheral(PIOC, pin_mask, PERIPH_A, 0);
1118
1119                 break;
1120
1121         case 1:
1122                 pdev = &macb1_device;
1123
1124                 pin_mask  = (1 << 13);  /* TXD0 */
1125                 pin_mask |= (1 << 14);  /* TXD1 */
1126                 pin_mask |= (1 << 11);  /* TXEN */
1127                 pin_mask |= (1 << 12);  /* TXCK */
1128                 pin_mask |= (1 << 10);  /* RXD0 */
1129                 pin_mask |= (1 << 6);   /* RXD1 */
1130                 pin_mask |= (1 << 5);   /* RXER */
1131                 pin_mask |= (1 << 4);   /* RXDV */
1132                 pin_mask |= (1 << 3);   /* MDC  */
1133                 pin_mask |= (1 << 2);   /* MDIO */
1134
1135 #ifndef CONFIG_BOARD_MIMC200
1136                 if (!data->is_rmii)
1137                         pin_mask |= (1 << 15);  /* SPD  */
1138 #endif
1139
1140                 select_peripheral(PIOD, pin_mask, PERIPH_B, 0);
1141
1142                 if (!data->is_rmii) {
1143                         pin_mask  = (1 << 19);  /* COL  */
1144                         pin_mask |= (1 << 23);  /* CRS  */
1145                         pin_mask |= (1 << 26);  /* TXER */
1146                         pin_mask |= (1 << 27);  /* TXD2 */
1147                         pin_mask |= (1 << 28);  /* TXD3 */
1148                         pin_mask |= (1 << 29);  /* RXD2 */
1149                         pin_mask |= (1 << 30);  /* RXD3 */
1150                         pin_mask |= (1 << 24);  /* RXCK */
1151
1152                         select_peripheral(PIOC, pin_mask, PERIPH_B, 0);
1153                 }
1154                 break;
1155
1156         default:
1157                 return NULL;
1158         }
1159
1160         memcpy(pdev->dev.platform_data, data, sizeof(struct eth_platform_data));
1161         platform_device_register(pdev);
1162
1163         return pdev;
1164 }
1165 #endif
1166
1167 /* --------------------------------------------------------------------
1168  *  SPI
1169  * -------------------------------------------------------------------- */
1170 static struct resource atmel_spi0_resource[] = {
1171         PBMEM(0xffe00000),
1172         IRQ(3),
1173 };
1174 DEFINE_DEV(atmel_spi, 0);
1175 DEV_CLK(spi_clk, atmel_spi0, pba, 0);
1176
1177 static struct resource atmel_spi1_resource[] = {
1178         PBMEM(0xffe00400),
1179         IRQ(4),
1180 };
1181 DEFINE_DEV(atmel_spi, 1);
1182 DEV_CLK(spi_clk, atmel_spi1, pba, 1);
1183
1184 static void __init
1185 at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b,
1186                       unsigned int n, const u8 *pins)
1187 {
1188         unsigned int pin, mode;
1189
1190         for (; n; n--, b++) {
1191                 b->bus_num = bus_num;
1192                 if (b->chip_select >= 4)
1193                         continue;
1194                 pin = (unsigned)b->controller_data;
1195                 if (!pin) {
1196                         pin = pins[b->chip_select];
1197                         b->controller_data = (void *)pin;
1198                 }
1199                 mode = AT32_GPIOF_OUTPUT;
1200                 if (!(b->mode & SPI_CS_HIGH))
1201                         mode |= AT32_GPIOF_HIGH;
1202                 at32_select_gpio(pin, mode);
1203         }
1204 }
1205
1206 struct platform_device *__init
1207 at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
1208 {
1209         /*
1210          * Manage the chipselects as GPIOs, normally using the same pins
1211          * the SPI controller expects; but boards can use other pins.
1212          */
1213         static u8 __initdata spi0_pins[] =
1214                 { GPIO_PIN_PA(3), GPIO_PIN_PA(4),
1215                   GPIO_PIN_PA(5), GPIO_PIN_PA(20), };
1216         static u8 __initdata spi1_pins[] =
1217                 { GPIO_PIN_PB(2), GPIO_PIN_PB(3),
1218                   GPIO_PIN_PB(4), GPIO_PIN_PA(27), };
1219         struct platform_device *pdev;
1220         u32 pin_mask;
1221
1222         switch (id) {
1223         case 0:
1224                 pdev = &atmel_spi0_device;
1225                 pin_mask  = (1 << 1) | (1 << 2);        /* MOSI & SCK */
1226
1227                 /* pullup MISO so a level is always defined */
1228                 select_peripheral(PIOA, (1 << 0), PERIPH_A, AT32_GPIOF_PULLUP);
1229                 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1230
1231                 at32_spi_setup_slaves(0, b, n, spi0_pins);
1232                 break;
1233
1234         case 1:
1235                 pdev = &atmel_spi1_device;
1236                 pin_mask  = (1 << 1) | (1 << 5);        /* MOSI */
1237
1238                 /* pullup MISO so a level is always defined */
1239                 select_peripheral(PIOB, (1 << 0), PERIPH_B, AT32_GPIOF_PULLUP);
1240                 select_peripheral(PIOB, pin_mask, PERIPH_B, 0);
1241
1242                 at32_spi_setup_slaves(1, b, n, spi1_pins);
1243                 break;
1244
1245         default:
1246                 return NULL;
1247         }
1248
1249         spi_register_board_info(b, n);
1250         platform_device_register(pdev);
1251         return pdev;
1252 }
1253
1254 /* --------------------------------------------------------------------
1255  *  TWI
1256  * -------------------------------------------------------------------- */
1257 static struct resource atmel_twi0_resource[] __initdata = {
1258         PBMEM(0xffe00800),
1259         IRQ(5),
1260 };
1261 static struct clk atmel_twi0_pclk = {
1262         .name           = "twi_pclk",
1263         .parent         = &pba_clk,
1264         .mode           = pba_clk_mode,
1265         .get_rate       = pba_clk_get_rate,
1266         .index          = 2,
1267 };
1268
1269 struct platform_device *__init at32_add_device_twi(unsigned int id,
1270                                                     struct i2c_board_info *b,
1271                                                     unsigned int n)
1272 {
1273         struct platform_device *pdev;
1274         u32 pin_mask;
1275
1276         if (id != 0)
1277                 return NULL;
1278
1279         pdev = platform_device_alloc("atmel_twi", id);
1280         if (!pdev)
1281                 return NULL;
1282
1283         if (platform_device_add_resources(pdev, atmel_twi0_resource,
1284                                 ARRAY_SIZE(atmel_twi0_resource)))
1285                 goto err_add_resources;
1286
1287         pin_mask  = (1 << 6) | (1 << 7);        /* SDA & SDL */
1288
1289         select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1290
1291         atmel_twi0_pclk.dev = &pdev->dev;
1292
1293         if (b)
1294                 i2c_register_board_info(id, b, n);
1295
1296         platform_device_add(pdev);
1297         return pdev;
1298
1299 err_add_resources:
1300         platform_device_put(pdev);
1301         return NULL;
1302 }
1303
1304 /* --------------------------------------------------------------------
1305  * MMC
1306  * -------------------------------------------------------------------- */
1307 static struct resource atmel_mci0_resource[] __initdata = {
1308         PBMEM(0xfff02400),
1309         IRQ(28),
1310 };
1311 static struct clk atmel_mci0_pclk = {
1312         .name           = "mci_clk",
1313         .parent         = &pbb_clk,
1314         .mode           = pbb_clk_mode,
1315         .get_rate       = pbb_clk_get_rate,
1316         .index          = 9,
1317 };
1318
1319 struct platform_device *__init
1320 at32_add_device_mci(unsigned int id, struct mci_platform_data *data)
1321 {
1322         struct platform_device          *pdev;
1323         struct dw_dma_slave             *dws = &data->dma_slave;
1324         u32                             pioa_mask;
1325         u32                             piob_mask;
1326
1327         if (id != 0 || !data)
1328                 return NULL;
1329
1330         /* Must have at least one usable slot */
1331         if (!data->slot[0].bus_width && !data->slot[1].bus_width)
1332                 return NULL;
1333
1334         pdev = platform_device_alloc("atmel_mci", id);
1335         if (!pdev)
1336                 goto fail;
1337
1338         if (platform_device_add_resources(pdev, atmel_mci0_resource,
1339                                 ARRAY_SIZE(atmel_mci0_resource)))
1340                 goto fail;
1341
1342         dws->dma_dev = &dw_dmac0_device.dev;
1343         dws->reg_width = DW_DMA_SLAVE_WIDTH_32BIT;
1344         dws->cfg_hi = (DWC_CFGH_SRC_PER(0)
1345                                 | DWC_CFGH_DST_PER(1));
1346         dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL
1347                                 | DWC_CFGL_HS_SRC_POL);
1348
1349         if (platform_device_add_data(pdev, data,
1350                                 sizeof(struct mci_platform_data)))
1351                 goto fail;
1352
1353         /* CLK line is common to both slots */
1354         pioa_mask = 1 << 10;
1355
1356         switch (data->slot[0].bus_width) {
1357         case 4:
1358                 pioa_mask |= 1 << 13;           /* DATA1 */
1359                 pioa_mask |= 1 << 14;           /* DATA2 */
1360                 pioa_mask |= 1 << 15;           /* DATA3 */
1361                 /* fall through */
1362         case 1:
1363                 pioa_mask |= 1 << 11;           /* CMD   */
1364                 pioa_mask |= 1 << 12;           /* DATA0 */
1365
1366                 if (gpio_is_valid(data->slot[0].detect_pin))
1367                         at32_select_gpio(data->slot[0].detect_pin, 0);
1368                 if (gpio_is_valid(data->slot[0].wp_pin))
1369                         at32_select_gpio(data->slot[0].wp_pin, 0);
1370                 break;
1371         case 0:
1372                 /* Slot is unused */
1373                 break;
1374         default:
1375                 goto fail;
1376         }
1377
1378         select_peripheral(PIOA, pioa_mask, PERIPH_A, 0);
1379         piob_mask = 0;
1380
1381         switch (data->slot[1].bus_width) {
1382         case 4:
1383                 piob_mask |= 1 <<  8;           /* DATA1 */
1384                 piob_mask |= 1 <<  9;           /* DATA2 */
1385                 piob_mask |= 1 << 10;           /* DATA3 */
1386                 /* fall through */
1387         case 1:
1388                 piob_mask |= 1 <<  6;           /* CMD   */
1389                 piob_mask |= 1 <<  7;           /* DATA0 */
1390                 select_peripheral(PIOB, piob_mask, PERIPH_B, 0);
1391
1392                 if (gpio_is_valid(data->slot[1].detect_pin))
1393                         at32_select_gpio(data->slot[1].detect_pin, 0);
1394                 if (gpio_is_valid(data->slot[1].wp_pin))
1395                         at32_select_gpio(data->slot[1].wp_pin, 0);
1396                 break;
1397         case 0:
1398                 /* Slot is unused */
1399                 break;
1400         default:
1401                 if (!data->slot[0].bus_width)
1402                         goto fail;
1403
1404                 data->slot[1].bus_width = 0;
1405                 break;
1406         }
1407
1408         atmel_mci0_pclk.dev = &pdev->dev;
1409
1410         platform_device_add(pdev);
1411         return pdev;
1412
1413 fail:
1414         platform_device_put(pdev);
1415         return NULL;
1416 }
1417
1418 /* --------------------------------------------------------------------
1419  *  LCDC
1420  * -------------------------------------------------------------------- */
1421 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
1422 static struct atmel_lcdfb_info atmel_lcdfb0_data;
1423 static struct resource atmel_lcdfb0_resource[] = {
1424         {
1425                 .start          = 0xff000000,
1426                 .end            = 0xff000fff,
1427                 .flags          = IORESOURCE_MEM,
1428         },
1429         IRQ(1),
1430         {
1431                 /* Placeholder for pre-allocated fb memory */
1432                 .start          = 0x00000000,
1433                 .end            = 0x00000000,
1434                 .flags          = 0,
1435         },
1436 };
1437 DEFINE_DEV_DATA(atmel_lcdfb, 0);
1438 DEV_CLK(hck1, atmel_lcdfb0, hsb, 7);
1439 static struct clk atmel_lcdfb0_pixclk = {
1440         .name           = "lcdc_clk",
1441         .dev            = &atmel_lcdfb0_device.dev,
1442         .mode           = genclk_mode,
1443         .get_rate       = genclk_get_rate,
1444         .set_rate       = genclk_set_rate,
1445         .set_parent     = genclk_set_parent,
1446         .index          = 7,
1447 };
1448
1449 struct platform_device *__init
1450 at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
1451                      unsigned long fbmem_start, unsigned long fbmem_len,
1452                      u64 pin_mask)
1453 {
1454         struct platform_device *pdev;
1455         struct atmel_lcdfb_info *info;
1456         struct fb_monspecs *monspecs;
1457         struct fb_videomode *modedb;
1458         unsigned int modedb_size;
1459         u32 portc_mask, portd_mask, porte_mask;
1460
1461         /*
1462          * Do a deep copy of the fb data, monspecs and modedb. Make
1463          * sure all allocations are done before setting up the
1464          * portmux.
1465          */
1466         monspecs = kmemdup(data->default_monspecs,
1467                            sizeof(struct fb_monspecs), GFP_KERNEL);
1468         if (!monspecs)
1469                 return NULL;
1470
1471         modedb_size = sizeof(struct fb_videomode) * monspecs->modedb_len;
1472         modedb = kmemdup(monspecs->modedb, modedb_size, GFP_KERNEL);
1473         if (!modedb)
1474                 goto err_dup_modedb;
1475         monspecs->modedb = modedb;
1476
1477         switch (id) {
1478         case 0:
1479                 pdev = &atmel_lcdfb0_device;
1480
1481                 if (pin_mask == 0ULL)
1482                         /* Default to "full" lcdc control signals and 24bit */
1483                         pin_mask = ATMEL_LCDC_PRI_24BIT | ATMEL_LCDC_PRI_CONTROL;
1484
1485                 /* LCDC on port C */
1486                 portc_mask = pin_mask & 0xfff80000;
1487                 select_peripheral(PIOC, portc_mask, PERIPH_A, 0);
1488
1489                 /* LCDC on port D */
1490                 portd_mask = pin_mask & 0x0003ffff;
1491                 select_peripheral(PIOD, portd_mask, PERIPH_A, 0);
1492
1493                 /* LCDC on port E */
1494                 porte_mask = (pin_mask >> 32) & 0x0007ffff;
1495                 select_peripheral(PIOE, porte_mask, PERIPH_B, 0);
1496
1497                 clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
1498                 clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
1499                 break;
1500
1501         default:
1502                 goto err_invalid_id;
1503         }
1504
1505         if (fbmem_len) {
1506                 pdev->resource[2].start = fbmem_start;
1507                 pdev->resource[2].end = fbmem_start + fbmem_len - 1;
1508                 pdev->resource[2].flags = IORESOURCE_MEM;
1509         }
1510
1511         info = pdev->dev.platform_data;
1512         memcpy(info, data, sizeof(struct atmel_lcdfb_info));
1513         info->default_monspecs = monspecs;
1514
1515         platform_device_register(pdev);
1516         return pdev;
1517
1518 err_invalid_id:
1519         kfree(modedb);
1520 err_dup_modedb:
1521         kfree(monspecs);
1522         return NULL;
1523 }
1524 #endif
1525
1526 /* --------------------------------------------------------------------
1527  *  PWM
1528  * -------------------------------------------------------------------- */
1529 static struct resource atmel_pwm0_resource[] __initdata = {
1530         PBMEM(0xfff01400),
1531         IRQ(24),
1532 };
1533 static struct clk atmel_pwm0_mck = {
1534         .name           = "pwm_clk",
1535         .parent         = &pbb_clk,
1536         .mode           = pbb_clk_mode,
1537         .get_rate       = pbb_clk_get_rate,
1538         .index          = 5,
1539 };
1540
1541 struct platform_device *__init at32_add_device_pwm(u32 mask)
1542 {
1543         struct platform_device *pdev;
1544         u32 pin_mask;
1545
1546         if (!mask)
1547                 return NULL;
1548
1549         pdev = platform_device_alloc("atmel_pwm", 0);
1550         if (!pdev)
1551                 return NULL;
1552
1553         if (platform_device_add_resources(pdev, atmel_pwm0_resource,
1554                                 ARRAY_SIZE(atmel_pwm0_resource)))
1555                 goto out_free_pdev;
1556
1557         if (platform_device_add_data(pdev, &mask, sizeof(mask)))
1558                 goto out_free_pdev;
1559
1560         pin_mask = 0;
1561         if (mask & (1 << 0))
1562                 pin_mask |= (1 << 28);
1563         if (mask & (1 << 1))
1564                 pin_mask |= (1 << 29);
1565         if (pin_mask > 0)
1566                 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1567
1568         pin_mask = 0;
1569         if (mask & (1 << 2))
1570                 pin_mask |= (1 << 21);
1571         if (mask & (1 << 3))
1572                 pin_mask |= (1 << 22);
1573         if (pin_mask > 0)
1574                 select_peripheral(PIOA, pin_mask, PERIPH_B, 0);
1575
1576         atmel_pwm0_mck.dev = &pdev->dev;
1577
1578         platform_device_add(pdev);
1579
1580         return pdev;
1581
1582 out_free_pdev:
1583         platform_device_put(pdev);
1584         return NULL;
1585 }
1586
1587 /* --------------------------------------------------------------------
1588  *  SSC
1589  * -------------------------------------------------------------------- */
1590 static struct resource ssc0_resource[] = {
1591         PBMEM(0xffe01c00),
1592         IRQ(10),
1593 };
1594 DEFINE_DEV(ssc, 0);
1595 DEV_CLK(pclk, ssc0, pba, 7);
1596
1597 static struct resource ssc1_resource[] = {
1598         PBMEM(0xffe02000),
1599         IRQ(11),
1600 };
1601 DEFINE_DEV(ssc, 1);
1602 DEV_CLK(pclk, ssc1, pba, 8);
1603
1604 static struct resource ssc2_resource[] = {
1605         PBMEM(0xffe02400),
1606         IRQ(12),
1607 };
1608 DEFINE_DEV(ssc, 2);
1609 DEV_CLK(pclk, ssc2, pba, 9);
1610
1611 struct platform_device *__init
1612 at32_add_device_ssc(unsigned int id, unsigned int flags)
1613 {
1614         struct platform_device *pdev;
1615         u32 pin_mask = 0;
1616
1617         switch (id) {
1618         case 0:
1619                 pdev = &ssc0_device;
1620                 if (flags & ATMEL_SSC_RF)
1621                         pin_mask |= (1 << 21);  /* RF */
1622                 if (flags & ATMEL_SSC_RK)
1623                         pin_mask |= (1 << 22);  /* RK */
1624                 if (flags & ATMEL_SSC_TK)
1625                         pin_mask |= (1 << 23);  /* TK */
1626                 if (flags & ATMEL_SSC_TF)
1627                         pin_mask |= (1 << 24);  /* TF */
1628                 if (flags & ATMEL_SSC_TD)
1629                         pin_mask |= (1 << 25);  /* TD */
1630                 if (flags & ATMEL_SSC_RD)
1631                         pin_mask |= (1 << 26);  /* RD */
1632
1633                 if (pin_mask > 0)
1634                         select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1635
1636                 break;
1637         case 1:
1638                 pdev = &ssc1_device;
1639                 if (flags & ATMEL_SSC_RF)
1640                         pin_mask |= (1 << 0);   /* RF */
1641                 if (flags & ATMEL_SSC_RK)
1642                         pin_mask |= (1 << 1);   /* RK */
1643                 if (flags & ATMEL_SSC_TK)
1644                         pin_mask |= (1 << 2);   /* TK */
1645                 if (flags & ATMEL_SSC_TF)
1646                         pin_mask |= (1 << 3);   /* TF */
1647                 if (flags & ATMEL_SSC_TD)
1648                         pin_mask |= (1 << 4);   /* TD */
1649                 if (flags & ATMEL_SSC_RD)
1650                         pin_mask |= (1 << 5);   /* RD */
1651
1652                 if (pin_mask > 0)
1653                         select_peripheral(PIOA, pin_mask, PERIPH_B, 0);
1654
1655                 break;
1656         case 2:
1657                 pdev = &ssc2_device;
1658                 if (flags & ATMEL_SSC_TD)
1659                         pin_mask |= (1 << 13);  /* TD */
1660                 if (flags & ATMEL_SSC_RD)
1661                         pin_mask |= (1 << 14);  /* RD */
1662                 if (flags & ATMEL_SSC_TK)
1663                         pin_mask |= (1 << 15);  /* TK */
1664                 if (flags & ATMEL_SSC_TF)
1665                         pin_mask |= (1 << 16);  /* TF */
1666                 if (flags & ATMEL_SSC_RF)
1667                         pin_mask |= (1 << 17);  /* RF */
1668                 if (flags & ATMEL_SSC_RK)
1669                         pin_mask |= (1 << 18);  /* RK */
1670
1671                 if (pin_mask > 0)
1672                         select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
1673
1674                 break;
1675         default:
1676                 return NULL;
1677         }
1678
1679         platform_device_register(pdev);
1680         return pdev;
1681 }
1682
1683 /* --------------------------------------------------------------------
1684  *  USB Device Controller
1685  * -------------------------------------------------------------------- */
1686 static struct resource usba0_resource[] __initdata = {
1687         {
1688                 .start          = 0xff300000,
1689                 .end            = 0xff3fffff,
1690                 .flags          = IORESOURCE_MEM,
1691         }, {
1692                 .start          = 0xfff03000,
1693                 .end            = 0xfff033ff,
1694                 .flags          = IORESOURCE_MEM,
1695         },
1696         IRQ(31),
1697 };
1698 static struct clk usba0_pclk = {
1699         .name           = "pclk",
1700         .parent         = &pbb_clk,
1701         .mode           = pbb_clk_mode,
1702         .get_rate       = pbb_clk_get_rate,
1703         .index          = 12,
1704 };
1705 static struct clk usba0_hclk = {
1706         .name           = "hclk",
1707         .parent         = &hsb_clk,
1708         .mode           = hsb_clk_mode,
1709         .get_rate       = hsb_clk_get_rate,
1710         .index          = 6,
1711 };
1712
1713 #define EP(nam, idx, maxpkt, maxbk, dma, isoc)                  \
1714         [idx] = {                                               \
1715                 .name           = nam,                          \
1716                 .index          = idx,                          \
1717                 .fifo_size      = maxpkt,                       \
1718                 .nr_banks       = maxbk,                        \
1719                 .can_dma        = dma,                          \
1720                 .can_isoc       = isoc,                         \
1721         }
1722
1723 static struct usba_ep_data at32_usba_ep[] __initdata = {
1724         EP("ep0",     0,   64, 1, 0, 0),
1725         EP("ep1",     1,  512, 2, 1, 1),
1726         EP("ep2",     2,  512, 2, 1, 1),
1727         EP("ep3-int", 3,   64, 3, 1, 0),
1728         EP("ep4-int", 4,   64, 3, 1, 0),
1729         EP("ep5",     5, 1024, 3, 1, 1),
1730         EP("ep6",     6, 1024, 3, 1, 1),
1731 };
1732
1733 #undef EP
1734
1735 struct platform_device *__init
1736 at32_add_device_usba(unsigned int id, struct usba_platform_data *data)
1737 {
1738         /*
1739          * pdata doesn't have room for any endpoints, so we need to
1740          * append room for the ones we need right after it.
1741          */
1742         struct {
1743                 struct usba_platform_data pdata;
1744                 struct usba_ep_data ep[7];
1745         } usba_data;
1746         struct platform_device *pdev;
1747
1748         if (id != 0)
1749                 return NULL;
1750
1751         pdev = platform_device_alloc("atmel_usba_udc", 0);
1752         if (!pdev)
1753                 return NULL;
1754
1755         if (platform_device_add_resources(pdev, usba0_resource,
1756                                           ARRAY_SIZE(usba0_resource)))
1757                 goto out_free_pdev;
1758
1759         if (data)
1760                 usba_data.pdata.vbus_pin = data->vbus_pin;
1761         else
1762                 usba_data.pdata.vbus_pin = -EINVAL;
1763
1764         data = &usba_data.pdata;
1765         data->num_ep = ARRAY_SIZE(at32_usba_ep);
1766         memcpy(data->ep, at32_usba_ep, sizeof(at32_usba_ep));
1767
1768         if (platform_device_add_data(pdev, data, sizeof(usba_data)))
1769                 goto out_free_pdev;
1770
1771         if (gpio_is_valid(data->vbus_pin))
1772                 at32_select_gpio(data->vbus_pin, 0);
1773
1774         usba0_pclk.dev = &pdev->dev;
1775         usba0_hclk.dev = &pdev->dev;
1776
1777         platform_device_add(pdev);
1778
1779         return pdev;
1780
1781 out_free_pdev:
1782         platform_device_put(pdev);
1783         return NULL;
1784 }
1785
1786 /* --------------------------------------------------------------------
1787  * IDE / CompactFlash
1788  * -------------------------------------------------------------------- */
1789 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7001)
1790 static struct resource at32_smc_cs4_resource[] __initdata = {
1791         {
1792                 .start  = 0x04000000,
1793                 .end    = 0x07ffffff,
1794                 .flags  = IORESOURCE_MEM,
1795         },
1796         IRQ(~0UL), /* Magic IRQ will be overridden */
1797 };
1798 static struct resource at32_smc_cs5_resource[] __initdata = {
1799         {
1800                 .start  = 0x20000000,
1801                 .end    = 0x23ffffff,
1802                 .flags  = IORESOURCE_MEM,
1803         },
1804         IRQ(~0UL), /* Magic IRQ will be overridden */
1805 };
1806
1807 static int __init at32_init_ide_or_cf(struct platform_device *pdev,
1808                 unsigned int cs, unsigned int extint)
1809 {
1810         static unsigned int extint_pin_map[4] __initdata = {
1811                 (1 << 25),
1812                 (1 << 26),
1813                 (1 << 27),
1814                 (1 << 28),
1815         };
1816         static bool common_pins_initialized __initdata = false;
1817         unsigned int extint_pin;
1818         int ret;
1819         u32 pin_mask;
1820
1821         if (extint >= ARRAY_SIZE(extint_pin_map))
1822                 return -EINVAL;
1823         extint_pin = extint_pin_map[extint];
1824
1825         switch (cs) {
1826         case 4:
1827                 ret = platform_device_add_resources(pdev,
1828                                 at32_smc_cs4_resource,
1829                                 ARRAY_SIZE(at32_smc_cs4_resource));
1830                 if (ret)
1831                         return ret;
1832
1833                 /* NCS4   -> OE_N  */
1834                 select_peripheral(PIOE, (1 << 21), PERIPH_A, 0);
1835                 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_CF0_ENABLE);
1836                 break;
1837         case 5:
1838                 ret = platform_device_add_resources(pdev,
1839                                 at32_smc_cs5_resource,
1840                                 ARRAY_SIZE(at32_smc_cs5_resource));
1841                 if (ret)
1842                         return ret;
1843
1844                 /* NCS5   -> OE_N  */
1845                 select_peripheral(PIOE, (1 << 22), PERIPH_A, 0);
1846                 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_CF1_ENABLE);
1847                 break;
1848         default:
1849                 return -EINVAL;
1850         }
1851
1852         if (!common_pins_initialized) {
1853                 pin_mask  = (1 << 19);  /* CFCE1  -> CS0_N */
1854                 pin_mask |= (1 << 20);  /* CFCE2  -> CS1_N */
1855                 pin_mask |= (1 << 23);  /* CFRNW  -> DIR   */
1856                 pin_mask |= (1 << 24);  /* NWAIT  <- IORDY */
1857
1858                 select_peripheral(PIOE, pin_mask, PERIPH_A, 0);
1859
1860                 common_pins_initialized = true;
1861         }
1862
1863         select_peripheral(PIOB, extint_pin, PERIPH_A, AT32_GPIOF_DEGLITCH);
1864
1865         pdev->resource[1].start = EIM_IRQ_BASE + extint;
1866         pdev->resource[1].end = pdev->resource[1].start;
1867
1868         return 0;
1869 }
1870
1871 struct platform_device *__init
1872 at32_add_device_ide(unsigned int id, unsigned int extint,
1873                     struct ide_platform_data *data)
1874 {
1875         struct platform_device *pdev;
1876
1877         pdev = platform_device_alloc("at32_ide", id);
1878         if (!pdev)
1879                 goto fail;
1880
1881         if (platform_device_add_data(pdev, data,
1882                                 sizeof(struct ide_platform_data)))
1883                 goto fail;
1884
1885         if (at32_init_ide_or_cf(pdev, data->cs, extint))
1886                 goto fail;
1887
1888         platform_device_add(pdev);
1889         return pdev;
1890
1891 fail:
1892         platform_device_put(pdev);
1893         return NULL;
1894 }
1895
1896 struct platform_device *__init
1897 at32_add_device_cf(unsigned int id, unsigned int extint,
1898                     struct cf_platform_data *data)
1899 {
1900         struct platform_device *pdev;
1901
1902         pdev = platform_device_alloc("at32_cf", id);
1903         if (!pdev)
1904                 goto fail;
1905
1906         if (platform_device_add_data(pdev, data,
1907                                 sizeof(struct cf_platform_data)))
1908                 goto fail;
1909
1910         if (at32_init_ide_or_cf(pdev, data->cs, extint))
1911                 goto fail;
1912
1913         if (gpio_is_valid(data->detect_pin))
1914                 at32_select_gpio(data->detect_pin, AT32_GPIOF_DEGLITCH);
1915         if (gpio_is_valid(data->reset_pin))
1916                 at32_select_gpio(data->reset_pin, 0);
1917         if (gpio_is_valid(data->vcc_pin))
1918                 at32_select_gpio(data->vcc_pin, 0);
1919         /* READY is used as extint, so we can't select it as gpio */
1920
1921         platform_device_add(pdev);
1922         return pdev;
1923
1924 fail:
1925         platform_device_put(pdev);
1926         return NULL;
1927 }
1928 #endif
1929
1930 /* --------------------------------------------------------------------
1931  * NAND Flash / SmartMedia
1932  * -------------------------------------------------------------------- */
1933 static struct resource smc_cs3_resource[] __initdata = {
1934         {
1935                 .start  = 0x0c000000,
1936                 .end    = 0x0fffffff,
1937                 .flags  = IORESOURCE_MEM,
1938         }, {
1939                 .start  = 0xfff03c00,
1940                 .end    = 0xfff03fff,
1941                 .flags  = IORESOURCE_MEM,
1942         },
1943 };
1944
1945 struct platform_device *__init
1946 at32_add_device_nand(unsigned int id, struct atmel_nand_data *data)
1947 {
1948         struct platform_device *pdev;
1949
1950         if (id != 0 || !data)
1951                 return NULL;
1952
1953         pdev = platform_device_alloc("atmel_nand", id);
1954         if (!pdev)
1955                 goto fail;
1956
1957         if (platform_device_add_resources(pdev, smc_cs3_resource,
1958                                 ARRAY_SIZE(smc_cs3_resource)))
1959                 goto fail;
1960
1961         if (platform_device_add_data(pdev, data,
1962                                 sizeof(struct atmel_nand_data)))
1963                 goto fail;
1964
1965         hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_NAND_ENABLE);
1966         if (data->enable_pin)
1967                 at32_select_gpio(data->enable_pin,
1968                                 AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
1969         if (data->rdy_pin)
1970                 at32_select_gpio(data->rdy_pin, 0);
1971         if (data->det_pin)
1972                 at32_select_gpio(data->det_pin, 0);
1973
1974         platform_device_add(pdev);
1975         return pdev;
1976
1977 fail:
1978         platform_device_put(pdev);
1979         return NULL;
1980 }
1981
1982 /* --------------------------------------------------------------------
1983  * AC97C
1984  * -------------------------------------------------------------------- */
1985 static struct resource atmel_ac97c0_resource[] __initdata = {
1986         PBMEM(0xfff02800),
1987         IRQ(29),
1988 };
1989 static struct clk atmel_ac97c0_pclk = {
1990         .name           = "pclk",
1991         .parent         = &pbb_clk,
1992         .mode           = pbb_clk_mode,
1993         .get_rate       = pbb_clk_get_rate,
1994         .index          = 10,
1995 };
1996
1997 struct platform_device *__init
1998 at32_add_device_ac97c(unsigned int id, struct ac97c_platform_data *data,
1999                       unsigned int flags)
2000 {
2001         struct platform_device          *pdev;
2002         struct dw_dma_slave             *rx_dws;
2003         struct dw_dma_slave             *tx_dws;
2004         struct ac97c_platform_data      _data;
2005         u32                             pin_mask;
2006
2007         if (id != 0)
2008                 return NULL;
2009
2010         pdev = platform_device_alloc("atmel_ac97c", id);
2011         if (!pdev)
2012                 return NULL;
2013
2014         if (platform_device_add_resources(pdev, atmel_ac97c0_resource,
2015                                 ARRAY_SIZE(atmel_ac97c0_resource)))
2016                 goto out_free_resources;
2017
2018         if (!data) {
2019                 data = &_data;
2020                 memset(data, 0, sizeof(struct ac97c_platform_data));
2021                 data->reset_pin = -ENODEV;
2022         }
2023
2024         rx_dws = &data->rx_dws;
2025         tx_dws = &data->tx_dws;
2026
2027         /* Check if DMA slave interface for capture should be configured. */
2028         if (flags & AC97C_CAPTURE) {
2029                 rx_dws->dma_dev = &dw_dmac0_device.dev;
2030                 rx_dws->reg_width = DW_DMA_SLAVE_WIDTH_16BIT;
2031                 rx_dws->cfg_hi = DWC_CFGH_SRC_PER(3);
2032                 rx_dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL);
2033         }
2034
2035         /* Check if DMA slave interface for playback should be configured. */
2036         if (flags & AC97C_PLAYBACK) {
2037                 tx_dws->dma_dev = &dw_dmac0_device.dev;
2038                 tx_dws->reg_width = DW_DMA_SLAVE_WIDTH_16BIT;
2039                 tx_dws->cfg_hi = DWC_CFGH_DST_PER(4);
2040                 tx_dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL);
2041         }
2042
2043         if (platform_device_add_data(pdev, data,
2044                                 sizeof(struct ac97c_platform_data)))
2045                 goto out_free_resources;
2046
2047         /* SDO | SYNC | SCLK | SDI */
2048         pin_mask = (1 << 20) | (1 << 21) | (1 << 22) | (1 << 23);
2049
2050         select_peripheral(PIOB, pin_mask, PERIPH_B, 0);
2051
2052         if (gpio_is_valid(data->reset_pin))
2053                 at32_select_gpio(data->reset_pin, AT32_GPIOF_OUTPUT
2054                                 | AT32_GPIOF_HIGH);
2055
2056         atmel_ac97c0_pclk.dev = &pdev->dev;
2057
2058         platform_device_add(pdev);
2059         return pdev;
2060
2061 out_free_resources:
2062         platform_device_put(pdev);
2063         return NULL;
2064 }
2065
2066 /* --------------------------------------------------------------------
2067  * ABDAC
2068  * -------------------------------------------------------------------- */
2069 static struct resource abdac0_resource[] __initdata = {
2070         PBMEM(0xfff02000),
2071         IRQ(27),
2072 };
2073 static struct clk abdac0_pclk = {
2074         .name           = "pclk",
2075         .parent         = &pbb_clk,
2076         .mode           = pbb_clk_mode,
2077         .get_rate       = pbb_clk_get_rate,
2078         .index          = 8,
2079 };
2080 static struct clk abdac0_sample_clk = {
2081         .name           = "sample_clk",
2082         .mode           = genclk_mode,
2083         .get_rate       = genclk_get_rate,
2084         .set_rate       = genclk_set_rate,
2085         .set_parent     = genclk_set_parent,
2086         .index          = 6,
2087 };
2088
2089 struct platform_device *__init
2090 at32_add_device_abdac(unsigned int id, struct atmel_abdac_pdata *data)
2091 {
2092         struct platform_device  *pdev;
2093         struct dw_dma_slave     *dws;
2094         u32                     pin_mask;
2095
2096         if (id != 0 || !data)
2097                 return NULL;
2098
2099         pdev = platform_device_alloc("atmel_abdac", id);
2100         if (!pdev)
2101                 return NULL;
2102
2103         if (platform_device_add_resources(pdev, abdac0_resource,
2104                                 ARRAY_SIZE(abdac0_resource)))
2105                 goto out_free_resources;
2106
2107         dws = &data->dws;
2108
2109         dws->dma_dev = &dw_dmac0_device.dev;
2110         dws->reg_width = DW_DMA_SLAVE_WIDTH_32BIT;
2111         dws->cfg_hi = DWC_CFGH_DST_PER(2);
2112         dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL);
2113
2114         if (platform_device_add_data(pdev, data,
2115                                 sizeof(struct atmel_abdac_pdata)))
2116                 goto out_free_resources;
2117
2118         pin_mask  = (1 << 20) | (1 << 22);      /* DATA1 & DATAN1 */
2119         pin_mask |= (1 << 21) | (1 << 23);      /* DATA0 & DATAN0 */
2120
2121         select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
2122
2123         abdac0_pclk.dev = &pdev->dev;
2124         abdac0_sample_clk.dev = &pdev->dev;
2125
2126         platform_device_add(pdev);
2127         return pdev;
2128
2129 out_free_resources:
2130         platform_device_put(pdev);
2131         return NULL;
2132 }
2133
2134 /* --------------------------------------------------------------------
2135  *  GCLK
2136  * -------------------------------------------------------------------- */
2137 static struct clk gclk0 = {
2138         .name           = "gclk0",
2139         .mode           = genclk_mode,
2140         .get_rate       = genclk_get_rate,
2141         .set_rate       = genclk_set_rate,
2142         .set_parent     = genclk_set_parent,
2143         .index          = 0,
2144 };
2145 static struct clk gclk1 = {
2146         .name           = "gclk1",
2147         .mode           = genclk_mode,
2148         .get_rate       = genclk_get_rate,
2149         .set_rate       = genclk_set_rate,
2150         .set_parent     = genclk_set_parent,
2151         .index          = 1,
2152 };
2153 static struct clk gclk2 = {
2154         .name           = "gclk2",
2155         .mode           = genclk_mode,
2156         .get_rate       = genclk_get_rate,
2157         .set_rate       = genclk_set_rate,
2158         .set_parent     = genclk_set_parent,
2159         .index          = 2,
2160 };
2161 static struct clk gclk3 = {
2162         .name           = "gclk3",
2163         .mode           = genclk_mode,
2164         .get_rate       = genclk_get_rate,
2165         .set_rate       = genclk_set_rate,
2166         .set_parent     = genclk_set_parent,
2167         .index          = 3,
2168 };
2169 static struct clk gclk4 = {
2170         .name           = "gclk4",
2171         .mode           = genclk_mode,
2172         .get_rate       = genclk_get_rate,
2173         .set_rate       = genclk_set_rate,
2174         .set_parent     = genclk_set_parent,
2175         .index          = 4,
2176 };
2177
2178 static __initdata struct clk *init_clocks[] = {
2179         &osc32k,
2180         &osc0,
2181         &osc1,
2182         &pll0,
2183         &pll1,
2184         &cpu_clk,
2185         &hsb_clk,
2186         &pba_clk,
2187         &pbb_clk,
2188         &at32_pm_pclk,
2189         &at32_intc0_pclk,
2190         &at32_hmatrix_clk,
2191         &ebi_clk,
2192         &hramc_clk,
2193         &sdramc_clk,
2194         &smc0_pclk,
2195         &smc0_mck,
2196         &pdc_hclk,
2197         &pdc_pclk,
2198         &dw_dmac0_hclk,
2199         &pico_clk,
2200         &pio0_mck,
2201         &pio1_mck,
2202         &pio2_mck,
2203         &pio3_mck,
2204         &pio4_mck,
2205         &at32_tcb0_t0_clk,
2206         &at32_tcb1_t0_clk,
2207         &atmel_psif0_pclk,
2208         &atmel_psif1_pclk,
2209         &atmel_usart0_usart,
2210         &atmel_usart1_usart,
2211         &atmel_usart2_usart,
2212         &atmel_usart3_usart,
2213         &atmel_pwm0_mck,
2214 #if defined(CONFIG_CPU_AT32AP7000)
2215         &macb0_hclk,
2216         &macb0_pclk,
2217         &macb1_hclk,
2218         &macb1_pclk,
2219 #endif
2220         &atmel_spi0_spi_clk,
2221         &atmel_spi1_spi_clk,
2222         &atmel_twi0_pclk,
2223         &atmel_mci0_pclk,
2224 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
2225         &atmel_lcdfb0_hck1,
2226         &atmel_lcdfb0_pixclk,
2227 #endif
2228         &ssc0_pclk,
2229         &ssc1_pclk,
2230         &ssc2_pclk,
2231         &usba0_hclk,
2232         &usba0_pclk,
2233         &atmel_ac97c0_pclk,
2234         &abdac0_pclk,
2235         &abdac0_sample_clk,
2236         &gclk0,
2237         &gclk1,
2238         &gclk2,
2239         &gclk3,
2240         &gclk4,
2241 };
2242
2243 void __init setup_platform(void)
2244 {
2245         u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
2246         int i;
2247
2248         if (pm_readl(MCCTRL) & PM_BIT(PLLSEL)) {
2249                 main_clock = &pll0;
2250                 cpu_clk.parent = &pll0;
2251         } else {
2252                 main_clock = &osc0;
2253                 cpu_clk.parent = &osc0;
2254         }
2255
2256         if (pm_readl(PLL0) & PM_BIT(PLLOSC))
2257                 pll0.parent = &osc1;
2258         if (pm_readl(PLL1) & PM_BIT(PLLOSC))
2259                 pll1.parent = &osc1;
2260
2261         genclk_init_parent(&gclk0);
2262         genclk_init_parent(&gclk1);
2263         genclk_init_parent(&gclk2);
2264         genclk_init_parent(&gclk3);
2265         genclk_init_parent(&gclk4);
2266 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
2267         genclk_init_parent(&atmel_lcdfb0_pixclk);
2268 #endif
2269         genclk_init_parent(&abdac0_sample_clk);
2270
2271         /*
2272          * Build initial dynamic clock list by registering all clocks
2273          * from the array.
2274          * At the same time, turn on all clocks that have at least one
2275          * user already, and turn off everything else. We only do this
2276          * for module clocks, and even though it isn't particularly
2277          * pretty to  check the address of the mode function, it should
2278          * do the trick...
2279          */
2280         for (i = 0; i < ARRAY_SIZE(init_clocks); i++) {
2281                 struct clk *clk = init_clocks[i];
2282
2283                 /* first, register clock */
2284                 at32_clk_register(clk);
2285
2286                 if (clk->users == 0)
2287                         continue;
2288
2289                 if (clk->mode == &cpu_clk_mode)
2290                         cpu_mask |= 1 << clk->index;
2291                 else if (clk->mode == &hsb_clk_mode)
2292                         hsb_mask |= 1 << clk->index;
2293                 else if (clk->mode == &pba_clk_mode)
2294                         pba_mask |= 1 << clk->index;
2295                 else if (clk->mode == &pbb_clk_mode)
2296                         pbb_mask |= 1 << clk->index;
2297         }
2298
2299         pm_writel(CPU_MASK, cpu_mask);
2300         pm_writel(HSB_MASK, hsb_mask);
2301         pm_writel(PBA_MASK, pba_mask);
2302         pm_writel(PBB_MASK, pbb_mask);
2303
2304         /* Initialize the port muxes */
2305         at32_init_pio(&pio0_device);
2306         at32_init_pio(&pio1_device);
2307         at32_init_pio(&pio2_device);
2308         at32_init_pio(&pio3_device);
2309         at32_init_pio(&pio4_device);
2310 }
2311
2312 struct gen_pool *sram_pool;
2313
2314 static int __init sram_init(void)
2315 {
2316         struct gen_pool *pool;
2317
2318         /* 1KiB granularity */
2319         pool = gen_pool_create(10, -1);
2320         if (!pool)
2321                 goto fail;
2322
2323         if (gen_pool_add(pool, 0x24000000, 0x8000, -1))
2324                 goto err_pool_add;
2325
2326         sram_pool = pool;
2327         return 0;
2328
2329 err_pool_add:
2330         gen_pool_destroy(pool);
2331 fail:
2332         pr_err("Failed to create SRAM pool\n");
2333         return -ENOMEM;
2334 }
2335 core_initcall(sram_init);