arch/avr32/mach-at32ap/at32ap700x.c

   1 /*
   2  * Copyright (C) 2005-2006 Atmel Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8 #include <linux/clk.h>
   9 #include <linux/delay.h>
  10 #include <linux/dw_dmac.h>
  11 #include <linux/fb.h>
  12 #include <linux/init.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/dma-mapping.h>
  15 #include <linux/gpio.h>
  16 #include <linux/spi/spi.h>
  17 #include <linux/usb/atmel_usba_udc.h>
  18
  19 #include <mach/atmel-mci.h>
  20 #include <linux/atmel-mci.h>
  21
  22 #include <asm/io.h>
  23 #include <asm/irq.h>
  24
  25 #include <mach/at32ap700x.h>
  26 #include <mach/board.h>
  27 #include <mach/hmatrix.h>
  28 #include <mach/portmux.h>
  29 #include <mach/sram.h>
  30
  31 #include <sound/atmel-abdac.h>
  32 #include <sound/atmel-ac97c.h>
  33
  34 #include <video/atmel_lcdc.h>
  35
  36 #include "clock.h"
  37 #include "pio.h"
  38 #include "pm.h"
  39
  40
  41 #define PBMEM(base)                                     \
  42         {                                               \
  43                 .start          = base,                 \
  44                 .end            = base + 0x3ff,         \
  45                 .flags          = IORESOURCE_MEM,       \
  46         }
  47 #define IRQ(num)                                        \
  48         {                                               \
  49                 .start          = num,                  \
  50                 .end            = num,                  \
  51                 .flags          = IORESOURCE_IRQ,       \
  52         }
  53 #define NAMED_IRQ(num, _name)                           \
  54         {                                               \
  55                 .start          = num,                  \
  56                 .end            = num,                  \
  57                 .name           = _name,                \
  58                 .flags          = IORESOURCE_IRQ,       \
  59         }
  60
  61 /* REVISIT these assume *every* device supports DMA, but several
  62  * don't ... tc, smc, pio, rtc, watchdog, pwm, ps2, and more.
  63  */
  64 #define DEFINE_DEV(_name, _id)                                  \
  65 static u64 _name##_id##_dma_mask = DMA_BIT_MASK(32);            \
  66 static struct platform_device _name##_id##_device = {           \
  67         .name           = #_name,                               \
  68         .id             = _id,                                  \
  69         .dev            = {                                     \
  70                 .dma_mask = &_name##_id##_dma_mask,             \
  71                 .coherent_dma_mask = DMA_BIT_MASK(32),          \
  72         },                                                      \
  73         .resource       = _name##_id##_resource,                \
  74         .num_resources  = ARRAY_SIZE(_name##_id##_resource),    \
  75 }
  76 #define DEFINE_DEV_DATA(_name, _id)                             \
  77 static u64 _name##_id##_dma_mask = DMA_BIT_MASK(32);            \
  78 static struct platform_device _name##_id##_device = {           \
  79         .name           = #_name,                               \
  80         .id             = _id,                                  \
  81         .dev            = {                                     \
  82                 .dma_mask = &_name##_id##_dma_mask,             \
  83                 .platform_data  = &_name##_id##_data,           \
  84                 .coherent_dma_mask = DMA_BIT_MASK(32),          \
  85         },                                                      \
  86         .resource       = _name##_id##_resource,                \
  87         .num_resources  = ARRAY_SIZE(_name##_id##_resource),    \
  88 }
  89
  90 #define select_peripheral(port, pin_mask, periph, flags)        \
  91         at32_select_periph(GPIO_##port##_BASE, pin_mask,        \
  92                            GPIO_##periph, flags)
  93
  94 #define DEV_CLK(_name, devname, bus, _index)                    \
  95 static struct clk devname##_##_name = {                         \
  96         .name           = #_name,                               \
  97         .dev            = &devname##_device.dev,                \
  98         .parent         = &bus##_clk,                           \
  99         .mode           = bus##_clk_mode,                       \
 100         .get_rate       = bus##_clk_get_rate,                   \
 101         .index          = _index,                               \
 102 }
 103
 104 static DEFINE_SPINLOCK(pm_lock);
 105
 106 static struct clk osc0;
 107 static struct clk osc1;
 108
 109 static unsigned long osc_get_rate(struct clk *clk)
 110 {
 111         return at32_board_osc_rates[clk->index];
 112 }
 113
 114 static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
 115 {
 116         unsigned long div, mul, rate;
 117
 118         div = PM_BFEXT(PLLDIV, control) + 1;
 119         mul = PM_BFEXT(PLLMUL, control) + 1;
 120
 121         rate = clk->parent->get_rate(clk->parent);
 122         rate = (rate + div / 2) / div;
 123         rate *= mul;
 124
 125         return rate;
 126 }
 127
 128 static long pll_set_rate(struct clk *clk, unsigned long rate,
 129                          u32 *pll_ctrl)
 130 {
 131         unsigned long mul;
 132         unsigned long mul_best_fit = 0;
 133         unsigned long div;
 134         unsigned long div_min;
 135         unsigned long div_max;
 136         unsigned long div_best_fit = 0;
 137         unsigned long base;
 138         unsigned long pll_in;
 139         unsigned long actual = 0;
 140         unsigned long rate_error;
 141         unsigned long rate_error_prev = ~0UL;
 142         u32 ctrl;
 143
 144         /* Rate must be between 80 MHz and 200 Mhz. */
 145         if (rate < 80000000UL || rate > 200000000UL)
 146                 return -EINVAL;
 147
 148         ctrl = PM_BF(PLLOPT, 4);
 149         base = clk->parent->get_rate(clk->parent);
 150
 151         /* PLL input frequency must be between 6 MHz and 32 MHz. */
 152         div_min = DIV_ROUND_UP(base, 32000000UL);
 153         div_max = base / 6000000UL;
 154
 155         if (div_max < div_min)
 156                 return -EINVAL;
 157
 158         for (div = div_min; div <= div_max; div++) {
 159                 pll_in = (base + div / 2) / div;
 160                 mul = (rate + pll_in / 2) / pll_in;
 161
 162                 if (mul == 0)
 163                         continue;
 164
 165                 actual = pll_in * mul;
 166                 rate_error = abs(actual - rate);
 167
 168                 if (rate_error < rate_error_prev) {
 169                         mul_best_fit = mul;
 170                         div_best_fit = div;
 171                         rate_error_prev = rate_error;
 172                 }
 173
 174                 if (rate_error == 0)
 175                         break;
 176         }
 177
 178         if (div_best_fit == 0)
 179                 return -EINVAL;
 180
 181         ctrl |= PM_BF(PLLMUL, mul_best_fit - 1);
 182         ctrl |= PM_BF(PLLDIV, div_best_fit - 1);
 183         ctrl |= PM_BF(PLLCOUNT, 16);
 184
 185         if (clk->parent == &osc1)
 186                 ctrl |= PM_BIT(PLLOSC);
 187
 188         *pll_ctrl = ctrl;
 189
 190         return actual;
 191 }
 192
 193 static unsigned long pll0_get_rate(struct clk *clk)
 194 {
 195         u32 control;
 196
 197         control = pm_readl(PLL0);
 198
 199         return pll_get_rate(clk, control);
 200 }
 201
 202 static void pll1_mode(struct clk *clk, int enabled)
 203 {
 204         unsigned long timeout;
 205         u32 status;
 206         u32 ctrl;
 207
 208         ctrl = pm_readl(PLL1);
 209
 210         if (enabled) {
 211                 if (!PM_BFEXT(PLLMUL, ctrl) && !PM_BFEXT(PLLDIV, ctrl)) {
 212                         pr_debug("clk %s: failed to enable, rate not set\n",
 213                                         clk->name);
 214                         return;
 215                 }
 216
 217                 ctrl |= PM_BIT(PLLEN);
 218                 pm_writel(PLL1, ctrl);
 219
 220                 /* Wait for PLL lock. */
 221                 for (timeout = 10000; timeout; timeout--) {
 222                         status = pm_readl(ISR);
 223                         if (status & PM_BIT(LOCK1))
 224                                 break;
 225                         udelay(10);
 226                 }
 227
 228                 if (!(status & PM_BIT(LOCK1)))
 229                         printk(KERN_ERR "clk %s: timeout waiting for lock\n",
 230                                         clk->name);
 231         } else {
 232                 ctrl &= ~PM_BIT(PLLEN);
 233                 pm_writel(PLL1, ctrl);
 234         }
 235 }
 236
 237 static unsigned long pll1_get_rate(struct clk *clk)
 238 {
 239         u32 control;
 240
 241         control = pm_readl(PLL1);
 242
 243         return pll_get_rate(clk, control);
 244 }
 245
 246 static long pll1_set_rate(struct clk *clk, unsigned long rate, int apply)
 247 {
 248         u32 ctrl = 0;
 249         unsigned long actual_rate;
 250
 251         actual_rate = pll_set_rate(clk, rate, &ctrl);
 252
 253         if (apply) {
 254                 if (actual_rate != rate)
 255                         return -EINVAL;
 256                 if (clk->users > 0)
 257                         return -EBUSY;
 258                 pr_debug(KERN_INFO "clk %s: new rate %lu (actual rate %lu)\n",
 259                                 clk->name, rate, actual_rate);
 260                 pm_writel(PLL1, ctrl);
 261         }
 262
 263         return actual_rate;
 264 }
 265
 266 static int pll1_set_parent(struct clk *clk, struct clk *parent)
 267 {
 268         u32 ctrl;
 269
 270         if (clk->users > 0)
 271                 return -EBUSY;
 272
 273         ctrl = pm_readl(PLL1);
 274         WARN_ON(ctrl & PM_BIT(PLLEN));
 275
 276         if (parent == &osc0)
 277                 ctrl &= ~PM_BIT(PLLOSC);
 278         else if (parent == &osc1)
 279                 ctrl |= PM_BIT(PLLOSC);
 280         else
 281                 return -EINVAL;
 282
 283         pm_writel(PLL1, ctrl);
 284         clk->parent = parent;
 285
 286         return 0;
 287 }
 288
 289 /*
 290  * The AT32AP7000 has five primary clock sources: One 32kHz
 291  * oscillator, two crystal oscillators and two PLLs.
 292  */
 293 static struct clk osc32k = {
 294         .name           = "osc32k",
 295         .get_rate       = osc_get_rate,
 296         .users          = 1,
 297         .index          = 0,
 298 };
 299 static struct clk osc0 = {
 300         .name           = "osc0",
 301         .get_rate       = osc_get_rate,
 302         .users          = 1,
 303         .index          = 1,
 304 };
 305 static struct clk osc1 = {
 306         .name           = "osc1",
 307         .get_rate       = osc_get_rate,
 308         .index          = 2,
 309 };
 310 static struct clk pll0 = {
 311         .name           = "pll0",
 312         .get_rate       = pll0_get_rate,
 313         .parent         = &osc0,
 314 };
 315 static struct clk pll1 = {
 316         .name           = "pll1",
 317         .mode           = pll1_mode,
 318         .get_rate       = pll1_get_rate,
 319         .set_rate       = pll1_set_rate,
 320         .set_parent     = pll1_set_parent,
 321         .parent         = &osc0,
 322 };
 323
 324 /*
 325  * The main clock can be either osc0 or pll0.  The boot loader may
 326  * have chosen one for us, so we don't really know which one until we
 327  * have a look at the SM.
 328  */
 329 static struct clk *main_clock;
 330
 331 /*
 332  * Synchronous clocks are generated from the main clock. The clocks
 333  * must satisfy the constraint
 334  *   fCPU >= fHSB >= fPB
 335  * i.e. each clock must not be faster than its parent.
 336  */
 337 static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift)
 338 {
 339         return main_clock->get_rate(main_clock) >> shift;
 340 };
 341
 342 static void cpu_clk_mode(struct clk *clk, int enabled)
 343 {
 344         unsigned long flags;
 345         u32 mask;
 346
 347         spin_lock_irqsave(&pm_lock, flags);
 348         mask = pm_readl(CPU_MASK);
 349         if (enabled)
 350                 mask |= 1 << clk->index;
 351         else
 352                 mask &= ~(1 << clk->index);
 353         pm_writel(CPU_MASK, mask);
 354         spin_unlock_irqrestore(&pm_lock, flags);
 355 }
 356
 357 static unsigned long cpu_clk_get_rate(struct clk *clk)
 358 {
 359         unsigned long cksel, shift = 0;
 360
 361         cksel = pm_readl(CKSEL);
 362         if (cksel & PM_BIT(CPUDIV))
 363                 shift = PM_BFEXT(CPUSEL, cksel) + 1;
 364
 365         return bus_clk_get_rate(clk, shift);
 366 }
 367
 368 static long cpu_clk_set_rate(struct clk *clk, unsigned long rate, int apply)
 369 {
 370         u32 control;
 371         unsigned long parent_rate, child_div, actual_rate, div;
 372
 373         parent_rate = clk->parent->get_rate(clk->parent);
 374         control = pm_readl(CKSEL);
 375
 376         if (control & PM_BIT(HSBDIV))
 377                 child_div = 1 << (PM_BFEXT(HSBSEL, control) + 1);
 378         else
 379                 child_div = 1;
 380
 381         if (rate > 3 * (parent_rate / 4) || child_div == 1) {
 382                 actual_rate = parent_rate;
 383                 control &= ~PM_BIT(CPUDIV);
 384         } else {
 385                 unsigned int cpusel;
 386                 div = (parent_rate + rate / 2) / rate;
 387                 if (div > child_div)
 388                         div = child_div;
 389                 cpusel = (div > 1) ? (fls(div) - 2) : 0;
 390                 control = PM_BIT(CPUDIV) | PM_BFINS(CPUSEL, cpusel, control);
 391                 actual_rate = parent_rate / (1 << (cpusel + 1));
 392         }
 393
 394         pr_debug("clk %s: new rate %lu (actual rate %lu)\n",
 395                         clk->name, rate, actual_rate);
 396
 397         if (apply)
 398                 pm_writel(CKSEL, control);
 399
 400         return actual_rate;
 401 }
 402
 403 static void hsb_clk_mode(struct clk *clk, int enabled)
 404 {
 405         unsigned long flags;
 406         u32 mask;
 407
 408         spin_lock_irqsave(&pm_lock, flags);
 409         mask = pm_readl(HSB_MASK);
 410         if (enabled)
 411                 mask |= 1 << clk->index;
 412         else
 413                 mask &= ~(1 << clk->index);
 414         pm_writel(HSB_MASK, mask);
 415         spin_unlock_irqrestore(&pm_lock, flags);
 416 }
 417
 418 static unsigned long hsb_clk_get_rate(struct clk *clk)
 419 {
 420         unsigned long cksel, shift = 0;
 421
 422         cksel = pm_readl(CKSEL);
 423         if (cksel & PM_BIT(HSBDIV))
 424                 shift = PM_BFEXT(HSBSEL, cksel) + 1;
 425
 426         return bus_clk_get_rate(clk, shift);
 427 }
 428
 429 void pba_clk_mode(struct clk *clk, int enabled)
 430 {
 431         unsigned long flags;
 432         u32 mask;
 433
 434         spin_lock_irqsave(&pm_lock, flags);
 435         mask = pm_readl(PBA_MASK);
 436         if (enabled)
 437                 mask |= 1 << clk->index;
 438         else
 439                 mask &= ~(1 << clk->index);
 440         pm_writel(PBA_MASK, mask);
 441         spin_unlock_irqrestore(&pm_lock, flags);
 442 }
 443
 444 unsigned long pba_clk_get_rate(struct clk *clk)
 445 {
 446         unsigned long cksel, shift = 0;
 447
 448         cksel = pm_readl(CKSEL);
 449         if (cksel & PM_BIT(PBADIV))
 450                 shift = PM_BFEXT(PBASEL, cksel) + 1;
 451
 452         return bus_clk_get_rate(clk, shift);
 453 }
 454
 455 static void pbb_clk_mode(struct clk *clk, int enabled)
 456 {
 457         unsigned long flags;
 458         u32 mask;
 459
 460         spin_lock_irqsave(&pm_lock, flags);
 461         mask = pm_readl(PBB_MASK);
 462         if (enabled)
 463                 mask |= 1 << clk->index;
 464         else
 465                 mask &= ~(1 << clk->index);
 466         pm_writel(PBB_MASK, mask);
 467         spin_unlock_irqrestore(&pm_lock, flags);
 468 }
 469
 470 static unsigned long pbb_clk_get_rate(struct clk *clk)
 471 {
 472         unsigned long cksel, shift = 0;
 473
 474         cksel = pm_readl(CKSEL);
 475         if (cksel & PM_BIT(PBBDIV))
 476                 shift = PM_BFEXT(PBBSEL, cksel) + 1;
 477
 478         return bus_clk_get_rate(clk, shift);
 479 }
 480
 481 static struct clk cpu_clk = {
 482         .name           = "cpu",
 483         .get_rate       = cpu_clk_get_rate,
 484         .set_rate       = cpu_clk_set_rate,
 485         .users          = 1,
 486 };
 487 static struct clk hsb_clk = {
 488         .name           = "hsb",
 489         .parent         = &cpu_clk,
 490         .get_rate       = hsb_clk_get_rate,
 491 };
 492 static struct clk pba_clk = {
 493         .name           = "pba",
 494         .parent         = &hsb_clk,
 495         .mode           = hsb_clk_mode,
 496         .get_rate       = pba_clk_get_rate,
 497         .index          = 1,
 498 };
 499 static struct clk pbb_clk = {
 500         .name           = "pbb",
 501         .parent         = &hsb_clk,
 502         .mode           = hsb_clk_mode,
 503         .get_rate       = pbb_clk_get_rate,
 504         .users          = 1,
 505         .index          = 2,
 506 };
 507
 508 /* --------------------------------------------------------------------
 509  *  Generic Clock operations
 510  * -------------------------------------------------------------------- */
 511
 512 static void genclk_mode(struct clk *clk, int enabled)
 513 {
 514         u32 control;
 515
 516         control = pm_readl(GCCTRL(clk->index));
 517         if (enabled)
 518                 control |= PM_BIT(CEN);
 519         else
 520                 control &= ~PM_BIT(CEN);
 521         pm_writel(GCCTRL(clk->index), control);
 522 }
 523
 524 static unsigned long genclk_get_rate(struct clk *clk)
 525 {
 526         u32 control;
 527         unsigned long div = 1;
 528
 529         control = pm_readl(GCCTRL(clk->index));
 530         if (control & PM_BIT(DIVEN))
 531                 div = 2 * (PM_BFEXT(DIV, control) + 1);
 532
 533         return clk->parent->get_rate(clk->parent) / div;
 534 }
 535
 536 static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
 537 {
 538         u32 control;
 539         unsigned long parent_rate, actual_rate, div;
 540
 541         parent_rate = clk->parent->get_rate(clk->parent);
 542         control = pm_readl(GCCTRL(clk->index));
 543
 544         if (rate > 3 * parent_rate / 4) {
 545                 actual_rate = parent_rate;
 546                 control &= ~PM_BIT(DIVEN);
 547         } else {
 548                 div = (parent_rate + rate) / (2 * rate) - 1;
 549                 control = PM_BFINS(DIV, div, control) | PM_BIT(DIVEN);
 550                 actual_rate = parent_rate / (2 * (div + 1));
 551         }
 552
 553         dev_dbg(clk->dev, "clk %s: new rate %lu (actual rate %lu)\n",
 554                 clk->name, rate, actual_rate);
 555
 556         if (apply)
 557                 pm_writel(GCCTRL(clk->index), control);
 558
 559         return actual_rate;
 560 }
 561
 562 int genclk_set_parent(struct clk *clk, struct clk *parent)
 563 {
 564         u32 control;
 565
 566         dev_dbg(clk->dev, "clk %s: new parent %s (was %s)\n",
 567                 clk->name, parent->name, clk->parent->name);
 568
 569         control = pm_readl(GCCTRL(clk->index));
 570
 571         if (parent == &osc1 || parent == &pll1)
 572                 control |= PM_BIT(OSCSEL);
 573         else if (parent == &osc0 || parent == &pll0)
 574                 control &= ~PM_BIT(OSCSEL);
 575         else
 576                 return -EINVAL;
 577
 578         if (parent == &pll0 || parent == &pll1)
 579                 control |= PM_BIT(PLLSEL);
 580         else
 581                 control &= ~PM_BIT(PLLSEL);
 582
 583         pm_writel(GCCTRL(clk->index), control);
 584         clk->parent = parent;
 585
 586         return 0;
 587 }
 588
 589 static void __init genclk_init_parent(struct clk *clk)
 590 {
 591         u32 control;
 592         struct clk *parent;
 593
 594         BUG_ON(clk->index > 7);
 595
 596         control = pm_readl(GCCTRL(clk->index));
 597         if (control & PM_BIT(OSCSEL))
 598                 parent = (control & PM_BIT(PLLSEL)) ? &pll1 : &osc1;
 599         else
 600                 parent = (control & PM_BIT(PLLSEL)) ? &pll0 : &osc0;
 601
 602         clk->parent = parent;
 603 }
 604
 605 static struct dw_dma_platform_data dw_dmac0_data = {
 606         .nr_channels    = 3,
 607 };
 608
 609 static struct resource dw_dmac0_resource[] = {
 610         PBMEM(0xff200000),
 611         IRQ(2),
 612 };
 613 DEFINE_DEV_DATA(dw_dmac, 0);
 614 DEV_CLK(hclk, dw_dmac0, hsb, 10);
 615
 616 /* --------------------------------------------------------------------
 617  *  System peripherals
 618  * -------------------------------------------------------------------- */
 619 static struct resource at32_pm0_resource[] = {
 620         {
 621                 .start  = 0xfff00000,
 622                 .end    = 0xfff0007f,
 623                 .flags  = IORESOURCE_MEM,
 624         },
 625         IRQ(20),
 626 };
 627
 628 static struct resource at32ap700x_rtc0_resource[] = {
 629         {
 630                 .start  = 0xfff00080,
 631                 .end    = 0xfff000af,
 632                 .flags  = IORESOURCE_MEM,
 633         },
 634         IRQ(21),
 635 };
 636
 637 static struct resource at32_wdt0_resource[] = {
 638         {
 639                 .start  = 0xfff000b0,
 640                 .end    = 0xfff000cf,
 641                 .flags  = IORESOURCE_MEM,
 642         },
 643 };
 644
 645 static struct resource at32_eic0_resource[] = {
 646         {
 647                 .start  = 0xfff00100,
 648                 .end    = 0xfff0013f,
 649                 .flags  = IORESOURCE_MEM,
 650         },
 651         IRQ(19),
 652 };
 653
 654 DEFINE_DEV(at32_pm, 0);
 655 DEFINE_DEV(at32ap700x_rtc, 0);
 656 DEFINE_DEV(at32_wdt, 0);
 657 DEFINE_DEV(at32_eic, 0);
 658
 659 /*
 660  * Peripheral clock for PM, RTC, WDT and EIC. PM will ensure that this
 661  * is always running.
 662  */
 663 static struct clk at32_pm_pclk = {
 664         .name           = "pclk",
 665         .dev            = &at32_pm0_device.dev,
 666         .parent         = &pbb_clk,
 667         .mode           = pbb_clk_mode,
 668         .get_rate       = pbb_clk_get_rate,
 669         .users          = 1,
 670         .index          = 0,
 671 };
 672
 673 static struct resource intc0_resource[] = {
 674         PBMEM(0xfff00400),
 675 };
 676 struct platform_device at32_intc0_device = {
 677         .name           = "intc",
 678         .id             = 0,
 679         .resource       = intc0_resource,
 680         .num_resources  = ARRAY_SIZE(intc0_resource),
 681 };
 682 DEV_CLK(pclk, at32_intc0, pbb, 1);
 683
 684 static struct clk ebi_clk = {
 685         .name           = "ebi",
 686         .parent         = &hsb_clk,
 687         .mode           = hsb_clk_mode,
 688         .get_rate       = hsb_clk_get_rate,
 689         .users          = 1,
 690 };
 691 static struct clk hramc_clk = {
 692         .name           = "hramc",
 693         .parent         = &hsb_clk,
 694         .mode           = hsb_clk_mode,
 695         .get_rate       = hsb_clk_get_rate,
 696         .users          = 1,
 697         .index          = 3,
 698 };
 699 static struct clk sdramc_clk = {
 700         .name           = "sdramc_clk",
 701         .parent         = &pbb_clk,
 702         .mode           = pbb_clk_mode,
 703         .get_rate       = pbb_clk_get_rate,
 704         .users          = 1,
 705         .index          = 14,
 706 };
 707
 708 static struct resource smc0_resource[] = {
 709         PBMEM(0xfff03400),
 710 };
 711 DEFINE_DEV(smc, 0);
 712 DEV_CLK(pclk, smc0, pbb, 13);
 713 DEV_CLK(mck, smc0, hsb, 0);
 714
 715 static struct platform_device pdc_device = {
 716         .name           = "pdc",
 717         .id             = 0,
 718 };
 719 DEV_CLK(hclk, pdc, hsb, 4);
 720 DEV_CLK(pclk, pdc, pba, 16);
 721
 722 static struct clk pico_clk = {
 723         .name           = "pico",
 724         .parent         = &cpu_clk,
 725         .mode           = cpu_clk_mode,
 726         .get_rate       = cpu_clk_get_rate,
 727         .users          = 1,
 728 };
 729
 730 /* --------------------------------------------------------------------
 731  * HMATRIX
 732  * -------------------------------------------------------------------- */
 733
 734 struct clk at32_hmatrix_clk = {
 735         .name           = "hmatrix_clk",
 736         .parent         = &pbb_clk,
 737         .mode           = pbb_clk_mode,
 738         .get_rate       = pbb_clk_get_rate,
 739         .index          = 2,
 740         .users          = 1,
 741 };
 742
 743 /*
 744  * Set bits in the HMATRIX Special Function Register (SFR) used by the
 745  * External Bus Interface (EBI). This can be used to enable special
 746  * features like CompactFlash support, NAND Flash support, etc. on
 747  * certain chipselects.
 748  */
 749 static inline void set_ebi_sfr_bits(u32 mask)
 750 {
 751         hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, mask);
 752 }
 753
 754 /* --------------------------------------------------------------------
 755  *  Timer/Counter (TC)
 756  * -------------------------------------------------------------------- */
 757
 758 static struct resource at32_tcb0_resource[] = {
 759         PBMEM(0xfff00c00),
 760         IRQ(22),
 761 };
 762 static struct platform_device at32_tcb0_device = {
 763         .name           = "atmel_tcb",
 764         .id             = 0,
 765         .resource       = at32_tcb0_resource,
 766         .num_resources  = ARRAY_SIZE(at32_tcb0_resource),
 767 };
 768 DEV_CLK(t0_clk, at32_tcb0, pbb, 3);
 769
 770 static struct resource at32_tcb1_resource[] = {
 771         PBMEM(0xfff01000),
 772         IRQ(23),
 773 };
 774 static struct platform_device at32_tcb1_device = {
 775         .name           = "atmel_tcb",
 776         .id             = 1,
 777         .resource       = at32_tcb1_resource,
 778         .num_resources  = ARRAY_SIZE(at32_tcb1_resource),
 779 };
 780 DEV_CLK(t0_clk, at32_tcb1, pbb, 4);
 781
 782 /* --------------------------------------------------------------------
 783  *  PIO
 784  * -------------------------------------------------------------------- */
 785
 786 static struct resource pio0_resource[] = {
 787         PBMEM(0xffe02800),
 788         IRQ(13),
 789 };
 790 DEFINE_DEV(pio, 0);
 791 DEV_CLK(mck, pio0, pba, 10);
 792
 793 static struct resource pio1_resource[] = {
 794         PBMEM(0xffe02c00),
 795         IRQ(14),
 796 };
 797 DEFINE_DEV(pio, 1);
 798 DEV_CLK(mck, pio1, pba, 11);
 799
 800 static struct resource pio2_resource[] = {
 801         PBMEM(0xffe03000),
 802         IRQ(15),
 803 };
 804 DEFINE_DEV(pio, 2);
 805 DEV_CLK(mck, pio2, pba, 12);
 806
 807 static struct resource pio3_resource[] = {
 808         PBMEM(0xffe03400),
 809         IRQ(16),
 810 };
 811 DEFINE_DEV(pio, 3);
 812 DEV_CLK(mck, pio3, pba, 13);
 813
 814 static struct resource pio4_resource[] = {
 815         PBMEM(0xffe03800),
 816         IRQ(17),
 817 };
 818 DEFINE_DEV(pio, 4);
 819 DEV_CLK(mck, pio4, pba, 14);
 820
 821 static int __init system_device_init(void)
 822 {
 823         platform_device_register(&at32_pm0_device);
 824         platform_device_register(&at32_intc0_device);
 825         platform_device_register(&at32ap700x_rtc0_device);
 826         platform_device_register(&at32_wdt0_device);
 827         platform_device_register(&at32_eic0_device);
 828         platform_device_register(&smc0_device);
 829         platform_device_register(&pdc_device);
 830         platform_device_register(&dw_dmac0_device);
 831
 832         platform_device_register(&at32_tcb0_device);
 833         platform_device_register(&at32_tcb1_device);
 834
 835         platform_device_register(&pio0_device);
 836         platform_device_register(&pio1_device);
 837         platform_device_register(&pio2_device);
 838         platform_device_register(&pio3_device);
 839         platform_device_register(&pio4_device);
 840
 841         return 0;
 842 }
 843 core_initcall(system_device_init);
 844
 845 /* --------------------------------------------------------------------
 846  *  PSIF
 847  * -------------------------------------------------------------------- */
 848 static struct resource atmel_psif0_resource[] __initdata = {
 849         {
 850                 .start  = 0xffe03c00,
 851                 .end    = 0xffe03cff,
 852                 .flags  = IORESOURCE_MEM,
 853         },
 854         IRQ(18),
 855 };
 856 static struct clk atmel_psif0_pclk = {
 857         .name           = "pclk",
 858         .parent         = &pba_clk,
 859         .mode           = pba_clk_mode,
 860         .get_rate       = pba_clk_get_rate,
 861         .index          = 15,
 862 };
 863
 864 static struct resource atmel_psif1_resource[] __initdata = {
 865         {
 866                 .start  = 0xffe03d00,
 867                 .end    = 0xffe03dff,
 868                 .flags  = IORESOURCE_MEM,
 869         },
 870         IRQ(18),
 871 };
 872 static struct clk atmel_psif1_pclk = {
 873         .name           = "pclk",
 874         .parent         = &pba_clk,
 875         .mode           = pba_clk_mode,
 876         .get_rate       = pba_clk_get_rate,
 877         .index          = 15,
 878 };
 879
 880 struct platform_device *__init at32_add_device_psif(unsigned int id)
 881 {
 882         struct platform_device *pdev;
 883         u32 pin_mask;
 884
 885         if (!(id == 0 || id == 1))
 886                 return NULL;
 887
 888         pdev = platform_device_alloc("atmel_psif", id);
 889         if (!pdev)
 890                 return NULL;
 891
 892         switch (id) {
 893         case 0:
 894                 pin_mask  = (1 << 8) | (1 << 9); /* CLOCK & DATA */
 895
 896                 if (platform_device_add_resources(pdev, atmel_psif0_resource,
 897                                         ARRAY_SIZE(atmel_psif0_resource)))
 898                         goto err_add_resources;
 899                 atmel_psif0_pclk.dev = &pdev->dev;
 900                 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
 901                 break;
 902         case 1:
 903                 pin_mask  = (1 << 11) | (1 << 12); /* CLOCK & DATA */
 904
 905                 if (platform_device_add_resources(pdev, atmel_psif1_resource,
 906                                         ARRAY_SIZE(atmel_psif1_resource)))
 907                         goto err_add_resources;
 908                 atmel_psif1_pclk.dev = &pdev->dev;
 909                 select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
 910                 break;
 911         default:
 912                 return NULL;
 913         }
 914
 915         platform_device_add(pdev);
 916         return pdev;
 917
 918 err_add_resources:
 919         platform_device_put(pdev);
 920         return NULL;
 921 }
 922
 923 /* --------------------------------------------------------------------
 924  *  USART
 925  * -------------------------------------------------------------------- */
 926
 927 static struct atmel_uart_data atmel_usart0_data = {
 928         .use_dma_tx     = 1,
 929         .use_dma_rx     = 1,
 930 };
 931 static struct resource atmel_usart0_resource[] = {
 932         PBMEM(0xffe00c00),
 933         IRQ(6),
 934 };
 935 DEFINE_DEV_DATA(atmel_usart, 0);
 936 DEV_CLK(usart, atmel_usart0, pba, 3);
 937
 938 static struct atmel_uart_data atmel_usart1_data = {
 939         .use_dma_tx     = 1,
 940         .use_dma_rx     = 1,
 941 };
 942 static struct resource atmel_usart1_resource[] = {
 943         PBMEM(0xffe01000),
 944         IRQ(7),
 945 };
 946 DEFINE_DEV_DATA(atmel_usart, 1);
 947 DEV_CLK(usart, atmel_usart1, pba, 4);
 948
 949 static struct atmel_uart_data atmel_usart2_data = {
 950         .use_dma_tx     = 1,
 951         .use_dma_rx     = 1,
 952 };
 953 static struct resource atmel_usart2_resource[] = {
 954         PBMEM(0xffe01400),
 955         IRQ(8),
 956 };
 957 DEFINE_DEV_DATA(atmel_usart, 2);
 958 DEV_CLK(usart, atmel_usart2, pba, 5);
 959
 960 static struct atmel_uart_data atmel_usart3_data = {
 961         .use_dma_tx     = 1,
 962         .use_dma_rx     = 1,
 963 };
 964 static struct resource atmel_usart3_resource[] = {
 965         PBMEM(0xffe01800),
 966         IRQ(9),
 967 };
 968 DEFINE_DEV_DATA(atmel_usart, 3);
 969 DEV_CLK(usart, atmel_usart3, pba, 6);
 970
 971 static inline void configure_usart0_pins(int flags)
 972 {
 973         u32 pin_mask = (1 << 8) | (1 << 9); /* RXD & TXD */
 974         if (flags & ATMEL_USART_RTS)    pin_mask |= (1 << 6);
 975         if (flags & ATMEL_USART_CTS)    pin_mask |= (1 << 7);
 976         if (flags & ATMEL_USART_CLK)    pin_mask |= (1 << 10);
 977
 978         select_peripheral(PIOA, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP);
 979 }
 980
 981 static inline void configure_usart1_pins(int flags)
 982 {
 983         u32 pin_mask = (1 << 17) | (1 << 18); /* RXD & TXD */
 984         if (flags & ATMEL_USART_RTS)    pin_mask |= (1 << 19);
 985         if (flags & ATMEL_USART_CTS)    pin_mask |= (1 << 20);
 986         if (flags & ATMEL_USART_CLK)    pin_mask |= (1 << 16);
 987
 988         select_peripheral(PIOA, pin_mask, PERIPH_A, AT32_GPIOF_PULLUP);
 989 }
 990
 991 static inline void configure_usart2_pins(int flags)
 992 {
 993         u32 pin_mask = (1 << 26) | (1 << 27); /* RXD & TXD */
 994         if (flags & ATMEL_USART_RTS)    pin_mask |= (1 << 30);
 995         if (flags & ATMEL_USART_CTS)    pin_mask |= (1 << 29);
 996         if (flags & ATMEL_USART_CLK)    pin_mask |= (1 << 28);
 997
 998         select_peripheral(PIOB, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP);
 999 }
1000
1001 static inline void configure_usart3_pins(int flags)
1002 {
1003         u32 pin_mask = (1 << 18) | (1 << 17); /* RXD & TXD */
1004         if (flags & ATMEL_USART_RTS)    pin_mask |= (1 << 16);
1005         if (flags & ATMEL_USART_CTS)    pin_mask |= (1 << 15);
1006         if (flags & ATMEL_USART_CLK)    pin_mask |= (1 << 19);
1007
1008         select_peripheral(PIOB, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP);
1009 }
1010
1011 static struct platform_device *__initdata at32_usarts[4];
1012
1013 void __init at32_map_usart(unsigned int hw_id, unsigned int line, int flags)
1014 {
1015         struct platform_device *pdev;
1016
1017         switch (hw_id) {
1018         case 0:
1019                 pdev = &atmel_usart0_device;
1020                 configure_usart0_pins(flags);
1021                 break;
1022         case 1:
1023                 pdev = &atmel_usart1_device;
1024                 configure_usart1_pins(flags);
1025                 break;
1026         case 2:
1027                 pdev = &atmel_usart2_device;
1028                 configure_usart2_pins(flags);
1029                 break;
1030         case 3:
1031                 pdev = &atmel_usart3_device;
1032                 configure_usart3_pins(flags);
1033                 break;
1034         default:
1035                 return;
1036         }
1037
1038         if (PXSEG(pdev->resource[0].start) == P4SEG) {
1039                 /* Addresses in the P4 segment are permanently mapped 1:1 */
1040                 struct atmel_uart_data *data = pdev->dev.platform_data;
1041                 data->regs = (void __iomem *)pdev->resource[0].start;
1042         }
1043
1044         pdev->id = line;
1045         at32_usarts[line] = pdev;
1046 }
1047
1048 struct platform_device *__init at32_add_device_usart(unsigned int id)
1049 {
1050         platform_device_register(at32_usarts[id]);
1051         return at32_usarts[id];
1052 }
1053
1054 struct platform_device *atmel_default_console_device;
1055
1056 void __init at32_setup_serial_console(unsigned int usart_id)
1057 {
1058         atmel_default_console_device = at32_usarts[usart_id];
1059 }
1060
1061 /* --------------------------------------------------------------------
1062  *  Ethernet
1063  * -------------------------------------------------------------------- */
1064
1065 #ifdef CONFIG_CPU_AT32AP7000
1066 static struct eth_platform_data macb0_data;
1067 static struct resource macb0_resource[] = {
1068         PBMEM(0xfff01800),
1069         IRQ(25),
1070 };
1071 DEFINE_DEV_DATA(macb, 0);
1072 DEV_CLK(hclk, macb0, hsb, 8);
1073 DEV_CLK(pclk, macb0, pbb, 6);
1074
1075 static struct eth_platform_data macb1_data;
1076 static struct resource macb1_resource[] = {
1077         PBMEM(0xfff01c00),
1078         IRQ(26),
1079 };
1080 DEFINE_DEV_DATA(macb, 1);
1081 DEV_CLK(hclk, macb1, hsb, 9);
1082 DEV_CLK(pclk, macb1, pbb, 7);
1083
1084 struct platform_device *__init
1085 at32_add_device_eth(unsigned int id, struct eth_platform_data *data)
1086 {
1087         struct platform_device *pdev;
1088         u32 pin_mask;
1089
1090         switch (id) {
1091         case 0:
1092                 pdev = &macb0_device;
1093
1094                 pin_mask  = (1 << 3);   /* TXD0 */
1095                 pin_mask |= (1 << 4);   /* TXD1 */
1096                 pin_mask |= (1 << 7);   /* TXEN */
1097                 pin_mask |= (1 << 8);   /* TXCK */
1098                 pin_mask |= (1 << 9);   /* RXD0 */
1099                 pin_mask |= (1 << 10);  /* RXD1 */
1100                 pin_mask |= (1 << 13);  /* RXER */
1101                 pin_mask |= (1 << 15);  /* RXDV */
1102                 pin_mask |= (1 << 16);  /* MDC  */
1103                 pin_mask |= (1 << 17);  /* MDIO */
1104
1105                 if (!data->is_rmii) {
1106                         pin_mask |= (1 << 0);   /* COL  */
1107                         pin_mask |= (1 << 1);   /* CRS  */
1108                         pin_mask |= (1 << 2);   /* TXER */
1109                         pin_mask |= (1 << 5);   /* TXD2 */
1110                         pin_mask |= (1 << 6);   /* TXD3 */
1111                         pin_mask |= (1 << 11);  /* RXD2 */
1112                         pin_mask |= (1 << 12);  /* RXD3 */
1113                         pin_mask |= (1 << 14);  /* RXCK */
1114 #ifndef CONFIG_BOARD_MIMC200
1115                         pin_mask |= (1 << 18);  /* SPD  */
1116 #endif
1117                 }
1118
1119                 select_peripheral(PIOC, pin_mask, PERIPH_A, 0);
1120
1121                 break;
1122
1123         case 1:
1124                 pdev = &macb1_device;
1125
1126                 pin_mask  = (1 << 13);  /* TXD0 */
1127                 pin_mask |= (1 << 14);  /* TXD1 */
1128                 pin_mask |= (1 << 11);  /* TXEN */
1129                 pin_mask |= (1 << 12);  /* TXCK */
1130                 pin_mask |= (1 << 10);  /* RXD0 */
1131                 pin_mask |= (1 << 6);   /* RXD1 */
1132                 pin_mask |= (1 << 5);   /* RXER */
1133                 pin_mask |= (1 << 4);   /* RXDV */
1134                 pin_mask |= (1 << 3);   /* MDC  */
1135                 pin_mask |= (1 << 2);   /* MDIO */
1136
1137 #ifndef CONFIG_BOARD_MIMC200
1138                 if (!data->is_rmii)
1139                         pin_mask |= (1 << 15);  /* SPD  */
1140 #endif
1141
1142                 select_peripheral(PIOD, pin_mask, PERIPH_B, 0);
1143
1144                 if (!data->is_rmii) {
1145                         pin_mask  = (1 << 19);  /* COL  */
1146                         pin_mask |= (1 << 23);  /* CRS  */
1147                         pin_mask |= (1 << 26);  /* TXER */
1148                         pin_mask |= (1 << 27);  /* TXD2 */
1149                         pin_mask |= (1 << 28);  /* TXD3 */
1150                         pin_mask |= (1 << 29);  /* RXD2 */
1151                         pin_mask |= (1 << 30);  /* RXD3 */
1152                         pin_mask |= (1 << 24);  /* RXCK */
1153
1154                         select_peripheral(PIOC, pin_mask, PERIPH_B, 0);
1155                 }
1156                 break;
1157
1158         default:
1159                 return NULL;
1160         }
1161
1162         memcpy(pdev->dev.platform_data, data, sizeof(struct eth_platform_data));
1163         platform_device_register(pdev);
1164
1165         return pdev;
1166 }
1167 #endif
1168
1169 /* --------------------------------------------------------------------
1170  *  SPI
1171  * -------------------------------------------------------------------- */
1172 static struct resource atmel_spi0_resource[] = {
1173         PBMEM(0xffe00000),
1174         IRQ(3),
1175 };
1176 DEFINE_DEV(atmel_spi, 0);
1177 DEV_CLK(spi_clk, atmel_spi0, pba, 0);
1178
1179 static struct resource atmel_spi1_resource[] = {
1180         PBMEM(0xffe00400),
1181         IRQ(4),
1182 };
1183 DEFINE_DEV(atmel_spi, 1);
1184 DEV_CLK(spi_clk, atmel_spi1, pba, 1);
1185
1186 void __init
1187 at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b, unsigned int n)
1188 {
1189         /*
1190          * Manage the chipselects as GPIOs, normally using the same pins
1191          * the SPI controller expects; but boards can use other pins.
1192          */
1193         static u8 __initdata spi_pins[][4] = {
1194                 { GPIO_PIN_PA(3), GPIO_PIN_PA(4),
1195                   GPIO_PIN_PA(5), GPIO_PIN_PA(20) },
1196                 { GPIO_PIN_PB(2), GPIO_PIN_PB(3),
1197                   GPIO_PIN_PB(4), GPIO_PIN_PA(27) },
1198         };
1199         unsigned int pin, mode;
1200
1201         /* There are only 2 SPI controllers */
1202         if (bus_num > 1)
1203                 return;
1204
1205         for (; n; n--, b++) {
1206                 b->bus_num = bus_num;
1207                 if (b->chip_select >= 4)
1208                         continue;
1209                 pin = (unsigned)b->controller_data;
1210                 if (!pin) {
1211                         pin = spi_pins[bus_num][b->chip_select];
1212                         b->controller_data = (void *)pin;
1213                 }
1214                 mode = AT32_GPIOF_OUTPUT;
1215                 if (!(b->mode & SPI_CS_HIGH))
1216                         mode |= AT32_GPIOF_HIGH;
1217                 at32_select_gpio(pin, mode);
1218         }
1219 }
1220
1221 struct platform_device *__init
1222 at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
1223 {
1224         struct platform_device *pdev;
1225         u32 pin_mask;
1226
1227         switch (id) {
1228         case 0:
1229                 pdev = &atmel_spi0_device;
1230                 pin_mask  = (1 << 1) | (1 << 2);        /* MOSI & SCK */
1231
1232                 /* pullup MISO so a level is always defined */
1233                 select_peripheral(PIOA, (1 << 0), PERIPH_A, AT32_GPIOF_PULLUP);
1234                 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1235
1236                 at32_spi_setup_slaves(0, b, n);
1237                 break;
1238
1239         case 1:
1240                 pdev = &atmel_spi1_device;
1241                 pin_mask  = (1 << 1) | (1 << 5);        /* MOSI */
1242
1243                 /* pullup MISO so a level is always defined */
1244                 select_peripheral(PIOB, (1 << 0), PERIPH_B, AT32_GPIOF_PULLUP);
1245                 select_peripheral(PIOB, pin_mask, PERIPH_B, 0);
1246
1247                 at32_spi_setup_slaves(1, b, n);
1248                 break;
1249
1250         default:
1251                 return NULL;
1252         }
1253
1254         spi_register_board_info(b, n);
1255         platform_device_register(pdev);
1256         return pdev;
1257 }
1258
1259 /* --------------------------------------------------------------------
1260  *  TWI
1261  * -------------------------------------------------------------------- */
1262 static struct resource atmel_twi0_resource[] __initdata = {
1263         PBMEM(0xffe00800),
1264         IRQ(5),
1265 };
1266 static struct clk atmel_twi0_pclk = {
1267         .name           = "twi_pclk",
1268         .parent         = &pba_clk,
1269         .mode           = pba_clk_mode,
1270         .get_rate       = pba_clk_get_rate,
1271         .index          = 2,
1272 };
1273
1274 struct platform_device *__init at32_add_device_twi(unsigned int id,
1275                                                     struct i2c_board_info *b,
1276                                                     unsigned int n)
1277 {
1278         struct platform_device *pdev;
1279         u32 pin_mask;
1280
1281         if (id != 0)
1282                 return NULL;
1283
1284         pdev = platform_device_alloc("atmel_twi", id);
1285         if (!pdev)
1286                 return NULL;
1287
1288         if (platform_device_add_resources(pdev, atmel_twi0_resource,
1289                                 ARRAY_SIZE(atmel_twi0_resource)))
1290                 goto err_add_resources;
1291
1292         pin_mask  = (1 << 6) | (1 << 7);        /* SDA & SDL */
1293
1294         select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1295
1296         atmel_twi0_pclk.dev = &pdev->dev;
1297
1298         if (b)
1299                 i2c_register_board_info(id, b, n);
1300
1301         platform_device_add(pdev);
1302         return pdev;
1303
1304 err_add_resources:
1305         platform_device_put(pdev);
1306         return NULL;
1307 }
1308
1309 /* --------------------------------------------------------------------
1310  * MMC
1311  * -------------------------------------------------------------------- */
1312 static struct resource atmel_mci0_resource[] __initdata = {
1313         PBMEM(0xfff02400),
1314         IRQ(28),
1315 };
1316 static struct clk atmel_mci0_pclk = {
1317         .name           = "mci_clk",
1318         .parent         = &pbb_clk,
1319         .mode           = pbb_clk_mode,
1320         .get_rate       = pbb_clk_get_rate,
1321         .index          = 9,
1322 };
1323
1324 struct platform_device *__init
1325 at32_add_device_mci(unsigned int id, struct mci_platform_data *data)
1326 {
1327         struct platform_device          *pdev;
1328         struct mci_dma_slave            *slave;
1329         u32                             pioa_mask;
1330         u32                             piob_mask;
1331
1332         if (id != 0 || !data)
1333                 return NULL;
1334
1335         /* Must have at least one usable slot */
1336         if (!data->slot[0].bus_width && !data->slot[1].bus_width)
1337                 return NULL;
1338
1339         pdev = platform_device_alloc("atmel_mci", id);
1340         if (!pdev)
1341                 goto fail;
1342
1343         if (platform_device_add_resources(pdev, atmel_mci0_resource,
1344                                 ARRAY_SIZE(atmel_mci0_resource)))
1345                 goto fail;
1346
1347         slave = kzalloc(sizeof(struct mci_dma_slave), GFP_KERNEL);
1348
1349         slave->sdata.dma_dev = &dw_dmac0_device.dev;
1350         slave->sdata.reg_width = DW_DMA_SLAVE_WIDTH_32BIT;
1351         slave->sdata.cfg_hi = (DWC_CFGH_SRC_PER(0)
1352                                 | DWC_CFGH_DST_PER(1));
1353         slave->sdata.cfg_lo &= ~(DWC_CFGL_HS_DST_POL
1354                                 | DWC_CFGL_HS_SRC_POL);
1355
1356         data->dma_slave = slave;
1357
1358         if (platform_device_add_data(pdev, data,
1359                                 sizeof(struct mci_platform_data)))
1360                 goto fail;
1361
1362         /* CLK line is common to both slots */
1363         pioa_mask = 1 << 10;
1364
1365         switch (data->slot[0].bus_width) {
1366         case 4:
1367                 pioa_mask |= 1 << 13;           /* DATA1 */
1368                 pioa_mask |= 1 << 14;           /* DATA2 */
1369                 pioa_mask |= 1 << 15;           /* DATA3 */
1370                 /* fall through */
1371         case 1:
1372                 pioa_mask |= 1 << 11;           /* CMD   */
1373                 pioa_mask |= 1 << 12;           /* DATA0 */
1374
1375                 if (gpio_is_valid(data->slot[0].detect_pin))
1376                         at32_select_gpio(data->slot[0].detect_pin, 0);
1377                 if (gpio_is_valid(data->slot[0].wp_pin))
1378                         at32_select_gpio(data->slot[0].wp_pin, 0);
1379                 break;
1380         case 0:
1381                 /* Slot is unused */
1382                 break;
1383         default:
1384                 goto fail;
1385         }
1386
1387         select_peripheral(PIOA, pioa_mask, PERIPH_A, 0);
1388         piob_mask = 0;
1389
1390         switch (data->slot[1].bus_width) {
1391         case 4:
1392                 piob_mask |= 1 <<  8;           /* DATA1 */
1393                 piob_mask |= 1 <<  9;           /* DATA2 */
1394                 piob_mask |= 1 << 10;           /* DATA3 */
1395                 /* fall through */
1396         case 1:
1397                 piob_mask |= 1 <<  6;           /* CMD   */
1398                 piob_mask |= 1 <<  7;           /* DATA0 */
1399                 select_peripheral(PIOB, piob_mask, PERIPH_B, 0);
1400
1401                 if (gpio_is_valid(data->slot[1].detect_pin))
1402                         at32_select_gpio(data->slot[1].detect_pin, 0);
1403                 if (gpio_is_valid(data->slot[1].wp_pin))
1404                         at32_select_gpio(data->slot[1].wp_pin, 0);
1405                 break;
1406         case 0:
1407                 /* Slot is unused */
1408                 break;
1409         default:
1410                 if (!data->slot[0].bus_width)
1411                         goto fail;
1412
1413                 data->slot[1].bus_width = 0;
1414                 break;
1415         }
1416
1417         atmel_mci0_pclk.dev = &pdev->dev;
1418
1419         platform_device_add(pdev);
1420         return pdev;
1421
1422 fail:
1423         data->dma_slave = NULL;
1424         kfree(slave);
1425         platform_device_put(pdev);
1426         return NULL;
1427 }
1428
1429 /* --------------------------------------------------------------------
1430  *  LCDC
1431  * -------------------------------------------------------------------- */
1432 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
1433 static struct atmel_lcdfb_info atmel_lcdfb0_data;
1434 static struct resource atmel_lcdfb0_resource[] = {
1435         {
1436                 .start          = 0xff000000,
1437                 .end            = 0xff000fff,
1438                 .flags          = IORESOURCE_MEM,
1439         },
1440         IRQ(1),
1441         {
1442                 /* Placeholder for pre-allocated fb memory */
1443                 .start          = 0x00000000,
1444                 .end            = 0x00000000,
1445                 .flags          = 0,
1446         },
1447 };
1448 DEFINE_DEV_DATA(atmel_lcdfb, 0);
1449 DEV_CLK(hck1, atmel_lcdfb0, hsb, 7);
1450 static struct clk atmel_lcdfb0_pixclk = {
1451         .name           = "lcdc_clk",
1452         .dev            = &atmel_lcdfb0_device.dev,
1453         .mode           = genclk_mode,
1454         .get_rate       = genclk_get_rate,
1455         .set_rate       = genclk_set_rate,
1456         .set_parent     = genclk_set_parent,
1457         .index          = 7,
1458 };
1459
1460 struct platform_device *__init
1461 at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
1462                      unsigned long fbmem_start, unsigned long fbmem_len,
1463                      u64 pin_mask)
1464 {
1465         struct platform_device *pdev;
1466         struct atmel_lcdfb_info *info;
1467         struct fb_monspecs *monspecs;
1468         struct fb_videomode *modedb;
1469         unsigned int modedb_size;
1470         u32 portc_mask, portd_mask, porte_mask;
1471
1472         /*
1473          * Do a deep copy of the fb data, monspecs and modedb. Make
1474          * sure all allocations are done before setting up the
1475          * portmux.
1476          */
1477         monspecs = kmemdup(data->default_monspecs,
1478                            sizeof(struct fb_monspecs), GFP_KERNEL);
1479         if (!monspecs)
1480                 return NULL;
1481
1482         modedb_size = sizeof(struct fb_videomode) * monspecs->modedb_len;
1483         modedb = kmemdup(monspecs->modedb, modedb_size, GFP_KERNEL);
1484         if (!modedb)
1485                 goto err_dup_modedb;
1486         monspecs->modedb = modedb;
1487
1488         switch (id) {
1489         case 0:
1490                 pdev = &atmel_lcdfb0_device;
1491
1492                 if (pin_mask == 0ULL)
1493                         /* Default to "full" lcdc control signals and 24bit */
1494                         pin_mask = ATMEL_LCDC_PRI_24BIT | ATMEL_LCDC_PRI_CONTROL;
1495
1496                 /* LCDC on port C */
1497                 portc_mask = pin_mask & 0xfff80000;
1498                 select_peripheral(PIOC, portc_mask, PERIPH_A, 0);
1499
1500                 /* LCDC on port D */
1501                 portd_mask = pin_mask & 0x0003ffff;
1502                 select_peripheral(PIOD, portd_mask, PERIPH_A, 0);
1503
1504                 /* LCDC on port E */
1505                 porte_mask = (pin_mask >> 32) & 0x0007ffff;
1506                 select_peripheral(PIOE, porte_mask, PERIPH_B, 0);
1507
1508                 clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
1509                 clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
1510                 break;
1511
1512         default:
1513                 goto err_invalid_id;
1514         }
1515
1516         if (fbmem_len) {
1517                 pdev->resource[2].start = fbmem_start;
1518                 pdev->resource[2].end = fbmem_start + fbmem_len - 1;
1519                 pdev->resource[2].flags = IORESOURCE_MEM;
1520         }
1521
1522         info = pdev->dev.platform_data;
1523         memcpy(info, data, sizeof(struct atmel_lcdfb_info));
1524         info->default_monspecs = monspecs;
1525
1526         platform_device_register(pdev);
1527         return pdev;
1528
1529 err_invalid_id:
1530         kfree(modedb);
1531 err_dup_modedb:
1532         kfree(monspecs);
1533         return NULL;
1534 }
1535 #endif
1536
1537 /* --------------------------------------------------------------------
1538  *  PWM
1539  * -------------------------------------------------------------------- */
1540 static struct resource atmel_pwm0_resource[] __initdata = {
1541         PBMEM(0xfff01400),
1542         IRQ(24),
1543 };
1544 static struct clk atmel_pwm0_mck = {
1545         .name           = "pwm_clk",
1546         .parent         = &pbb_clk,
1547         .mode           = pbb_clk_mode,
1548         .get_rate       = pbb_clk_get_rate,
1549         .index          = 5,
1550 };
1551
1552 struct platform_device *__init at32_add_device_pwm(u32 mask)
1553 {
1554         struct platform_device *pdev;
1555         u32 pin_mask;
1556
1557         if (!mask)
1558                 return NULL;
1559
1560         pdev = platform_device_alloc("atmel_pwm", 0);
1561         if (!pdev)
1562                 return NULL;
1563
1564         if (platform_device_add_resources(pdev, atmel_pwm0_resource,
1565                                 ARRAY_SIZE(atmel_pwm0_resource)))
1566                 goto out_free_pdev;
1567
1568         if (platform_device_add_data(pdev, &mask, sizeof(mask)))
1569                 goto out_free_pdev;
1570
1571         pin_mask = 0;
1572         if (mask & (1 << 0))
1573                 pin_mask |= (1 << 28);
1574         if (mask & (1 << 1))
1575                 pin_mask |= (1 << 29);
1576         if (pin_mask > 0)
1577                 select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1578
1579         pin_mask = 0;
1580         if (mask & (1 << 2))
1581                 pin_mask |= (1 << 21);
1582         if (mask & (1 << 3))
1583                 pin_mask |= (1 << 22);
1584         if (pin_mask > 0)
1585                 select_peripheral(PIOA, pin_mask, PERIPH_B, 0);
1586
1587         atmel_pwm0_mck.dev = &pdev->dev;
1588
1589         platform_device_add(pdev);
1590
1591         return pdev;
1592
1593 out_free_pdev:
1594         platform_device_put(pdev);
1595         return NULL;
1596 }
1597
1598 /* --------------------------------------------------------------------
1599  *  SSC
1600  * -------------------------------------------------------------------- */
1601 static struct resource ssc0_resource[] = {
1602         PBMEM(0xffe01c00),
1603         IRQ(10),
1604 };
1605 DEFINE_DEV(ssc, 0);
1606 DEV_CLK(pclk, ssc0, pba, 7);
1607
1608 static struct resource ssc1_resource[] = {
1609         PBMEM(0xffe02000),
1610         IRQ(11),
1611 };
1612 DEFINE_DEV(ssc, 1);
1613 DEV_CLK(pclk, ssc1, pba, 8);
1614
1615 static struct resource ssc2_resource[] = {
1616         PBMEM(0xffe02400),
1617         IRQ(12),
1618 };
1619 DEFINE_DEV(ssc, 2);
1620 DEV_CLK(pclk, ssc2, pba, 9);
1621
1622 struct platform_device *__init
1623 at32_add_device_ssc(unsigned int id, unsigned int flags)
1624 {
1625         struct platform_device *pdev;
1626         u32 pin_mask = 0;
1627
1628         switch (id) {
1629         case 0:
1630                 pdev = &ssc0_device;
1631                 if (flags & ATMEL_SSC_RF)
1632                         pin_mask |= (1 << 21);  /* RF */
1633                 if (flags & ATMEL_SSC_RK)
1634                         pin_mask |= (1 << 22);  /* RK */
1635                 if (flags & ATMEL_SSC_TK)
1636                         pin_mask |= (1 << 23);  /* TK */
1637                 if (flags & ATMEL_SSC_TF)
1638                         pin_mask |= (1 << 24);  /* TF */
1639                 if (flags & ATMEL_SSC_TD)
1640                         pin_mask |= (1 << 25);  /* TD */
1641                 if (flags & ATMEL_SSC_RD)
1642                         pin_mask |= (1 << 26);  /* RD */
1643
1644                 if (pin_mask > 0)
1645                         select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
1646
1647                 break;
1648         case 1:
1649                 pdev = &ssc1_device;
1650                 if (flags & ATMEL_SSC_RF)
1651                         pin_mask |= (1 << 0);   /* RF */
1652                 if (flags & ATMEL_SSC_RK)
1653                         pin_mask |= (1 << 1);   /* RK */
1654                 if (flags & ATMEL_SSC_TK)
1655                         pin_mask |= (1 << 2);   /* TK */
1656                 if (flags & ATMEL_SSC_TF)
1657                         pin_mask |= (1 << 3);   /* TF */
1658                 if (flags & ATMEL_SSC_TD)
1659                         pin_mask |= (1 << 4);   /* TD */
1660                 if (flags & ATMEL_SSC_RD)
1661                         pin_mask |= (1 << 5);   /* RD */
1662
1663                 if (pin_mask > 0)
1664                         select_peripheral(PIOA, pin_mask, PERIPH_B, 0);
1665
1666                 break;
1667         case 2:
1668                 pdev = &ssc2_device;
1669                 if (flags & ATMEL_SSC_TD)
1670                         pin_mask |= (1 << 13);  /* TD */
1671                 if (flags & ATMEL_SSC_RD)
1672                         pin_mask |= (1 << 14);  /* RD */
1673                 if (flags & ATMEL_SSC_TK)
1674                         pin_mask |= (1 << 15);  /* TK */
1675                 if (flags & ATMEL_SSC_TF)
1676                         pin_mask |= (1 << 16);  /* TF */
1677                 if (flags & ATMEL_SSC_RF)
1678                         pin_mask |= (1 << 17);  /* RF */
1679                 if (flags & ATMEL_SSC_RK)
1680                         pin_mask |= (1 << 18);  /* RK */
1681
1682                 if (pin_mask > 0)
1683                         select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
1684
1685                 break;
1686         default:
1687                 return NULL;
1688         }
1689
1690         platform_device_register(pdev);
1691         return pdev;
1692 }
1693
1694 /* --------------------------------------------------------------------
1695  *  USB Device Controller
1696  * -------------------------------------------------------------------- */
1697 static struct resource usba0_resource[] __initdata = {
1698         {
1699                 .start          = 0xff300000,
1700                 .end            = 0xff3fffff,
1701                 .flags          = IORESOURCE_MEM,
1702         }, {
1703                 .start          = 0xfff03000,
1704                 .end            = 0xfff033ff,
1705                 .flags          = IORESOURCE_MEM,
1706         },
1707         IRQ(31),
1708 };
1709 static struct clk usba0_pclk = {
1710         .name           = "pclk",
1711         .parent         = &pbb_clk,
1712         .mode           = pbb_clk_mode,
1713         .get_rate       = pbb_clk_get_rate,
1714         .index          = 12,
1715 };
1716 static struct clk usba0_hclk = {
1717         .name           = "hclk",
1718         .parent         = &hsb_clk,
1719         .mode           = hsb_clk_mode,
1720         .get_rate       = hsb_clk_get_rate,
1721         .index          = 6,
1722 };
1723
1724 #define EP(nam, idx, maxpkt, maxbk, dma, isoc)                  \
1725         [idx] = {                                               \
1726                 .name           = nam,                          \
1727                 .index          = idx,                          \
1728                 .fifo_size      = maxpkt,                       \
1729                 .nr_banks       = maxbk,                        \
1730                 .can_dma        = dma,                          \
1731                 .can_isoc       = isoc,                         \
1732         }
1733
1734 static struct usba_ep_data at32_usba_ep[] __initdata = {
1735         EP("ep0",     0,   64, 1, 0, 0),
1736         EP("ep1",     1,  512, 2, 1, 1),
1737         EP("ep2",     2,  512, 2, 1, 1),
1738         EP("ep3-int", 3,   64, 3, 1, 0),
1739         EP("ep4-int", 4,   64, 3, 1, 0),
1740         EP("ep5",     5, 1024, 3, 1, 1),
1741         EP("ep6",     6, 1024, 3, 1, 1),
1742 };
1743
1744 #undef EP
1745
1746 struct platform_device *__init
1747 at32_add_device_usba(unsigned int id, struct usba_platform_data *data)
1748 {
1749         /*
1750          * pdata doesn't have room for any endpoints, so we need to
1751          * append room for the ones we need right after it.
1752          */
1753         struct {
1754                 struct usba_platform_data pdata;
1755                 struct usba_ep_data ep[7];
1756         } usba_data;
1757         struct platform_device *pdev;
1758
1759         if (id != 0)
1760                 return NULL;
1761
1762         pdev = platform_device_alloc("atmel_usba_udc", 0);
1763         if (!pdev)
1764                 return NULL;
1765
1766         if (platform_device_add_resources(pdev, usba0_resource,
1767                                           ARRAY_SIZE(usba0_resource)))
1768                 goto out_free_pdev;
1769
1770         if (data)
1771                 usba_data.pdata.vbus_pin = data->vbus_pin;
1772         else
1773                 usba_data.pdata.vbus_pin = -EINVAL;
1774
1775         data = &usba_data.pdata;
1776         data->num_ep = ARRAY_SIZE(at32_usba_ep);
1777         memcpy(data->ep, at32_usba_ep, sizeof(at32_usba_ep));
1778
1779         if (platform_device_add_data(pdev, data, sizeof(usba_data)))
1780                 goto out_free_pdev;
1781
1782         if (gpio_is_valid(data->vbus_pin))
1783                 at32_select_gpio(data->vbus_pin, 0);
1784
1785         usba0_pclk.dev = &pdev->dev;
1786         usba0_hclk.dev = &pdev->dev;
1787
1788         platform_device_add(pdev);
1789
1790         return pdev;
1791
1792 out_free_pdev:
1793         platform_device_put(pdev);
1794         return NULL;
1795 }
1796
1797 /* --------------------------------------------------------------------
1798  * IDE / CompactFlash
1799  * -------------------------------------------------------------------- */
1800 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7001)
1801 static struct resource at32_smc_cs4_resource[] __initdata = {
1802         {
1803                 .start  = 0x04000000,
1804                 .end    = 0x07ffffff,
1805                 .flags  = IORESOURCE_MEM,
1806         },
1807         IRQ(~0UL), /* Magic IRQ will be overridden */
1808 };
1809 static struct resource at32_smc_cs5_resource[] __initdata = {
1810         {
1811                 .start  = 0x20000000,
1812                 .end    = 0x23ffffff,
1813                 .flags  = IORESOURCE_MEM,
1814         },
1815         IRQ(~0UL), /* Magic IRQ will be overridden */
1816 };
1817
1818 static int __init at32_init_ide_or_cf(struct platform_device *pdev,
1819                 unsigned int cs, unsigned int extint)
1820 {
1821         static unsigned int extint_pin_map[4] __initdata = {
1822                 (1 << 25),
1823                 (1 << 26),
1824                 (1 << 27),
1825                 (1 << 28),
1826         };
1827         static bool common_pins_initialized __initdata = false;
1828         unsigned int extint_pin;
1829         int ret;
1830         u32 pin_mask;
1831
1832         if (extint >= ARRAY_SIZE(extint_pin_map))
1833                 return -EINVAL;
1834         extint_pin = extint_pin_map[extint];
1835
1836         switch (cs) {
1837         case 4:
1838                 ret = platform_device_add_resources(pdev,
1839                                 at32_smc_cs4_resource,
1840                                 ARRAY_SIZE(at32_smc_cs4_resource));
1841                 if (ret)
1842                         return ret;
1843
1844                 /* NCS4   -> OE_N  */
1845                 select_peripheral(PIOE, (1 << 21), PERIPH_A, 0);
1846                 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_CF0_ENABLE);
1847                 break;
1848         case 5:
1849                 ret = platform_device_add_resources(pdev,
1850                                 at32_smc_cs5_resource,
1851                                 ARRAY_SIZE(at32_smc_cs5_resource));
1852                 if (ret)
1853                         return ret;
1854
1855                 /* NCS5   -> OE_N  */
1856                 select_peripheral(PIOE, (1 << 22), PERIPH_A, 0);
1857                 hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_CF1_ENABLE);
1858                 break;
1859         default:
1860                 return -EINVAL;
1861         }
1862
1863         if (!common_pins_initialized) {
1864                 pin_mask  = (1 << 19);  /* CFCE1  -> CS0_N */
1865                 pin_mask |= (1 << 20);  /* CFCE2  -> CS1_N */
1866                 pin_mask |= (1 << 23);  /* CFRNW  -> DIR   */
1867                 pin_mask |= (1 << 24);  /* NWAIT  <- IORDY */
1868
1869                 select_peripheral(PIOE, pin_mask, PERIPH_A, 0);
1870
1871                 common_pins_initialized = true;
1872         }
1873
1874         select_peripheral(PIOB, extint_pin, PERIPH_A, AT32_GPIOF_DEGLITCH);
1875
1876         pdev->resource[1].start = EIM_IRQ_BASE + extint;
1877         pdev->resource[1].end = pdev->resource[1].start;
1878
1879         return 0;
1880 }
1881
1882 struct platform_device *__init
1883 at32_add_device_ide(unsigned int id, unsigned int extint,
1884                     struct ide_platform_data *data)
1885 {
1886         struct platform_device *pdev;
1887
1888         pdev = platform_device_alloc("at32_ide", id);
1889         if (!pdev)
1890                 goto fail;
1891
1892         if (platform_device_add_data(pdev, data,
1893                                 sizeof(struct ide_platform_data)))
1894                 goto fail;
1895
1896         if (at32_init_ide_or_cf(pdev, data->cs, extint))
1897                 goto fail;
1898
1899         platform_device_add(pdev);
1900         return pdev;
1901
1902 fail:
1903         platform_device_put(pdev);
1904         return NULL;
1905 }
1906
1907 struct platform_device *__init
1908 at32_add_device_cf(unsigned int id, unsigned int extint,
1909                     struct cf_platform_data *data)
1910 {
1911         struct platform_device *pdev;
1912
1913         pdev = platform_device_alloc("at32_cf", id);
1914         if (!pdev)
1915                 goto fail;
1916
1917         if (platform_device_add_data(pdev, data,
1918                                 sizeof(struct cf_platform_data)))
1919                 goto fail;
1920
1921         if (at32_init_ide_or_cf(pdev, data->cs, extint))
1922                 goto fail;
1923
1924         if (gpio_is_valid(data->detect_pin))
1925                 at32_select_gpio(data->detect_pin, AT32_GPIOF_DEGLITCH);
1926         if (gpio_is_valid(data->reset_pin))
1927                 at32_select_gpio(data->reset_pin, 0);
1928         if (gpio_is_valid(data->vcc_pin))
1929                 at32_select_gpio(data->vcc_pin, 0);
1930         /* READY is used as extint, so we can't select it as gpio */
1931
1932         platform_device_add(pdev);
1933         return pdev;
1934
1935 fail:
1936         platform_device_put(pdev);
1937         return NULL;
1938 }
1939 #endif
1940
1941 /* --------------------------------------------------------------------
1942  * NAND Flash / SmartMedia
1943  * -------------------------------------------------------------------- */
1944 static struct resource smc_cs3_resource[] __initdata = {
1945         {
1946                 .start  = 0x0c000000,
1947                 .end    = 0x0fffffff,
1948                 .flags  = IORESOURCE_MEM,
1949         }, {
1950                 .start  = 0xfff03c00,
1951                 .end    = 0xfff03fff,
1952                 .flags  = IORESOURCE_MEM,
1953         },
1954 };
1955
1956 struct platform_device *__init
1957 at32_add_device_nand(unsigned int id, struct atmel_nand_data *data)
1958 {
1959         struct platform_device *pdev;
1960
1961         if (id != 0 || !data)
1962                 return NULL;
1963
1964         pdev = platform_device_alloc("atmel_nand", id);
1965         if (!pdev)
1966                 goto fail;
1967
1968         if (platform_device_add_resources(pdev, smc_cs3_resource,
1969                                 ARRAY_SIZE(smc_cs3_resource)))
1970                 goto fail;
1971
1972         if (platform_device_add_data(pdev, data,
1973                                 sizeof(struct atmel_nand_data)))
1974                 goto fail;
1975
1976         hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_NAND_ENABLE);
1977         if (data->enable_pin)
1978                 at32_select_gpio(data->enable_pin,
1979                                 AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
1980         if (data->rdy_pin)
1981                 at32_select_gpio(data->rdy_pin, 0);
1982         if (data->det_pin)
1983                 at32_select_gpio(data->det_pin, 0);
1984
1985         platform_device_add(pdev);
1986         return pdev;
1987
1988 fail:
1989         platform_device_put(pdev);
1990         return NULL;
1991 }
1992
1993 /* --------------------------------------------------------------------
1994  * AC97C
1995  * -------------------------------------------------------------------- */
1996 static struct resource atmel_ac97c0_resource[] __initdata = {
1997         PBMEM(0xfff02800),
1998         IRQ(29),
1999 };
2000 static struct clk atmel_ac97c0_pclk = {
2001         .name           = "pclk",
2002         .parent         = &pbb_clk,
2003         .mode           = pbb_clk_mode,
2004         .get_rate       = pbb_clk_get_rate,
2005         .index          = 10,
2006 };
2007
2008 struct platform_device *__init
2009 at32_add_device_ac97c(unsigned int id, struct ac97c_platform_data *data,
2010                       unsigned int flags)
2011 {
2012         struct platform_device          *pdev;
2013         struct dw_dma_slave             *rx_dws;
2014         struct dw_dma_slave             *tx_dws;
2015         struct ac97c_platform_data      _data;
2016         u32                             pin_mask;
2017
2018         if (id != 0)
2019                 return NULL;
2020
2021         pdev = platform_device_alloc("atmel_ac97c", id);
2022         if (!pdev)
2023                 return NULL;
2024
2025         if (platform_device_add_resources(pdev, atmel_ac97c0_resource,
2026                                 ARRAY_SIZE(atmel_ac97c0_resource)))
2027                 goto out_free_resources;
2028
2029         if (!data) {
2030                 data = &_data;
2031                 memset(data, 0, sizeof(struct ac97c_platform_data));
2032                 data->reset_pin = -ENODEV;
2033         }
2034
2035         rx_dws = &data->rx_dws;
2036         tx_dws = &data->tx_dws;
2037
2038         /* Check if DMA slave interface for capture should be configured. */
2039         if (flags & AC97C_CAPTURE) {
2040                 rx_dws->dma_dev = &dw_dmac0_device.dev;
2041                 rx_dws->reg_width = DW_DMA_SLAVE_WIDTH_16BIT;
2042                 rx_dws->cfg_hi = DWC_CFGH_SRC_PER(3);
2043                 rx_dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL);
2044         }
2045
2046         /* Check if DMA slave interface for playback should be configured. */
2047         if (flags & AC97C_PLAYBACK) {
2048                 tx_dws->dma_dev = &dw_dmac0_device.dev;
2049                 tx_dws->reg_width = DW_DMA_SLAVE_WIDTH_16BIT;
2050                 tx_dws->cfg_hi = DWC_CFGH_DST_PER(4);
2051                 tx_dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL);
2052         }
2053
2054         if (platform_device_add_data(pdev, data,
2055                                 sizeof(struct ac97c_platform_data)))
2056                 goto out_free_resources;
2057
2058         /* SDO | SYNC | SCLK | SDI */
2059         pin_mask = (1 << 20) | (1 << 21) | (1 << 22) | (1 << 23);
2060
2061         select_peripheral(PIOB, pin_mask, PERIPH_B, 0);
2062
2063         if (gpio_is_valid(data->reset_pin))
2064                 at32_select_gpio(data->reset_pin, AT32_GPIOF_OUTPUT
2065                                 | AT32_GPIOF_HIGH);
2066
2067         atmel_ac97c0_pclk.dev = &pdev->dev;
2068
2069         platform_device_add(pdev);
2070         return pdev;
2071
2072 out_free_resources:
2073         platform_device_put(pdev);
2074         return NULL;
2075 }
2076
2077 /* --------------------------------------------------------------------
2078  * ABDAC
2079  * -------------------------------------------------------------------- */
2080 static struct resource abdac0_resource[] __initdata = {
2081         PBMEM(0xfff02000),
2082         IRQ(27),
2083 };
2084 static struct clk abdac0_pclk = {
2085         .name           = "pclk",
2086         .parent         = &pbb_clk,
2087         .mode           = pbb_clk_mode,
2088         .get_rate       = pbb_clk_get_rate,
2089         .index          = 8,
2090 };
2091 static struct clk abdac0_sample_clk = {
2092         .name           = "sample_clk",
2093         .mode           = genclk_mode,
2094         .get_rate       = genclk_get_rate,
2095         .set_rate       = genclk_set_rate,
2096         .set_parent     = genclk_set_parent,
2097         .index          = 6,
2098 };
2099
2100 struct platform_device *__init
2101 at32_add_device_abdac(unsigned int id, struct atmel_abdac_pdata *data)
2102 {
2103         struct platform_device  *pdev;
2104         struct dw_dma_slave     *dws;
2105         u32                     pin_mask;
2106
2107         if (id != 0 || !data)
2108                 return NULL;
2109
2110         pdev = platform_device_alloc("atmel_abdac", id);
2111         if (!pdev)
2112                 return NULL;
2113
2114         if (platform_device_add_resources(pdev, abdac0_resource,
2115                                 ARRAY_SIZE(abdac0_resource)))
2116                 goto out_free_resources;
2117
2118         dws = &data->dws;
2119
2120         dws->dma_dev = &dw_dmac0_device.dev;
2121         dws->reg_width = DW_DMA_SLAVE_WIDTH_32BIT;
2122         dws->cfg_hi = DWC_CFGH_DST_PER(2);
2123         dws->cfg_lo &= ~(DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL);
2124
2125         if (platform_device_add_data(pdev, data,
2126                                 sizeof(struct atmel_abdac_pdata)))
2127                 goto out_free_resources;
2128
2129         pin_mask  = (1 << 20) | (1 << 22);      /* DATA1 & DATAN1 */
2130         pin_mask |= (1 << 21) | (1 << 23);      /* DATA0 & DATAN0 */
2131
2132         select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
2133
2134         abdac0_pclk.dev = &pdev->dev;
2135         abdac0_sample_clk.dev = &pdev->dev;
2136
2137         platform_device_add(pdev);
2138         return pdev;
2139
2140 out_free_resources:
2141         platform_device_put(pdev);
2142         return NULL;
2143 }
2144
2145 /* --------------------------------------------------------------------
2146  *  GCLK
2147  * -------------------------------------------------------------------- */
2148 static struct clk gclk0 = {
2149         .name           = "gclk0",
2150         .mode           = genclk_mode,
2151         .get_rate       = genclk_get_rate,
2152         .set_rate       = genclk_set_rate,
2153         .set_parent     = genclk_set_parent,
2154         .index          = 0,
2155 };
2156 static struct clk gclk1 = {
2157         .name           = "gclk1",
2158         .mode           = genclk_mode,
2159         .get_rate       = genclk_get_rate,
2160         .set_rate       = genclk_set_rate,
2161         .set_parent     = genclk_set_parent,
2162         .index          = 1,
2163 };
2164 static struct clk gclk2 = {
2165         .name           = "gclk2",
2166         .mode           = genclk_mode,
2167         .get_rate       = genclk_get_rate,
2168         .set_rate       = genclk_set_rate,
2169         .set_parent     = genclk_set_parent,
2170         .index          = 2,
2171 };
2172 static struct clk gclk3 = {
2173         .name           = "gclk3",
2174         .mode           = genclk_mode,
2175         .get_rate       = genclk_get_rate,
2176         .set_rate       = genclk_set_rate,
2177         .set_parent     = genclk_set_parent,
2178         .index          = 3,
2179 };
2180 static struct clk gclk4 = {
2181         .name           = "gclk4",
2182         .mode           = genclk_mode,
2183         .get_rate       = genclk_get_rate,
2184         .set_rate       = genclk_set_rate,
2185         .set_parent     = genclk_set_parent,
2186         .index          = 4,
2187 };
2188
2189 static __initdata struct clk *init_clocks[] = {
2190         &osc32k,
2191         &osc0,
2192         &osc1,
2193         &pll0,
2194         &pll1,
2195         &cpu_clk,
2196         &hsb_clk,
2197         &pba_clk,
2198         &pbb_clk,
2199         &at32_pm_pclk,
2200         &at32_intc0_pclk,
2201         &at32_hmatrix_clk,
2202         &ebi_clk,
2203         &hramc_clk,
2204         &sdramc_clk,
2205         &smc0_pclk,
2206         &smc0_mck,
2207         &pdc_hclk,
2208         &pdc_pclk,
2209         &dw_dmac0_hclk,
2210         &pico_clk,
2211         &pio0_mck,
2212         &pio1_mck,
2213         &pio2_mck,
2214         &pio3_mck,
2215         &pio4_mck,
2216         &at32_tcb0_t0_clk,
2217         &at32_tcb1_t0_clk,
2218         &atmel_psif0_pclk,
2219         &atmel_psif1_pclk,
2220         &atmel_usart0_usart,
2221         &atmel_usart1_usart,
2222         &atmel_usart2_usart,
2223         &atmel_usart3_usart,
2224         &atmel_pwm0_mck,
2225 #if defined(CONFIG_CPU_AT32AP7000)
2226         &macb0_hclk,
2227         &macb0_pclk,
2228         &macb1_hclk,
2229         &macb1_pclk,
2230 #endif
2231         &atmel_spi0_spi_clk,
2232         &atmel_spi1_spi_clk,
2233         &atmel_twi0_pclk,
2234         &atmel_mci0_pclk,
2235 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
2236         &atmel_lcdfb0_hck1,
2237         &atmel_lcdfb0_pixclk,
2238 #endif
2239         &ssc0_pclk,
2240         &ssc1_pclk,
2241         &ssc2_pclk,
2242         &usba0_hclk,
2243         &usba0_pclk,
2244         &atmel_ac97c0_pclk,
2245         &abdac0_pclk,
2246         &abdac0_sample_clk,
2247         &gclk0,
2248         &gclk1,
2249         &gclk2,
2250         &gclk3,
2251         &gclk4,
2252 };
2253
2254 void __init setup_platform(void)
2255 {
2256         u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
2257         int i;
2258
2259         if (pm_readl(MCCTRL) & PM_BIT(PLLSEL)) {
2260                 main_clock = &pll0;
2261                 cpu_clk.parent = &pll0;
2262         } else {
2263                 main_clock = &osc0;
2264                 cpu_clk.parent = &osc0;
2265         }
2266
2267         if (pm_readl(PLL0) & PM_BIT(PLLOSC))
2268                 pll0.parent = &osc1;
2269         if (pm_readl(PLL1) & PM_BIT(PLLOSC))
2270                 pll1.parent = &osc1;
2271
2272         genclk_init_parent(&gclk0);
2273         genclk_init_parent(&gclk1);
2274         genclk_init_parent(&gclk2);
2275         genclk_init_parent(&gclk3);
2276         genclk_init_parent(&gclk4);
2277 #if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
2278         genclk_init_parent(&atmel_lcdfb0_pixclk);
2279 #endif
2280         genclk_init_parent(&abdac0_sample_clk);
2281
2282         /*
2283          * Build initial dynamic clock list by registering all clocks
2284          * from the array.
2285          * At the same time, turn on all clocks that have at least one
2286          * user already, and turn off everything else. We only do this
2287          * for module clocks, and even though it isn't particularly
2288          * pretty to  check the address of the mode function, it should
2289          * do the trick...
2290          */
2291         for (i = 0; i < ARRAY_SIZE(init_clocks); i++) {
2292                 struct clk *clk = init_clocks[i];
2293
2294                 /* first, register clock */
2295                 at32_clk_register(clk);
2296
2297                 if (clk->users == 0)
2298                         continue;
2299
2300                 if (clk->mode == &cpu_clk_mode)
2301                         cpu_mask |= 1 << clk->index;
2302                 else if (clk->mode == &hsb_clk_mode)
2303                         hsb_mask |= 1 << clk->index;
2304                 else if (clk->mode == &pba_clk_mode)
2305                         pba_mask |= 1 << clk->index;
2306                 else if (clk->mode == &pbb_clk_mode)
2307                         pbb_mask |= 1 << clk->index;
2308         }
2309
2310         pm_writel(CPU_MASK, cpu_mask);
2311         pm_writel(HSB_MASK, hsb_mask);
2312         pm_writel(PBA_MASK, pba_mask);
2313         pm_writel(PBB_MASK, pbb_mask);
2314
2315         /* Initialize the port muxes */
2316         at32_init_pio(&pio0_device);
2317         at32_init_pio(&pio1_device);
2318         at32_init_pio(&pio2_device);
2319         at32_init_pio(&pio3_device);
2320         at32_init_pio(&pio4_device);
2321 }
2322
2323 struct gen_pool *sram_pool;
2324
2325 static int __init sram_init(void)
2326 {
2327         struct gen_pool *pool;
2328
2329         /* 1KiB granularity */
2330         pool = gen_pool_create(10, -1);
2331         if (!pool)
2332                 goto fail;
2333
2334         if (gen_pool_add(pool, 0x24000000, 0x8000, -1))
2335                 goto err_pool_add;
2336
2337         sram_pool = pool;
2338         return 0;
2339
2340 err_pool_add:
2341         gen_pool_destroy(pool);
2342 fail:
2343         pr_err("Failed to create SRAM pool\n");
2344         return -ENOMEM;
2345 }
2346 core_initcall(sram_init);