2 * Copyright (C) 2012,2013 - ARM Ltd
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 * Derived from arch/arm/kvm/coproc.c:
6 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
7 * Authors: Rusty Russell <rusty@rustcorp.com.au>
8 * Christoffer Dall <c.dall@virtualopensystems.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License, version 2, as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
24 #include <linux/kvm_host.h>
25 #include <linux/uaccess.h>
26 #include <asm/kvm_arm.h>
27 #include <asm/kvm_host.h>
28 #include <asm/kvm_emulate.h>
29 #include <asm/kvm_coproc.h>
30 #include <asm/kvm_mmu.h>
31 #include <asm/cacheflush.h>
32 #include <asm/cputype.h>
33 #include <asm/debug-monitors.h>
34 #include <trace/events/kvm.h>
39 * All of this file is extremly similar to the ARM coproc.c, but the
40 * types are different. My gut feeling is that it should be pretty
41 * easy to merge, but that would be an ABI breakage -- again. VFP
42 * would also need to be abstracted.
44 * For AArch32, we only take care of what is being trapped. Anything
45 * that has to do with init and userspace access has to go via the
49 /* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */
50 static u32 cache_levels;
52 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
55 /* Which cache CCSIDR represents depends on CSSELR value. */
56 static u32 get_ccsidr(u32 csselr)
60 /* Make sure noone else changes CSSELR during this! */
62 /* Put value into CSSELR */
63 asm volatile("msr csselr_el1, %x0" : : "r" (csselr));
65 /* Read result out of CCSIDR */
66 asm volatile("mrs %0, ccsidr_el1" : "=r" (ccsidr));
73 * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized).
75 static bool access_dcsw(struct kvm_vcpu *vcpu,
76 const struct sys_reg_params *p,
77 const struct sys_reg_desc *r)
80 return read_from_write_only(vcpu, p);
82 kvm_set_way_flush(vcpu);
87 * Generic accessor for VM registers. Only called as long as HCR_TVM
88 * is set. If the guest enables the MMU, we stop trapping the VM
89 * sys_regs and leave it in complete control of the caches.
91 static bool access_vm_reg(struct kvm_vcpu *vcpu,
92 const struct sys_reg_params *p,
93 const struct sys_reg_desc *r)
96 bool was_enabled = vcpu_has_cache_enabled(vcpu);
100 val = *vcpu_reg(vcpu, p->Rt);
101 if (!p->is_aarch32) {
102 vcpu_sys_reg(vcpu, r->reg) = val;
105 vcpu_cp15_64_high(vcpu, r->reg) = val >> 32;
106 vcpu_cp15_64_low(vcpu, r->reg) = val & 0xffffffffUL;
109 kvm_toggle_cache(vcpu, was_enabled);
113 static bool trap_raz_wi(struct kvm_vcpu *vcpu,
114 const struct sys_reg_params *p,
115 const struct sys_reg_desc *r)
118 return ignore_write(vcpu, p);
120 return read_zero(vcpu, p);
123 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu,
124 const struct sys_reg_params *p,
125 const struct sys_reg_desc *r)
128 return ignore_write(vcpu, p);
130 *vcpu_reg(vcpu, p->Rt) = (1 << 3);
135 static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu,
136 const struct sys_reg_params *p,
137 const struct sys_reg_desc *r)
140 return ignore_write(vcpu, p);
143 asm volatile("mrs %0, dbgauthstatus_el1" : "=r" (val));
144 *vcpu_reg(vcpu, p->Rt) = val;
150 * We want to avoid world-switching all the DBG registers all the
153 * - If we've touched any debug register, it is likely that we're
154 * going to touch more of them. It then makes sense to disable the
155 * traps and start doing the save/restore dance
156 * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is
157 * then mandatory to save/restore the registers, as the guest
160 * For this, we use a DIRTY bit, indicating the guest has modified the
161 * debug registers, used as follow:
164 * - If the dirty bit is set (because we're coming back from trapping),
165 * disable the traps, save host registers, restore guest registers.
166 * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set),
167 * set the dirty bit, disable the traps, save host registers,
168 * restore guest registers.
169 * - Otherwise, enable the traps
172 * - If the dirty bit is set, save guest registers, restore host
173 * registers and clear the dirty bit. This ensure that the host can
174 * now use the debug registers.
176 static bool trap_debug_regs(struct kvm_vcpu *vcpu,
177 const struct sys_reg_params *p,
178 const struct sys_reg_desc *r)
181 vcpu_sys_reg(vcpu, r->reg) = *vcpu_reg(vcpu, p->Rt);
182 vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
184 *vcpu_reg(vcpu, p->Rt) = vcpu_sys_reg(vcpu, r->reg);
190 static void reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
194 asm volatile("mrs %0, amair_el1\n" : "=r" (amair));
195 vcpu_sys_reg(vcpu, AMAIR_EL1) = amair;
198 static void reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
201 * Simply map the vcpu_id into the Aff0 field of the MPIDR.
203 vcpu_sys_reg(vcpu, MPIDR_EL1) = (1UL << 31) | (vcpu->vcpu_id & 0xff);
206 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
207 #define DBG_BCR_BVR_WCR_WVR_EL1(n) \
209 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b100), \
210 trap_debug_regs, reset_val, (DBGBVR0_EL1 + (n)), 0 }, \
212 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b101), \
213 trap_debug_regs, reset_val, (DBGBCR0_EL1 + (n)), 0 }, \
215 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b110), \
216 trap_debug_regs, reset_val, (DBGWVR0_EL1 + (n)), 0 }, \
218 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm((n)), Op2(0b111), \
219 trap_debug_regs, reset_val, (DBGWCR0_EL1 + (n)), 0 }
222 * Architected system registers.
223 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
225 * We could trap ID_DFR0 and tell the guest we don't support performance
226 * monitoring. Unfortunately the patch to make the kernel check ID_DFR0 was
227 * NAKed, so it will read the PMCR anyway.
229 * Therefore we tell the guest we have 0 counters. Unfortunately, we
230 * must always support PMCCNTR (the cycle counter): we just RAZ/WI for
231 * all PM registers, which doesn't crash the guest kernel at least.
233 * Debug handling: We do trap most, if not all debug related system
234 * registers. The implementation is good enough to ensure that a guest
235 * can use these with minimal performance degradation. The drawback is
236 * that we don't implement any of the external debug, none of the
237 * OSlock protocol. This should be revisited if we ever encounter a
238 * more demanding guest...
240 static const struct sys_reg_desc sys_reg_descs[] = {
242 { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b0110), Op2(0b010),
245 { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b1010), Op2(0b010),
248 { Op0(0b01), Op1(0b000), CRn(0b0111), CRm(0b1110), Op2(0b010),
251 DBG_BCR_BVR_WCR_WVR_EL1(0),
252 DBG_BCR_BVR_WCR_WVR_EL1(1),
254 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b000),
255 trap_debug_regs, reset_val, MDCCINT_EL1, 0 },
257 { Op0(0b10), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b010),
258 trap_debug_regs, reset_val, MDSCR_EL1, 0 },
259 DBG_BCR_BVR_WCR_WVR_EL1(2),
260 DBG_BCR_BVR_WCR_WVR_EL1(3),
261 DBG_BCR_BVR_WCR_WVR_EL1(4),
262 DBG_BCR_BVR_WCR_WVR_EL1(5),
263 DBG_BCR_BVR_WCR_WVR_EL1(6),
264 DBG_BCR_BVR_WCR_WVR_EL1(7),
265 DBG_BCR_BVR_WCR_WVR_EL1(8),
266 DBG_BCR_BVR_WCR_WVR_EL1(9),
267 DBG_BCR_BVR_WCR_WVR_EL1(10),
268 DBG_BCR_BVR_WCR_WVR_EL1(11),
269 DBG_BCR_BVR_WCR_WVR_EL1(12),
270 DBG_BCR_BVR_WCR_WVR_EL1(13),
271 DBG_BCR_BVR_WCR_WVR_EL1(14),
272 DBG_BCR_BVR_WCR_WVR_EL1(15),
275 { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b000),
278 { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b100),
281 { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0001), Op2(0b100),
284 { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0011), Op2(0b100),
287 { Op0(0b10), Op1(0b000), CRn(0b0001), CRm(0b0100), Op2(0b100),
289 /* DBGCLAIMSET_EL1 */
290 { Op0(0b10), Op1(0b000), CRn(0b0111), CRm(0b1000), Op2(0b110),
292 /* DBGCLAIMCLR_EL1 */
293 { Op0(0b10), Op1(0b000), CRn(0b0111), CRm(0b1001), Op2(0b110),
295 /* DBGAUTHSTATUS_EL1 */
296 { Op0(0b10), Op1(0b000), CRn(0b0111), CRm(0b1110), Op2(0b110),
297 trap_dbgauthstatus_el1 },
300 { Op0(0b10), Op1(0b010), CRn(0b0000), CRm(0b0000), Op2(0b000),
301 NULL, reset_val, TEECR32_EL1, 0 },
303 { Op0(0b10), Op1(0b010), CRn(0b0001), CRm(0b0000), Op2(0b000),
304 NULL, reset_val, TEEHBR32_EL1, 0 },
307 { Op0(0b10), Op1(0b011), CRn(0b0000), CRm(0b0001), Op2(0b000),
310 { Op0(0b10), Op1(0b011), CRn(0b0000), CRm(0b0100), Op2(0b000),
312 /* DBGDTR[TR]X_EL0 */
313 { Op0(0b10), Op1(0b011), CRn(0b0000), CRm(0b0101), Op2(0b000),
317 { Op0(0b10), Op1(0b100), CRn(0b0000), CRm(0b0111), Op2(0b000),
318 NULL, reset_val, DBGVCR32_EL2, 0 },
321 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b101),
322 NULL, reset_mpidr, MPIDR_EL1 },
324 { Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b000),
325 access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 },
327 { Op0(0b11), Op1(0b000), CRn(0b0001), CRm(0b0000), Op2(0b010),
328 NULL, reset_val, CPACR_EL1, 0 },
330 { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b000),
331 access_vm_reg, reset_unknown, TTBR0_EL1 },
333 { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b001),
334 access_vm_reg, reset_unknown, TTBR1_EL1 },
336 { Op0(0b11), Op1(0b000), CRn(0b0010), CRm(0b0000), Op2(0b010),
337 access_vm_reg, reset_val, TCR_EL1, 0 },
340 { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0001), Op2(0b000),
341 access_vm_reg, reset_unknown, AFSR0_EL1 },
343 { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0001), Op2(0b001),
344 access_vm_reg, reset_unknown, AFSR1_EL1 },
346 { Op0(0b11), Op1(0b000), CRn(0b0101), CRm(0b0010), Op2(0b000),
347 access_vm_reg, reset_unknown, ESR_EL1 },
349 { Op0(0b11), Op1(0b000), CRn(0b0110), CRm(0b0000), Op2(0b000),
350 access_vm_reg, reset_unknown, FAR_EL1 },
352 { Op0(0b11), Op1(0b000), CRn(0b0111), CRm(0b0100), Op2(0b000),
353 NULL, reset_unknown, PAR_EL1 },
356 { Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b001),
359 { Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b010),
363 { Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0010), Op2(0b000),
364 access_vm_reg, reset_unknown, MAIR_EL1 },
366 { Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0011), Op2(0b000),
367 access_vm_reg, reset_amair_el1, AMAIR_EL1 },
370 { Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b0000), Op2(0b000),
371 NULL, reset_val, VBAR_EL1, 0 },
374 { Op0(0b11), Op1(0b000), CRn(0b1100), CRm(0b1100), Op2(0b101),
378 { Op0(0b11), Op1(0b000), CRn(0b1101), CRm(0b0000), Op2(0b001),
379 access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 },
381 { Op0(0b11), Op1(0b000), CRn(0b1101), CRm(0b0000), Op2(0b100),
382 NULL, reset_unknown, TPIDR_EL1 },
385 { Op0(0b11), Op1(0b000), CRn(0b1110), CRm(0b0001), Op2(0b000),
386 NULL, reset_val, CNTKCTL_EL1, 0},
389 { Op0(0b11), Op1(0b010), CRn(0b0000), CRm(0b0000), Op2(0b000),
390 NULL, reset_unknown, CSSELR_EL1 },
393 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b000),
396 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b001),
399 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b010),
402 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b011),
405 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b100),
408 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b101),
411 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b110),
414 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b111),
417 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b000),
420 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b001),
423 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b010),
426 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b000),
429 { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b011),
433 { Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b010),
434 NULL, reset_unknown, TPIDR_EL0 },
436 { Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b0000), Op2(0b011),
437 NULL, reset_unknown, TPIDRRO_EL0 },
440 { Op0(0b11), Op1(0b100), CRn(0b0011), CRm(0b0000), Op2(0b000),
441 NULL, reset_unknown, DACR32_EL2 },
443 { Op0(0b11), Op1(0b100), CRn(0b0101), CRm(0b0000), Op2(0b001),
444 NULL, reset_unknown, IFSR32_EL2 },
446 { Op0(0b11), Op1(0b100), CRn(0b0101), CRm(0b0011), Op2(0b000),
447 NULL, reset_val, FPEXC32_EL2, 0x70 },
450 static bool trap_dbgidr(struct kvm_vcpu *vcpu,
451 const struct sys_reg_params *p,
452 const struct sys_reg_desc *r)
455 return ignore_write(vcpu, p);
457 u64 dfr = read_cpuid(ID_AA64DFR0_EL1);
458 u64 pfr = read_cpuid(ID_AA64PFR0_EL1);
459 u32 el3 = !!((pfr >> 12) & 0xf);
461 *vcpu_reg(vcpu, p->Rt) = ((((dfr >> 20) & 0xf) << 28) |
462 (((dfr >> 12) & 0xf) << 24) |
463 (((dfr >> 28) & 0xf) << 20) |
464 (6 << 16) | (el3 << 14) | (el3 << 12));
469 static bool trap_debug32(struct kvm_vcpu *vcpu,
470 const struct sys_reg_params *p,
471 const struct sys_reg_desc *r)
474 vcpu_cp14(vcpu, r->reg) = *vcpu_reg(vcpu, p->Rt);
475 vcpu->arch.debug_flags |= KVM_ARM64_DEBUG_DIRTY;
477 *vcpu_reg(vcpu, p->Rt) = vcpu_cp14(vcpu, r->reg);
483 #define DBG_BCR_BVR_WCR_WVR(n) \
485 { Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_debug32, \
486 NULL, (cp14_DBGBVR0 + (n) * 2) }, \
488 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_debug32, \
489 NULL, (cp14_DBGBCR0 + (n) * 2) }, \
491 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_debug32, \
492 NULL, (cp14_DBGWVR0 + (n) * 2) }, \
494 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_debug32, \
495 NULL, (cp14_DBGWCR0 + (n) * 2) }
498 { Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_debug32, \
499 NULL, cp14_DBGBXVR0 + n * 2 }
502 * Trapped cp14 registers. We generally ignore most of the external
503 * debug, on the principle that they don't really make sense to a
504 * guest. Revisit this one day, whould this principle change.
506 static const struct sys_reg_desc cp14_regs[] = {
508 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgidr },
510 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi },
512 DBG_BCR_BVR_WCR_WVR(0),
514 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi },
515 DBG_BCR_BVR_WCR_WVR(1),
517 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug32 },
519 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug32 },
520 DBG_BCR_BVR_WCR_WVR(2),
522 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi },
524 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi },
525 DBG_BCR_BVR_WCR_WVR(3),
526 DBG_BCR_BVR_WCR_WVR(4),
527 DBG_BCR_BVR_WCR_WVR(5),
529 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi },
531 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi },
532 DBG_BCR_BVR_WCR_WVR(6),
534 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug32 },
535 DBG_BCR_BVR_WCR_WVR(7),
536 DBG_BCR_BVR_WCR_WVR(8),
537 DBG_BCR_BVR_WCR_WVR(9),
538 DBG_BCR_BVR_WCR_WVR(10),
539 DBG_BCR_BVR_WCR_WVR(11),
540 DBG_BCR_BVR_WCR_WVR(12),
541 DBG_BCR_BVR_WCR_WVR(13),
542 DBG_BCR_BVR_WCR_WVR(14),
543 DBG_BCR_BVR_WCR_WVR(15),
545 /* DBGDRAR (32bit) */
546 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi },
550 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_raz_wi },
553 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1 },
557 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi },
560 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi },
573 /* DBGDSAR (32bit) */
574 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi },
577 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi },
579 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi },
581 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi },
583 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi },
585 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi },
587 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 },
590 /* Trapped cp14 64bit registers */
591 static const struct sys_reg_desc cp14_64_regs[] = {
592 /* DBGDRAR (64bit) */
593 { Op1( 0), CRm( 1), .access = trap_raz_wi },
595 /* DBGDSAR (64bit) */
596 { Op1( 0), CRm( 2), .access = trap_raz_wi },
600 * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding,
601 * depending on the way they are accessed (as a 32bit or a 64bit
604 static const struct sys_reg_desc cp15_regs[] = {
605 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, c1_SCTLR },
606 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
607 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, c2_TTBR1 },
608 { Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, c2_TTBCR },
609 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, c3_DACR },
610 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, c5_DFSR },
611 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, c5_IFSR },
612 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, c5_ADFSR },
613 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, c5_AIFSR },
614 { Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, c6_DFAR },
615 { Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, c6_IFAR },
618 * DC{C,I,CI}SW operations:
620 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw },
621 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw },
622 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw },
625 { Op1( 0), CRn( 9), CRm(12), Op2( 0), trap_raz_wi },
626 { Op1( 0), CRn( 9), CRm(12), Op2( 1), trap_raz_wi },
627 { Op1( 0), CRn( 9), CRm(12), Op2( 2), trap_raz_wi },
628 { Op1( 0), CRn( 9), CRm(12), Op2( 3), trap_raz_wi },
629 { Op1( 0), CRn( 9), CRm(12), Op2( 5), trap_raz_wi },
630 { Op1( 0), CRn( 9), CRm(12), Op2( 6), trap_raz_wi },
631 { Op1( 0), CRn( 9), CRm(12), Op2( 7), trap_raz_wi },
632 { Op1( 0), CRn( 9), CRm(13), Op2( 0), trap_raz_wi },
633 { Op1( 0), CRn( 9), CRm(13), Op2( 1), trap_raz_wi },
634 { Op1( 0), CRn( 9), CRm(13), Op2( 2), trap_raz_wi },
635 { Op1( 0), CRn( 9), CRm(14), Op2( 0), trap_raz_wi },
636 { Op1( 0), CRn( 9), CRm(14), Op2( 1), trap_raz_wi },
637 { Op1( 0), CRn( 9), CRm(14), Op2( 2), trap_raz_wi },
639 { Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, c10_PRRR },
640 { Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, c10_NMRR },
641 { Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, c10_AMAIR0 },
642 { Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, c10_AMAIR1 },
645 { Op1( 0), CRn(12), CRm(12), Op2( 5), trap_raz_wi },
647 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, c13_CID },
650 static const struct sys_reg_desc cp15_64_regs[] = {
651 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR0 },
652 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, c2_TTBR1 },
655 /* Target specific emulation tables */
656 static struct kvm_sys_reg_target_table *target_tables[KVM_ARM_NUM_TARGETS];
658 void kvm_register_target_sys_reg_table(unsigned int target,
659 struct kvm_sys_reg_target_table *table)
661 target_tables[target] = table;
664 /* Get specific register table for this target. */
665 static const struct sys_reg_desc *get_target_table(unsigned target,
669 struct kvm_sys_reg_target_table *table;
671 table = target_tables[target];
673 *num = table->table64.num;
674 return table->table64.table;
676 *num = table->table32.num;
677 return table->table32.table;
681 static const struct sys_reg_desc *find_reg(const struct sys_reg_params *params,
682 const struct sys_reg_desc table[],
687 for (i = 0; i < num; i++) {
688 const struct sys_reg_desc *r = &table[i];
690 if (params->Op0 != r->Op0)
692 if (params->Op1 != r->Op1)
694 if (params->CRn != r->CRn)
696 if (params->CRm != r->CRm)
698 if (params->Op2 != r->Op2)
706 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu, struct kvm_run *run)
708 kvm_inject_undefined(vcpu);
713 * emulate_cp -- tries to match a sys_reg access in a handling table, and
714 * call the corresponding trap handler.
716 * @params: pointer to the descriptor of the access
717 * @table: array of trap descriptors
718 * @num: size of the trap descriptor array
720 * Return 0 if the access has been handled, and -1 if not.
722 static int emulate_cp(struct kvm_vcpu *vcpu,
723 const struct sys_reg_params *params,
724 const struct sys_reg_desc *table,
727 const struct sys_reg_desc *r;
730 return -1; /* Not handled */
732 r = find_reg(params, table, num);
736 * Not having an accessor means that we have
737 * configured a trap that we don't know how to
738 * handle. This certainly qualifies as a gross bug
739 * that should be fixed right away.
743 if (likely(r->access(vcpu, params, r))) {
744 /* Skip instruction, since it was emulated */
745 kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
756 static void unhandled_cp_access(struct kvm_vcpu *vcpu,
757 struct sys_reg_params *params)
759 u8 hsr_ec = kvm_vcpu_trap_get_class(vcpu);
763 case ESR_EL2_EC_CP15_32:
764 case ESR_EL2_EC_CP15_64:
767 case ESR_EL2_EC_CP14_MR:
768 case ESR_EL2_EC_CP14_64:
775 kvm_err("Unsupported guest CP%d access at: %08lx\n",
777 print_sys_reg_instr(params);
778 kvm_inject_undefined(vcpu);
782 * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP15 access
783 * @vcpu: The VCPU pointer
784 * @run: The kvm_run struct
786 static int kvm_handle_cp_64(struct kvm_vcpu *vcpu,
787 const struct sys_reg_desc *global,
789 const struct sys_reg_desc *target_specific,
792 struct sys_reg_params params;
793 u32 hsr = kvm_vcpu_get_hsr(vcpu);
794 int Rt2 = (hsr >> 10) & 0xf;
796 params.is_aarch32 = true;
797 params.is_32bit = false;
798 params.CRm = (hsr >> 1) & 0xf;
799 params.Rt = (hsr >> 5) & 0xf;
800 params.is_write = ((hsr & 1) == 0);
803 params.Op1 = (hsr >> 16) & 0xf;
808 * Massive hack here. Store Rt2 in the top 32bits so we only
809 * have one register to deal with. As we use the same trap
810 * backends between AArch32 and AArch64, we get away with it.
812 if (params.is_write) {
813 u64 val = *vcpu_reg(vcpu, params.Rt);
815 val |= *vcpu_reg(vcpu, Rt2) << 32;
816 *vcpu_reg(vcpu, params.Rt) = val;
819 if (!emulate_cp(vcpu, ¶ms, target_specific, nr_specific))
821 if (!emulate_cp(vcpu, ¶ms, global, nr_global))
824 unhandled_cp_access(vcpu, ¶ms);
827 /* Do the opposite hack for the read side */
828 if (!params.is_write) {
829 u64 val = *vcpu_reg(vcpu, params.Rt);
831 *vcpu_reg(vcpu, Rt2) = val;
838 * kvm_handle_cp15_32 -- handles a mrc/mcr trap on a guest CP15 access
839 * @vcpu: The VCPU pointer
840 * @run: The kvm_run struct
842 static int kvm_handle_cp_32(struct kvm_vcpu *vcpu,
843 const struct sys_reg_desc *global,
845 const struct sys_reg_desc *target_specific,
848 struct sys_reg_params params;
849 u32 hsr = kvm_vcpu_get_hsr(vcpu);
851 params.is_aarch32 = true;
852 params.is_32bit = true;
853 params.CRm = (hsr >> 1) & 0xf;
854 params.Rt = (hsr >> 5) & 0xf;
855 params.is_write = ((hsr & 1) == 0);
856 params.CRn = (hsr >> 10) & 0xf;
858 params.Op1 = (hsr >> 14) & 0x7;
859 params.Op2 = (hsr >> 17) & 0x7;
861 if (!emulate_cp(vcpu, ¶ms, target_specific, nr_specific))
863 if (!emulate_cp(vcpu, ¶ms, global, nr_global))
866 unhandled_cp_access(vcpu, ¶ms);
870 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
872 const struct sys_reg_desc *target_specific;
875 target_specific = get_target_table(vcpu->arch.target, false, &num);
876 return kvm_handle_cp_64(vcpu,
877 cp15_64_regs, ARRAY_SIZE(cp15_64_regs),
878 target_specific, num);
881 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
883 const struct sys_reg_desc *target_specific;
886 target_specific = get_target_table(vcpu->arch.target, false, &num);
887 return kvm_handle_cp_32(vcpu,
888 cp15_regs, ARRAY_SIZE(cp15_regs),
889 target_specific, num);
892 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
894 return kvm_handle_cp_64(vcpu,
895 cp14_64_regs, ARRAY_SIZE(cp14_64_regs),
899 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
901 return kvm_handle_cp_32(vcpu,
902 cp14_regs, ARRAY_SIZE(cp14_regs),
906 static int emulate_sys_reg(struct kvm_vcpu *vcpu,
907 const struct sys_reg_params *params)
910 const struct sys_reg_desc *table, *r;
912 table = get_target_table(vcpu->arch.target, true, &num);
914 /* Search target-specific then generic table. */
915 r = find_reg(params, table, num);
917 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
921 * Not having an accessor means that we have
922 * configured a trap that we don't know how to
923 * handle. This certainly qualifies as a gross bug
924 * that should be fixed right away.
928 if (likely(r->access(vcpu, params, r))) {
929 /* Skip instruction, since it was emulated */
930 kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
933 /* If access function fails, it should complain. */
935 kvm_err("Unsupported guest sys_reg access at: %lx\n",
937 print_sys_reg_instr(params);
939 kvm_inject_undefined(vcpu);
943 static void reset_sys_reg_descs(struct kvm_vcpu *vcpu,
944 const struct sys_reg_desc *table, size_t num)
948 for (i = 0; i < num; i++)
950 table[i].reset(vcpu, &table[i]);
954 * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access
955 * @vcpu: The VCPU pointer
956 * @run: The kvm_run struct
958 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu, struct kvm_run *run)
960 struct sys_reg_params params;
961 unsigned long esr = kvm_vcpu_get_hsr(vcpu);
963 params.is_aarch32 = false;
964 params.is_32bit = false;
965 params.Op0 = (esr >> 20) & 3;
966 params.Op1 = (esr >> 14) & 0x7;
967 params.CRn = (esr >> 10) & 0xf;
968 params.CRm = (esr >> 1) & 0xf;
969 params.Op2 = (esr >> 17) & 0x7;
970 params.Rt = (esr >> 5) & 0x1f;
971 params.is_write = !(esr & 1);
973 return emulate_sys_reg(vcpu, ¶ms);
976 /******************************************************************************
978 *****************************************************************************/
980 static bool index_to_params(u64 id, struct sys_reg_params *params)
982 switch (id & KVM_REG_SIZE_MASK) {
983 case KVM_REG_SIZE_U64:
984 /* Any unused index bits means it's not valid. */
985 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
986 | KVM_REG_ARM_COPROC_MASK
987 | KVM_REG_ARM64_SYSREG_OP0_MASK
988 | KVM_REG_ARM64_SYSREG_OP1_MASK
989 | KVM_REG_ARM64_SYSREG_CRN_MASK
990 | KVM_REG_ARM64_SYSREG_CRM_MASK
991 | KVM_REG_ARM64_SYSREG_OP2_MASK))
993 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK)
994 >> KVM_REG_ARM64_SYSREG_OP0_SHIFT);
995 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK)
996 >> KVM_REG_ARM64_SYSREG_OP1_SHIFT);
997 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK)
998 >> KVM_REG_ARM64_SYSREG_CRN_SHIFT);
999 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK)
1000 >> KVM_REG_ARM64_SYSREG_CRM_SHIFT);
1001 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK)
1002 >> KVM_REG_ARM64_SYSREG_OP2_SHIFT);
1009 /* Decode an index value, and find the sys_reg_desc entry. */
1010 static const struct sys_reg_desc *index_to_sys_reg_desc(struct kvm_vcpu *vcpu,
1014 const struct sys_reg_desc *table, *r;
1015 struct sys_reg_params params;
1017 /* We only do sys_reg for now. */
1018 if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG)
1021 if (!index_to_params(id, ¶ms))
1024 table = get_target_table(vcpu->arch.target, true, &num);
1025 r = find_reg(¶ms, table, num);
1027 r = find_reg(¶ms, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
1029 /* Not saved in the sys_reg array? */
1037 * These are the invariant sys_reg registers: we let the guest see the
1038 * host versions of these, so they're part of the guest state.
1040 * A future CPU may provide a mechanism to present different values to
1041 * the guest, or a future kvm may trap them.
1044 #define FUNCTION_INVARIANT(reg) \
1045 static void get_##reg(struct kvm_vcpu *v, \
1046 const struct sys_reg_desc *r) \
1050 asm volatile("mrs %0, " __stringify(reg) "\n" \
1052 ((struct sys_reg_desc *)r)->val = val; \
1055 FUNCTION_INVARIANT(midr_el1)
1056 FUNCTION_INVARIANT(ctr_el0)
1057 FUNCTION_INVARIANT(revidr_el1)
1058 FUNCTION_INVARIANT(id_pfr0_el1)
1059 FUNCTION_INVARIANT(id_pfr1_el1)
1060 FUNCTION_INVARIANT(id_dfr0_el1)
1061 FUNCTION_INVARIANT(id_afr0_el1)
1062 FUNCTION_INVARIANT(id_mmfr0_el1)
1063 FUNCTION_INVARIANT(id_mmfr1_el1)
1064 FUNCTION_INVARIANT(id_mmfr2_el1)
1065 FUNCTION_INVARIANT(id_mmfr3_el1)
1066 FUNCTION_INVARIANT(id_isar0_el1)
1067 FUNCTION_INVARIANT(id_isar1_el1)
1068 FUNCTION_INVARIANT(id_isar2_el1)
1069 FUNCTION_INVARIANT(id_isar3_el1)
1070 FUNCTION_INVARIANT(id_isar4_el1)
1071 FUNCTION_INVARIANT(id_isar5_el1)
1072 FUNCTION_INVARIANT(clidr_el1)
1073 FUNCTION_INVARIANT(aidr_el1)
1075 /* ->val is filled in by kvm_sys_reg_table_init() */
1076 static struct sys_reg_desc invariant_sys_regs[] = {
1077 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b000),
1078 NULL, get_midr_el1 },
1079 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0000), Op2(0b110),
1080 NULL, get_revidr_el1 },
1081 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b000),
1082 NULL, get_id_pfr0_el1 },
1083 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b001),
1084 NULL, get_id_pfr1_el1 },
1085 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b010),
1086 NULL, get_id_dfr0_el1 },
1087 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b011),
1088 NULL, get_id_afr0_el1 },
1089 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b100),
1090 NULL, get_id_mmfr0_el1 },
1091 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b101),
1092 NULL, get_id_mmfr1_el1 },
1093 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b110),
1094 NULL, get_id_mmfr2_el1 },
1095 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0001), Op2(0b111),
1096 NULL, get_id_mmfr3_el1 },
1097 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b000),
1098 NULL, get_id_isar0_el1 },
1099 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b001),
1100 NULL, get_id_isar1_el1 },
1101 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b010),
1102 NULL, get_id_isar2_el1 },
1103 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b011),
1104 NULL, get_id_isar3_el1 },
1105 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b100),
1106 NULL, get_id_isar4_el1 },
1107 { Op0(0b11), Op1(0b000), CRn(0b0000), CRm(0b0010), Op2(0b101),
1108 NULL, get_id_isar5_el1 },
1109 { Op0(0b11), Op1(0b001), CRn(0b0000), CRm(0b0000), Op2(0b001),
1110 NULL, get_clidr_el1 },
1111 { Op0(0b11), Op1(0b001), CRn(0b0000), CRm(0b0000), Op2(0b111),
1112 NULL, get_aidr_el1 },
1113 { Op0(0b11), Op1(0b011), CRn(0b0000), CRm(0b0000), Op2(0b001),
1114 NULL, get_ctr_el0 },
1117 static int reg_from_user(u64 *val, const void __user *uaddr, u64 id)
1119 if (copy_from_user(val, uaddr, KVM_REG_SIZE(id)) != 0)
1124 static int reg_to_user(void __user *uaddr, const u64 *val, u64 id)
1126 if (copy_to_user(uaddr, val, KVM_REG_SIZE(id)) != 0)
1131 static int get_invariant_sys_reg(u64 id, void __user *uaddr)
1133 struct sys_reg_params params;
1134 const struct sys_reg_desc *r;
1136 if (!index_to_params(id, ¶ms))
1139 r = find_reg(¶ms, invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs));
1143 return reg_to_user(uaddr, &r->val, id);
1146 static int set_invariant_sys_reg(u64 id, void __user *uaddr)
1148 struct sys_reg_params params;
1149 const struct sys_reg_desc *r;
1151 u64 val = 0; /* Make sure high bits are 0 for 32-bit regs */
1153 if (!index_to_params(id, ¶ms))
1155 r = find_reg(¶ms, invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs));
1159 err = reg_from_user(&val, uaddr, id);
1163 /* This is what we mean by invariant: you can't change it. */
1170 static bool is_valid_cache(u32 val)
1174 if (val >= CSSELR_MAX)
1177 /* Bottom bit is Instruction or Data bit. Next 3 bits are level. */
1179 ctype = (cache_levels >> (level * 3)) & 7;
1182 case 0: /* No cache */
1184 case 1: /* Instruction cache only */
1186 case 2: /* Data cache only */
1187 case 4: /* Unified cache */
1189 case 3: /* Separate instruction and data caches */
1191 default: /* Reserved: we can't know instruction or data. */
1196 static int demux_c15_get(u64 id, void __user *uaddr)
1199 u32 __user *uval = uaddr;
1201 /* Fail if we have unknown bits set. */
1202 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
1203 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
1206 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
1207 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
1208 if (KVM_REG_SIZE(id) != 4)
1210 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
1211 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
1212 if (!is_valid_cache(val))
1215 return put_user(get_ccsidr(val), uval);
1221 static int demux_c15_set(u64 id, void __user *uaddr)
1224 u32 __user *uval = uaddr;
1226 /* Fail if we have unknown bits set. */
1227 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
1228 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
1231 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
1232 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
1233 if (KVM_REG_SIZE(id) != 4)
1235 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
1236 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
1237 if (!is_valid_cache(val))
1240 if (get_user(newval, uval))
1243 /* This is also invariant: you can't change it. */
1244 if (newval != get_ccsidr(val))
1252 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
1254 const struct sys_reg_desc *r;
1255 void __user *uaddr = (void __user *)(unsigned long)reg->addr;
1257 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
1258 return demux_c15_get(reg->id, uaddr);
1260 if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
1263 r = index_to_sys_reg_desc(vcpu, reg->id);
1265 return get_invariant_sys_reg(reg->id, uaddr);
1267 return reg_to_user(uaddr, &vcpu_sys_reg(vcpu, r->reg), reg->id);
1270 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
1272 const struct sys_reg_desc *r;
1273 void __user *uaddr = (void __user *)(unsigned long)reg->addr;
1275 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
1276 return demux_c15_set(reg->id, uaddr);
1278 if (KVM_REG_SIZE(reg->id) != sizeof(__u64))
1281 r = index_to_sys_reg_desc(vcpu, reg->id);
1283 return set_invariant_sys_reg(reg->id, uaddr);
1285 return reg_from_user(&vcpu_sys_reg(vcpu, r->reg), uaddr, reg->id);
1288 static unsigned int num_demux_regs(void)
1290 unsigned int i, count = 0;
1292 for (i = 0; i < CSSELR_MAX; i++)
1293 if (is_valid_cache(i))
1299 static int write_demux_regids(u64 __user *uindices)
1301 u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX;
1304 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR;
1305 for (i = 0; i < CSSELR_MAX; i++) {
1306 if (!is_valid_cache(i))
1308 if (put_user(val | i, uindices))
1315 static u64 sys_reg_to_index(const struct sys_reg_desc *reg)
1317 return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 |
1318 KVM_REG_ARM64_SYSREG |
1319 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) |
1320 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) |
1321 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) |
1322 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) |
1323 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT));
1326 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind)
1331 if (put_user(sys_reg_to_index(reg), *uind))
1338 /* Assumed ordered tables, see kvm_sys_reg_table_init. */
1339 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind)
1341 const struct sys_reg_desc *i1, *i2, *end1, *end2;
1342 unsigned int total = 0;
1345 /* We check for duplicates here, to allow arch-specific overrides. */
1346 i1 = get_target_table(vcpu->arch.target, true, &num);
1349 end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs);
1351 BUG_ON(i1 == end1 || i2 == end2);
1353 /* Walk carefully, as both tables may refer to the same register. */
1355 int cmp = cmp_sys_reg(i1, i2);
1356 /* target-specific overrides generic entry. */
1358 /* Ignore registers we trap but don't save. */
1360 if (!copy_reg_to_user(i1, &uind))
1365 /* Ignore registers we trap but don't save. */
1367 if (!copy_reg_to_user(i2, &uind))
1373 if (cmp <= 0 && ++i1 == end1)
1375 if (cmp >= 0 && ++i2 == end2)
1381 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu)
1383 return ARRAY_SIZE(invariant_sys_regs)
1385 + walk_sys_regs(vcpu, (u64 __user *)NULL);
1388 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
1393 /* Then give them all the invariant registers' indices. */
1394 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) {
1395 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices))
1400 err = walk_sys_regs(vcpu, uindices);
1405 return write_demux_regids(uindices);
1408 static int check_sysreg_table(const struct sys_reg_desc *table, unsigned int n)
1412 for (i = 1; i < n; i++) {
1413 if (cmp_sys_reg(&table[i-1], &table[i]) >= 0) {
1414 kvm_err("sys_reg table %p out of order (%d)\n", table, i - 1);
1422 void kvm_sys_reg_table_init(void)
1425 struct sys_reg_desc clidr;
1427 /* Make sure tables are unique and in order. */
1428 BUG_ON(check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs)));
1429 BUG_ON(check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs)));
1430 BUG_ON(check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs)));
1431 BUG_ON(check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs)));
1432 BUG_ON(check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs)));
1433 BUG_ON(check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs)));
1435 /* We abuse the reset function to overwrite the table itself. */
1436 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++)
1437 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]);
1440 * CLIDR format is awkward, so clean it up. See ARM B4.1.20:
1442 * If software reads the Cache Type fields from Ctype1
1443 * upwards, once it has seen a value of 0b000, no caches
1444 * exist at further-out levels of the hierarchy. So, for
1445 * example, if Ctype3 is the first Cache Type field with a
1446 * value of 0b000, the values of Ctype4 to Ctype7 must be
1449 get_clidr_el1(NULL, &clidr); /* Ugly... */
1450 cache_levels = clidr.val;
1451 for (i = 0; i < 7; i++)
1452 if (((cache_levels >> (i*3)) & 7) == 0)
1454 /* Clear all higher bits. */
1455 cache_levels &= (1 << (i*3))-1;
1459 * kvm_reset_sys_regs - sets system registers to reset value
1460 * @vcpu: The VCPU pointer
1462 * This function finds the right table above and sets the registers on the
1463 * virtual CPU struct to their architecturally defined reset values.
1465 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu)
1468 const struct sys_reg_desc *table;
1470 /* Catch someone adding a register without putting in reset entry. */
1471 memset(&vcpu->arch.ctxt.sys_regs, 0x42, sizeof(vcpu->arch.ctxt.sys_regs));
1473 /* Generic chip reset first (so target could override). */
1474 reset_sys_reg_descs(vcpu, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
1476 table = get_target_table(vcpu->arch.target, true, &num);
1477 reset_sys_reg_descs(vcpu, table, num);
1479 for (num = 1; num < NR_SYS_REGS; num++)
1480 if (vcpu_sys_reg(vcpu, num) == 0x4242424242424242)
1481 panic("Didn't reset vcpu_sys_reg(%zi)", num);