arch/arm/probes/decode-arm.c

   1 /*
   2  *
   3  * arch/arm/probes/decode-arm.c
   4  *
   5  * Some code moved here from arch/arm/kernel/kprobes-arm.c
   6  *
   7  * Copyright (C) 2006, 2007 Motorola Inc.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/module.h>
  21 #include <linux/stddef.h>
  22 #include <linux/ptrace.h>
  23
  24 #include "decode.h"
  25 #include "decode-arm.h"
  26
  27 #define sign_extend(x, signbit) ((x) | (0 - ((x) & (1 << (signbit)))))
  28
  29 #define branch_displacement(insn) sign_extend(((insn) & 0xffffff) << 2, 25)
  30
  31 /*
  32  * To avoid the complications of mimicing single-stepping on a
  33  * processor without a Next-PC or a single-step mode, and to
  34  * avoid having to deal with the side-effects of boosting, we
  35  * simulate or emulate (almost) all ARM instructions.
  36  *
  37  * "Simulation" is where the instruction's behavior is duplicated in
  38  * C code.  "Emulation" is where the original instruction is rewritten
  39  * and executed, often by altering its registers.
  40  *
  41  * By having all behavior of the kprobe'd instruction completed before
  42  * returning from the kprobe_handler(), all locks (scheduler and
  43  * interrupt) can safely be released.  There is no need for secondary
  44  * breakpoints, no race with MP or preemptable kernels, nor having to
  45  * clean up resources counts at a later time impacting overall system
  46  * performance.  By rewriting the instruction, only the minimum registers
  47  * need to be loaded and saved back optimizing performance.
  48  *
  49  * Calling the insnslot_*_rwflags version of a function doesn't hurt
  50  * anything even when the CPSR flags aren't updated by the
  51  * instruction.  It's just a little slower in return for saving
  52  * a little space by not having a duplicate function that doesn't
  53  * update the flags.  (The same optimization can be said for
  54  * instructions that do or don't perform register writeback)
  55  * Also, instructions can either read the flags, only write the
  56  * flags, or read and write the flags.  To save combinations
  57  * rather than for sheer performance, flag functions just assume
  58  * read and write of flags.
  59  */
  60
  61 void __kprobes simulate_bbl(probes_opcode_t insn,
  62                 struct arch_probes_insn *asi, struct pt_regs *regs)
  63 {
  64         long iaddr = (long) regs->ARM_pc - 4;
  65         int disp  = branch_displacement(insn);
  66
  67         if (insn & (1 << 24))
  68                 regs->ARM_lr = iaddr + 4;
  69
  70         regs->ARM_pc = iaddr + 8 + disp;
  71 }
  72
  73 void __kprobes simulate_blx1(probes_opcode_t insn,
  74                 struct arch_probes_insn *asi, struct pt_regs *regs)
  75 {
  76         long iaddr = (long) regs->ARM_pc - 4;
  77         int disp = branch_displacement(insn);
  78
  79         regs->ARM_lr = iaddr + 4;
  80         regs->ARM_pc = iaddr + 8 + disp + ((insn >> 23) & 0x2);
  81         regs->ARM_cpsr |= PSR_T_BIT;
  82 }
  83
  84 void __kprobes simulate_blx2bx(probes_opcode_t insn,
  85                 struct arch_probes_insn *asi, struct pt_regs *regs)
  86 {
  87         int rm = insn & 0xf;
  88         long rmv = regs->uregs[rm];
  89
  90         if (insn & (1 << 5))
  91                 regs->ARM_lr = (long) regs->ARM_pc;
  92
  93         regs->ARM_pc = rmv & ~0x1;
  94         regs->ARM_cpsr &= ~PSR_T_BIT;
  95         if (rmv & 0x1)
  96                 regs->ARM_cpsr |= PSR_T_BIT;
  97 }
  98
  99 void __kprobes simulate_mrs(probes_opcode_t insn,
 100                 struct arch_probes_insn *asi, struct pt_regs *regs)
 101 {
 102         int rd = (insn >> 12) & 0xf;
 103         unsigned long mask = 0xf8ff03df; /* Mask out execution state */
 104         regs->uregs[rd] = regs->ARM_cpsr & mask;
 105 }
 106
 107 void __kprobes simulate_mov_ipsp(probes_opcode_t insn,
 108                 struct arch_probes_insn *asi, struct pt_regs *regs)
 109 {
 110         regs->uregs[12] = regs->uregs[13];
 111 }
 112
 113 /*
 114  * For the instruction masking and comparisons in all the "space_*"
 115  * functions below, Do _not_ rearrange the order of tests unless
 116  * you're very, very sure of what you are doing.  For the sake of
 117  * efficiency, the masks for some tests sometimes assume other test
 118  * have been done prior to them so the number of patterns to test
 119  * for an instruction set can be as broad as possible to reduce the
 120  * number of tests needed.
 121  */
 122
 123 static const union decode_item arm_1111_table[] = {
 124         /* Unconditional instructions                                   */
 125
 126         /* memory hint          1111 0100 x001 xxxx xxxx xxxx xxxx xxxx */
 127         /* PLDI (immediate)     1111 0100 x101 xxxx xxxx xxxx xxxx xxxx */
 128         /* PLDW (immediate)     1111 0101 x001 xxxx xxxx xxxx xxxx xxxx */
 129         /* PLD (immediate)      1111 0101 x101 xxxx xxxx xxxx xxxx xxxx */
 130         DECODE_SIMULATE (0xfe300000, 0xf4100000, PROBES_PRELOAD_IMM),
 131
 132         /* memory hint          1111 0110 x001 xxxx xxxx xxxx xxx0 xxxx */
 133         /* PLDI (register)      1111 0110 x101 xxxx xxxx xxxx xxx0 xxxx */
 134         /* PLDW (register)      1111 0111 x001 xxxx xxxx xxxx xxx0 xxxx */
 135         /* PLD (register)       1111 0111 x101 xxxx xxxx xxxx xxx0 xxxx */
 136         DECODE_SIMULATE (0xfe300010, 0xf6100000, PROBES_PRELOAD_REG),
 137
 138         /* BLX (immediate)      1111 101x xxxx xxxx xxxx xxxx xxxx xxxx */
 139         DECODE_SIMULATE (0xfe000000, 0xfa000000, PROBES_BRANCH_IMM),
 140
 141         /* CPS                  1111 0001 0000 xxx0 xxxx xxxx xx0x xxxx */
 142         /* SETEND               1111 0001 0000 0001 xxxx xxxx 0000 xxxx */
 143         /* SRS                  1111 100x x1x0 xxxx xxxx xxxx xxxx xxxx */
 144         /* RFE                  1111 100x x0x1 xxxx xxxx xxxx xxxx xxxx */
 145
 146         /* Coprocessor instructions... */
 147         /* MCRR2                1111 1100 0100 xxxx xxxx xxxx xxxx xxxx */
 148         /* MRRC2                1111 1100 0101 xxxx xxxx xxxx xxxx xxxx */
 149         /* LDC2                 1111 110x xxx1 xxxx xxxx xxxx xxxx xxxx */
 150         /* STC2                 1111 110x xxx0 xxxx xxxx xxxx xxxx xxxx */
 151         /* CDP2                 1111 1110 xxxx xxxx xxxx xxxx xxx0 xxxx */
 152         /* MCR2                 1111 1110 xxx0 xxxx xxxx xxxx xxx1 xxxx */
 153         /* MRC2                 1111 1110 xxx1 xxxx xxxx xxxx xxx1 xxxx */
 154
 155         /* Other unallocated instructions...                            */
 156         DECODE_END
 157 };
 158
 159 static const union decode_item arm_cccc_0001_0xx0____0xxx_table[] = {
 160         /* Miscellaneous instructions                                   */
 161
 162         /* MRS cpsr             cccc 0001 0000 xxxx xxxx xxxx 0000 xxxx */
 163         DECODE_SIMULATEX(0x0ff000f0, 0x01000000, PROBES_MRS,
 164                                                  REGS(0, NOPC, 0, 0, 0)),
 165
 166         /* BX                   cccc 0001 0010 xxxx xxxx xxxx 0001 xxxx */
 167         DECODE_SIMULATE (0x0ff000f0, 0x01200010, PROBES_BRANCH_REG),
 168
 169         /* BLX (register)       cccc 0001 0010 xxxx xxxx xxxx 0011 xxxx */
 170         DECODE_SIMULATEX(0x0ff000f0, 0x01200030, PROBES_BRANCH_REG,
 171                                                  REGS(0, 0, 0, 0, NOPC)),
 172
 173         /* CLZ                  cccc 0001 0110 xxxx xxxx xxxx 0001 xxxx */
 174         DECODE_EMULATEX (0x0ff000f0, 0x01600010, PROBES_CLZ,
 175                                                  REGS(0, NOPC, 0, 0, NOPC)),
 176
 177         /* QADD                 cccc 0001 0000 xxxx xxxx xxxx 0101 xxxx */
 178         /* QSUB                 cccc 0001 0010 xxxx xxxx xxxx 0101 xxxx */
 179         /* QDADD                cccc 0001 0100 xxxx xxxx xxxx 0101 xxxx */
 180         /* QDSUB                cccc 0001 0110 xxxx xxxx xxxx 0101 xxxx */
 181         DECODE_EMULATEX (0x0f9000f0, 0x01000050, PROBES_SATURATING_ARITHMETIC,
 182                                                  REGS(NOPC, NOPC, 0, 0, NOPC)),
 183
 184         /* BXJ                  cccc 0001 0010 xxxx xxxx xxxx 0010 xxxx */
 185         /* MSR                  cccc 0001 0x10 xxxx xxxx xxxx 0000 xxxx */
 186         /* MRS spsr             cccc 0001 0100 xxxx xxxx xxxx 0000 xxxx */
 187         /* BKPT                 1110 0001 0010 xxxx xxxx xxxx 0111 xxxx */
 188         /* SMC                  cccc 0001 0110 xxxx xxxx xxxx 0111 xxxx */
 189         /* And unallocated instructions...                              */
 190         DECODE_END
 191 };
 192
 193 static const union decode_item arm_cccc_0001_0xx0____1xx0_table[] = {
 194         /* Halfword multiply and multiply-accumulate                    */
 195
 196         /* SMLALxy              cccc 0001 0100 xxxx xxxx xxxx 1xx0 xxxx */
 197         DECODE_EMULATEX (0x0ff00090, 0x01400080, PROBES_MUL1,
 198                                                  REGS(NOPC, NOPC, NOPC, 0, NOPC)),
 199
 200         /* SMULWy               cccc 0001 0010 xxxx xxxx xxxx 1x10 xxxx */
 201         DECODE_OR       (0x0ff000b0, 0x012000a0),
 202         /* SMULxy               cccc 0001 0110 xxxx xxxx xxxx 1xx0 xxxx */
 203         DECODE_EMULATEX (0x0ff00090, 0x01600080, PROBES_MUL2,
 204                                                  REGS(NOPC, 0, NOPC, 0, NOPC)),
 205
 206         /* SMLAxy               cccc 0001 0000 xxxx xxxx xxxx 1xx0 xxxx */
 207         DECODE_OR       (0x0ff00090, 0x01000080),
 208         /* SMLAWy               cccc 0001 0010 xxxx xxxx xxxx 1x00 xxxx */
 209         DECODE_EMULATEX (0x0ff000b0, 0x01200080, PROBES_MUL2,
 210                                                  REGS(NOPC, NOPC, NOPC, 0, NOPC)),
 211
 212         DECODE_END
 213 };
 214
 215 static const union decode_item arm_cccc_0000_____1001_table[] = {
 216         /* Multiply and multiply-accumulate                             */
 217
 218         /* MUL                  cccc 0000 0000 xxxx xxxx xxxx 1001 xxxx */
 219         /* MULS                 cccc 0000 0001 xxxx xxxx xxxx 1001 xxxx */
 220         DECODE_EMULATEX (0x0fe000f0, 0x00000090, PROBES_MUL2,
 221                                                  REGS(NOPC, 0, NOPC, 0, NOPC)),
 222
 223         /* MLA                  cccc 0000 0010 xxxx xxxx xxxx 1001 xxxx */
 224         /* MLAS                 cccc 0000 0011 xxxx xxxx xxxx 1001 xxxx */
 225         DECODE_OR       (0x0fe000f0, 0x00200090),
 226         /* MLS                  cccc 0000 0110 xxxx xxxx xxxx 1001 xxxx */
 227         DECODE_EMULATEX (0x0ff000f0, 0x00600090, PROBES_MUL2,
 228                                                  REGS(NOPC, NOPC, NOPC, 0, NOPC)),
 229
 230         /* UMAAL                cccc 0000 0100 xxxx xxxx xxxx 1001 xxxx */
 231         DECODE_OR       (0x0ff000f0, 0x00400090),
 232         /* UMULL                cccc 0000 1000 xxxx xxxx xxxx 1001 xxxx */
 233         /* UMULLS               cccc 0000 1001 xxxx xxxx xxxx 1001 xxxx */
 234         /* UMLAL                cccc 0000 1010 xxxx xxxx xxxx 1001 xxxx */
 235         /* UMLALS               cccc 0000 1011 xxxx xxxx xxxx 1001 xxxx */
 236         /* SMULL                cccc 0000 1100 xxxx xxxx xxxx 1001 xxxx */
 237         /* SMULLS               cccc 0000 1101 xxxx xxxx xxxx 1001 xxxx */
 238         /* SMLAL                cccc 0000 1110 xxxx xxxx xxxx 1001 xxxx */
 239         /* SMLALS               cccc 0000 1111 xxxx xxxx xxxx 1001 xxxx */
 240         DECODE_EMULATEX (0x0f8000f0, 0x00800090, PROBES_MUL1,
 241                                                  REGS(NOPC, NOPC, NOPC, 0, NOPC)),
 242
 243         DECODE_END
 244 };
 245
 246 static const union decode_item arm_cccc_0001_____1001_table[] = {
 247         /* Synchronization primitives                                   */
 248
 249 #if __LINUX_ARM_ARCH__ < 6
 250         /* Deprecated on ARMv6 and may be UNDEFINED on v7               */
 251         /* SMP/SWPB             cccc 0001 0x00 xxxx xxxx xxxx 1001 xxxx */
 252         DECODE_EMULATEX (0x0fb000f0, 0x01000090, PROBES_SWP,
 253                                                  REGS(NOPC, NOPC, 0, 0, NOPC)),
 254 #endif
 255         /* LDREX/STREX{,D,B,H}  cccc 0001 1xxx xxxx xxxx xxxx 1001 xxxx */
 256         /* And unallocated instructions...                              */
 257         DECODE_END
 258 };
 259
 260 static const union decode_item arm_cccc_000x_____1xx1_table[] = {
 261         /* Extra load/store instructions                                */
 262
 263         /* STRHT                cccc 0000 xx10 xxxx xxxx xxxx 1011 xxxx */
 264         /* ???                  cccc 0000 xx10 xxxx xxxx xxxx 11x1 xxxx */
 265         /* LDRHT                cccc 0000 xx11 xxxx xxxx xxxx 1011 xxxx */
 266         /* LDRSBT               cccc 0000 xx11 xxxx xxxx xxxx 1101 xxxx */
 267         /* LDRSHT               cccc 0000 xx11 xxxx xxxx xxxx 1111 xxxx */
 268         DECODE_REJECT   (0x0f200090, 0x00200090),
 269
 270         /* LDRD/STRD lr,pc,{... cccc 000x x0x0 xxxx 111x xxxx 1101 xxxx */
 271         DECODE_REJECT   (0x0e10e0d0, 0x0000e0d0),
 272
 273         /* LDRD (register)      cccc 000x x0x0 xxxx xxxx xxxx 1101 xxxx */
 274         /* STRD (register)      cccc 000x x0x0 xxxx xxxx xxxx 1111 xxxx */
 275         DECODE_EMULATEX (0x0e5000d0, 0x000000d0, PROBES_LDRSTRD,
 276                                                  REGS(NOPCWB, NOPCX, 0, 0, NOPC)),
 277
 278         /* LDRD (immediate)     cccc 000x x1x0 xxxx xxxx xxxx 1101 xxxx */
 279         /* STRD (immediate)     cccc 000x x1x0 xxxx xxxx xxxx 1111 xxxx */
 280         DECODE_EMULATEX (0x0e5000d0, 0x004000d0, PROBES_LDRSTRD,
 281                                                  REGS(NOPCWB, NOPCX, 0, 0, 0)),
 282
 283         /* STRH (register)      cccc 000x x0x0 xxxx xxxx xxxx 1011 xxxx */
 284         DECODE_EMULATEX (0x0e5000f0, 0x000000b0, PROBES_STORE_EXTRA,
 285                                                  REGS(NOPCWB, NOPC, 0, 0, NOPC)),
 286
 287         /* LDRH (register)      cccc 000x x0x1 xxxx xxxx xxxx 1011 xxxx */
 288         /* LDRSB (register)     cccc 000x x0x1 xxxx xxxx xxxx 1101 xxxx */
 289         /* LDRSH (register)     cccc 000x x0x1 xxxx xxxx xxxx 1111 xxxx */
 290         DECODE_EMULATEX (0x0e500090, 0x00100090, PROBES_LOAD_EXTRA,
 291                                                  REGS(NOPCWB, NOPC, 0, 0, NOPC)),
 292
 293         /* STRH (immediate)     cccc 000x x1x0 xxxx xxxx xxxx 1011 xxxx */
 294         DECODE_EMULATEX (0x0e5000f0, 0x004000b0, PROBES_STORE_EXTRA,
 295                                                  REGS(NOPCWB, NOPC, 0, 0, 0)),
 296
 297         /* LDRH (immediate)     cccc 000x x1x1 xxxx xxxx xxxx 1011 xxxx */
 298         /* LDRSB (immediate)    cccc 000x x1x1 xxxx xxxx xxxx 1101 xxxx */
 299         /* LDRSH (immediate)    cccc 000x x1x1 xxxx xxxx xxxx 1111 xxxx */
 300         DECODE_EMULATEX (0x0e500090, 0x00500090, PROBES_LOAD_EXTRA,
 301                                                  REGS(NOPCWB, NOPC, 0, 0, 0)),
 302
 303         DECODE_END
 304 };
 305
 306 static const union decode_item arm_cccc_000x_table[] = {
 307         /* Data-processing (register)                                   */
 308
 309         /* <op>S PC, ...        cccc 000x xxx1 xxxx 1111 xxxx xxxx xxxx */
 310         DECODE_REJECT   (0x0e10f000, 0x0010f000),
 311
 312         /* MOV IP, SP           1110 0001 1010 0000 1100 0000 0000 1101 */
 313         DECODE_SIMULATE (0xffffffff, 0xe1a0c00d, PROBES_MOV_IP_SP),
 314
 315         /* TST (register)       cccc 0001 0001 xxxx xxxx xxxx xxx0 xxxx */
 316         /* TEQ (register)       cccc 0001 0011 xxxx xxxx xxxx xxx0 xxxx */
 317         /* CMP (register)       cccc 0001 0101 xxxx xxxx xxxx xxx0 xxxx */
 318         /* CMN (register)       cccc 0001 0111 xxxx xxxx xxxx xxx0 xxxx */
 319         DECODE_EMULATEX (0x0f900010, 0x01100000, PROBES_DATA_PROCESSING_REG,
 320                                                  REGS(ANY, 0, 0, 0, ANY)),
 321
 322         /* MOV (register)       cccc 0001 101x xxxx xxxx xxxx xxx0 xxxx */
 323         /* MVN (register)       cccc 0001 111x xxxx xxxx xxxx xxx0 xxxx */
 324         DECODE_EMULATEX (0x0fa00010, 0x01a00000, PROBES_DATA_PROCESSING_REG,
 325                                                  REGS(0, ANY, 0, 0, ANY)),
 326
 327         /* AND (register)       cccc 0000 000x xxxx xxxx xxxx xxx0 xxxx */
 328         /* EOR (register)       cccc 0000 001x xxxx xxxx xxxx xxx0 xxxx */
 329         /* SUB (register)       cccc 0000 010x xxxx xxxx xxxx xxx0 xxxx */
 330         /* RSB (register)       cccc 0000 011x xxxx xxxx xxxx xxx0 xxxx */
 331         /* ADD (register)       cccc 0000 100x xxxx xxxx xxxx xxx0 xxxx */
 332         /* ADC (register)       cccc 0000 101x xxxx xxxx xxxx xxx0 xxxx */
 333         /* SBC (register)       cccc 0000 110x xxxx xxxx xxxx xxx0 xxxx */
 334         /* RSC (register)       cccc 0000 111x xxxx xxxx xxxx xxx0 xxxx */
 335         /* ORR (register)       cccc 0001 100x xxxx xxxx xxxx xxx0 xxxx */
 336         /* BIC (register)       cccc 0001 110x xxxx xxxx xxxx xxx0 xxxx */
 337         DECODE_EMULATEX (0x0e000010, 0x00000000, PROBES_DATA_PROCESSING_REG,
 338                                                  REGS(ANY, ANY, 0, 0, ANY)),
 339
 340         /* TST (reg-shift reg)  cccc 0001 0001 xxxx xxxx xxxx 0xx1 xxxx */
 341         /* TEQ (reg-shift reg)  cccc 0001 0011 xxxx xxxx xxxx 0xx1 xxxx */
 342         /* CMP (reg-shift reg)  cccc 0001 0101 xxxx xxxx xxxx 0xx1 xxxx */
 343         /* CMN (reg-shift reg)  cccc 0001 0111 xxxx xxxx xxxx 0xx1 xxxx */
 344         DECODE_EMULATEX (0x0f900090, 0x01100010, PROBES_DATA_PROCESSING_REG,
 345                                                  REGS(NOPC, 0, NOPC, 0, NOPC)),
 346
 347         /* MOV (reg-shift reg)  cccc 0001 101x xxxx xxxx xxxx 0xx1 xxxx */
 348         /* MVN (reg-shift reg)  cccc 0001 111x xxxx xxxx xxxx 0xx1 xxxx */
 349         DECODE_EMULATEX (0x0fa00090, 0x01a00010, PROBES_DATA_PROCESSING_REG,
 350                                                  REGS(0, NOPC, NOPC, 0, NOPC)),
 351
 352         /* AND (reg-shift reg)  cccc 0000 000x xxxx xxxx xxxx 0xx1 xxxx */
 353         /* EOR (reg-shift reg)  cccc 0000 001x xxxx xxxx xxxx 0xx1 xxxx */
 354         /* SUB (reg-shift reg)  cccc 0000 010x xxxx xxxx xxxx 0xx1 xxxx */
 355         /* RSB (reg-shift reg)  cccc 0000 011x xxxx xxxx xxxx 0xx1 xxxx */
 356         /* ADD (reg-shift reg)  cccc 0000 100x xxxx xxxx xxxx 0xx1 xxxx */
 357         /* ADC (reg-shift reg)  cccc 0000 101x xxxx xxxx xxxx 0xx1 xxxx */
 358         /* SBC (reg-shift reg)  cccc 0000 110x xxxx xxxx xxxx 0xx1 xxxx */
 359         /* RSC (reg-shift reg)  cccc 0000 111x xxxx xxxx xxxx 0xx1 xxxx */
 360         /* ORR (reg-shift reg)  cccc 0001 100x xxxx xxxx xxxx 0xx1 xxxx */
 361         /* BIC (reg-shift reg)  cccc 0001 110x xxxx xxxx xxxx 0xx1 xxxx */
 362         DECODE_EMULATEX (0x0e000090, 0x00000010, PROBES_DATA_PROCESSING_REG,
 363                                                  REGS(NOPC, NOPC, NOPC, 0, NOPC)),
 364
 365         DECODE_END
 366 };
 367
 368 static const union decode_item arm_cccc_001x_table[] = {
 369         /* Data-processing (immediate)                                  */
 370
 371         /* MOVW                 cccc 0011 0000 xxxx xxxx xxxx xxxx xxxx */
 372         /* MOVT                 cccc 0011 0100 xxxx xxxx xxxx xxxx xxxx */
 373         DECODE_EMULATEX (0x0fb00000, 0x03000000, PROBES_MOV_HALFWORD,
 374                                                  REGS(0, NOPC, 0, 0, 0)),
 375
 376         /* YIELD                cccc 0011 0010 0000 xxxx xxxx 0000 0001 */
 377         DECODE_OR       (0x0fff00ff, 0x03200001),
 378         /* SEV                  cccc 0011 0010 0000 xxxx xxxx 0000 0100 */
 379         DECODE_EMULATE  (0x0fff00ff, 0x03200004, PROBES_SEV),
 380         /* NOP                  cccc 0011 0010 0000 xxxx xxxx 0000 0000 */
 381         /* WFE                  cccc 0011 0010 0000 xxxx xxxx 0000 0010 */
 382         /* WFI                  cccc 0011 0010 0000 xxxx xxxx 0000 0011 */
 383         DECODE_SIMULATE (0x0fff00fc, 0x03200000, PROBES_WFE),
 384         /* DBG                  cccc 0011 0010 0000 xxxx xxxx ffff xxxx */
 385         /* unallocated hints    cccc 0011 0010 0000 xxxx xxxx xxxx xxxx */
 386         /* MSR (immediate)      cccc 0011 0x10 xxxx xxxx xxxx xxxx xxxx */
 387         DECODE_REJECT   (0x0fb00000, 0x03200000),
 388
 389         /* <op>S PC, ...        cccc 001x xxx1 xxxx 1111 xxxx xxxx xxxx */
 390         DECODE_REJECT   (0x0e10f000, 0x0210f000),
 391
 392         /* TST (immediate)      cccc 0011 0001 xxxx xxxx xxxx xxxx xxxx */
 393         /* TEQ (immediate)      cccc 0011 0011 xxxx xxxx xxxx xxxx xxxx */
 394         /* CMP (immediate)      cccc 0011 0101 xxxx xxxx xxxx xxxx xxxx */
 395         /* CMN (immediate)      cccc 0011 0111 xxxx xxxx xxxx xxxx xxxx */
 396         DECODE_EMULATEX (0x0f900000, 0x03100000, PROBES_DATA_PROCESSING_IMM,
 397                                                  REGS(ANY, 0, 0, 0, 0)),
 398
 399         /* MOV (immediate)      cccc 0011 101x xxxx xxxx xxxx xxxx xxxx */
 400         /* MVN (immediate)      cccc 0011 111x xxxx xxxx xxxx xxxx xxxx */
 401         DECODE_EMULATEX (0x0fa00000, 0x03a00000, PROBES_DATA_PROCESSING_IMM,
 402                                                  REGS(0, ANY, 0, 0, 0)),
 403
 404         /* AND (immediate)      cccc 0010 000x xxxx xxxx xxxx xxxx xxxx */
 405         /* EOR (immediate)      cccc 0010 001x xxxx xxxx xxxx xxxx xxxx */
 406         /* SUB (immediate)      cccc 0010 010x xxxx xxxx xxxx xxxx xxxx */
 407         /* RSB (immediate)      cccc 0010 011x xxxx xxxx xxxx xxxx xxxx */
 408         /* ADD (immediate)      cccc 0010 100x xxxx xxxx xxxx xxxx xxxx */
 409         /* ADC (immediate)      cccc 0010 101x xxxx xxxx xxxx xxxx xxxx */
 410         /* SBC (immediate)      cccc 0010 110x xxxx xxxx xxxx xxxx xxxx */
 411         /* RSC (immediate)      cccc 0010 111x xxxx xxxx xxxx xxxx xxxx */
 412         /* ORR (immediate)      cccc 0011 100x xxxx xxxx xxxx xxxx xxxx */
 413         /* BIC (immediate)      cccc 0011 110x xxxx xxxx xxxx xxxx xxxx */
 414         DECODE_EMULATEX (0x0e000000, 0x02000000, PROBES_DATA_PROCESSING_IMM,
 415                                                  REGS(ANY, ANY, 0, 0, 0)),
 416
 417         DECODE_END
 418 };
 419
 420 static const union decode_item arm_cccc_0110_____xxx1_table[] = {
 421         /* Media instructions                                           */
 422
 423         /* SEL                  cccc 0110 1000 xxxx xxxx xxxx 1011 xxxx */
 424         DECODE_EMULATEX (0x0ff000f0, 0x068000b0, PROBES_SATURATE,
 425                                                  REGS(NOPC, NOPC, 0, 0, NOPC)),
 426
 427         /* SSAT                 cccc 0110 101x xxxx xxxx xxxx xx01 xxxx */
 428         /* USAT                 cccc 0110 111x xxxx xxxx xxxx xx01 xxxx */
 429         DECODE_OR(0x0fa00030, 0x06a00010),
 430         /* SSAT16               cccc 0110 1010 xxxx xxxx xxxx 0011 xxxx */
 431         /* USAT16               cccc 0110 1110 xxxx xxxx xxxx 0011 xxxx */
 432         DECODE_EMULATEX (0x0fb000f0, 0x06a00030, PROBES_SATURATE,
 433                                                  REGS(0, NOPC, 0, 0, NOPC)),
 434
 435         /* REV                  cccc 0110 1011 xxxx xxxx xxxx 0011 xxxx */
 436         /* REV16                cccc 0110 1011 xxxx xxxx xxxx 1011 xxxx */
 437         /* RBIT                 cccc 0110 1111 xxxx xxxx xxxx 0011 xxxx */
 438         /* REVSH                cccc 0110 1111 xxxx xxxx xxxx 1011 xxxx */
 439         DECODE_EMULATEX (0x0fb00070, 0x06b00030, PROBES_REV,
 440                                                  REGS(0, NOPC, 0, 0, NOPC)),
 441
 442         /* ???                  cccc 0110 0x00 xxxx xxxx xxxx xxx1 xxxx */
 443         DECODE_REJECT   (0x0fb00010, 0x06000010),
 444         /* ???                  cccc 0110 0xxx xxxx xxxx xxxx 1011 xxxx */
 445         DECODE_REJECT   (0x0f8000f0, 0x060000b0),
 446         /* ???                  cccc 0110 0xxx xxxx xxxx xxxx 1101 xxxx */
 447         DECODE_REJECT   (0x0f8000f0, 0x060000d0),
 448         /* SADD16               cccc 0110 0001 xxxx xxxx xxxx 0001 xxxx */
 449         /* SADDSUBX             cccc 0110 0001 xxxx xxxx xxxx 0011 xxxx */
 450         /* SSUBADDX             cccc 0110 0001 xxxx xxxx xxxx 0101 xxxx */
 451         /* SSUB16               cccc 0110 0001 xxxx xxxx xxxx 0111 xxxx */
 452         /* SADD8                cccc 0110 0001 xxxx xxxx xxxx 1001 xxxx */
 453         /* SSUB8                cccc 0110 0001 xxxx xxxx xxxx 1111 xxxx */
 454         /* QADD16               cccc 0110 0010 xxxx xxxx xxxx 0001 xxxx */
 455         /* QADDSUBX             cccc 0110 0010 xxxx xxxx xxxx 0011 xxxx */
 456         /* QSUBADDX             cccc 0110 0010 xxxx xxxx xxxx 0101 xxxx */
 457         /* QSUB16               cccc 0110 0010 xxxx xxxx xxxx 0111 xxxx */
 458         /* QADD8                cccc 0110 0010 xxxx xxxx xxxx 1001 xxxx */
 459         /* QSUB8                cccc 0110 0010 xxxx xxxx xxxx 1111 xxxx */
 460         /* SHADD16              cccc 0110 0011 xxxx xxxx xxxx 0001 xxxx */
 461         /* SHADDSUBX            cccc 0110 0011 xxxx xxxx xxxx 0011 xxxx */
 462         /* SHSUBADDX            cccc 0110 0011 xxxx xxxx xxxx 0101 xxxx */
 463         /* SHSUB16              cccc 0110 0011 xxxx xxxx xxxx 0111 xxxx */
 464         /* SHADD8               cccc 0110 0011 xxxx xxxx xxxx 1001 xxxx */
 465         /* SHSUB8               cccc 0110 0011 xxxx xxxx xxxx 1111 xxxx */
 466         /* UADD16               cccc 0110 0101 xxxx xxxx xxxx 0001 xxxx */
 467         /* UADDSUBX             cccc 0110 0101 xxxx xxxx xxxx 0011 xxxx */
 468         /* USUBADDX             cccc 0110 0101 xxxx xxxx xxxx 0101 xxxx */
 469         /* USUB16               cccc 0110 0101 xxxx xxxx xxxx 0111 xxxx */
 470         /* UADD8                cccc 0110 0101 xxxx xxxx xxxx 1001 xxxx */
 471         /* USUB8                cccc 0110 0101 xxxx xxxx xxxx 1111 xxxx */
 472         /* UQADD16              cccc 0110 0110 xxxx xxxx xxxx 0001 xxxx */
 473         /* UQADDSUBX            cccc 0110 0110 xxxx xxxx xxxx 0011 xxxx */
 474         /* UQSUBADDX            cccc 0110 0110 xxxx xxxx xxxx 0101 xxxx */
 475         /* UQSUB16              cccc 0110 0110 xxxx xxxx xxxx 0111 xxxx */
 476         /* UQADD8               cccc 0110 0110 xxxx xxxx xxxx 1001 xxxx */
 477         /* UQSUB8               cccc 0110 0110 xxxx xxxx xxxx 1111 xxxx */
 478         /* UHADD16              cccc 0110 0111 xxxx xxxx xxxx 0001 xxxx */
 479         /* UHADDSUBX            cccc 0110 0111 xxxx xxxx xxxx 0011 xxxx */
 480         /* UHSUBADDX            cccc 0110 0111 xxxx xxxx xxxx 0101 xxxx */
 481         /* UHSUB16              cccc 0110 0111 xxxx xxxx xxxx 0111 xxxx */
 482         /* UHADD8               cccc 0110 0111 xxxx xxxx xxxx 1001 xxxx */
 483         /* UHSUB8               cccc 0110 0111 xxxx xxxx xxxx 1111 xxxx */
 484         DECODE_EMULATEX (0x0f800010, 0x06000010, PROBES_MMI,
 485                                                  REGS(NOPC, NOPC, 0, 0, NOPC)),
 486
 487         /* PKHBT                cccc 0110 1000 xxxx xxxx xxxx x001 xxxx */
 488         /* PKHTB                cccc 0110 1000 xxxx xxxx xxxx x101 xxxx */
 489         DECODE_EMULATEX (0x0ff00030, 0x06800010, PROBES_PACK,
 490                                                  REGS(NOPC, NOPC, 0, 0, NOPC)),
 491
 492         /* ???                  cccc 0110 1001 xxxx xxxx xxxx 0111 xxxx */
 493         /* ???                  cccc 0110 1101 xxxx xxxx xxxx 0111 xxxx */
 494         DECODE_REJECT   (0x0fb000f0, 0x06900070),
 495
 496         /* SXTB16               cccc 0110 1000 1111 xxxx xxxx 0111 xxxx */
 497         /* SXTB                 cccc 0110 1010 1111 xxxx xxxx 0111 xxxx */
 498         /* SXTH                 cccc 0110 1011 1111 xxxx xxxx 0111 xxxx */
 499         /* UXTB16               cccc 0110 1100 1111 xxxx xxxx 0111 xxxx */
 500         /* UXTB                 cccc 0110 1110 1111 xxxx xxxx 0111 xxxx */
 501         /* UXTH                 cccc 0110 1111 1111 xxxx xxxx 0111 xxxx */
 502         DECODE_EMULATEX (0x0f8f00f0, 0x068f0070, PROBES_EXTEND,
 503                                                  REGS(0, NOPC, 0, 0, NOPC)),
 504
 505         /* SXTAB16              cccc 0110 1000 xxxx xxxx xxxx 0111 xxxx */
 506         /* SXTAB                cccc 0110 1010 xxxx xxxx xxxx 0111 xxxx */
 507         /* SXTAH                cccc 0110 1011 xxxx xxxx xxxx 0111 xxxx */
 508         /* UXTAB16              cccc 0110 1100 xxxx xxxx xxxx 0111 xxxx */
 509         /* UXTAB                cccc 0110 1110 xxxx xxxx xxxx 0111 xxxx */
 510         /* UXTAH                cccc 0110 1111 xxxx xxxx xxxx 0111 xxxx */
 511         DECODE_EMULATEX (0x0f8000f0, 0x06800070, PROBES_EXTEND_ADD,
 512                                                  REGS(NOPCX, NOPC, 0, 0, NOPC)),
 513
 514         DECODE_END
 515 };
 516
 517 static const union decode_item arm_cccc_0111_____xxx1_table[] = {
 518         /* Media instructions                                           */
 519
 520         /* UNDEFINED            cccc 0111 1111 xxxx xxxx xxxx 1111 xxxx */
 521         DECODE_REJECT   (0x0ff000f0, 0x07f000f0),
 522
 523         /* SMLALD               cccc 0111 0100 xxxx xxxx xxxx 00x1 xxxx */
 524         /* SMLSLD               cccc 0111 0100 xxxx xxxx xxxx 01x1 xxxx */
 525         DECODE_EMULATEX (0x0ff00090, 0x07400010, PROBES_MUL_ADD_LONG,
 526                                                  REGS(NOPC, NOPC, NOPC, 0, NOPC)),
 527
 528         /* SMUAD                cccc 0111 0000 xxxx 1111 xxxx 00x1 xxxx */
 529         /* SMUSD                cccc 0111 0000 xxxx 1111 xxxx 01x1 xxxx */
 530         DECODE_OR       (0x0ff0f090, 0x0700f010),
 531         /* SMMUL                cccc 0111 0101 xxxx 1111 xxxx 00x1 xxxx */
 532         DECODE_OR       (0x0ff0f0d0, 0x0750f010),
 533         /* USAD8                cccc 0111 1000 xxxx 1111 xxxx 0001 xxxx */
 534         DECODE_EMULATEX (0x0ff0f0f0, 0x0780f010, PROBES_MUL_ADD,
 535                                                  REGS(NOPC, 0, NOPC, 0, NOPC)),
 536
 537         /* SMLAD                cccc 0111 0000 xxxx xxxx xxxx 00x1 xxxx */
 538         /* SMLSD                cccc 0111 0000 xxxx xxxx xxxx 01x1 xxxx */
 539         DECODE_OR       (0x0ff00090, 0x07000010),
 540         /* SMMLA                cccc 0111 0101 xxxx xxxx xxxx 00x1 xxxx */
 541         DECODE_OR       (0x0ff000d0, 0x07500010),
 542         /* USADA8               cccc 0111 1000 xxxx xxxx xxxx 0001 xxxx */
 543         DECODE_EMULATEX (0x0ff000f0, 0x07800010, PROBES_MUL_ADD,
 544                                                  REGS(NOPC, NOPCX, NOPC, 0, NOPC)),
 545
 546         /* SMMLS                cccc 0111 0101 xxxx xxxx xxxx 11x1 xxxx */
 547         DECODE_EMULATEX (0x0ff000d0, 0x075000d0, PROBES_MUL_ADD,
 548                                                  REGS(NOPC, NOPC, NOPC, 0, NOPC)),
 549
 550         /* SBFX                 cccc 0111 101x xxxx xxxx xxxx x101 xxxx */
 551         /* UBFX                 cccc 0111 111x xxxx xxxx xxxx x101 xxxx */
 552         DECODE_EMULATEX (0x0fa00070, 0x07a00050, PROBES_BITFIELD,
 553                                                  REGS(0, NOPC, 0, 0, NOPC)),
 554
 555         /* BFC                  cccc 0111 110x xxxx xxxx xxxx x001 1111 */
 556         DECODE_EMULATEX (0x0fe0007f, 0x07c0001f, PROBES_BITFIELD,
 557                                                  REGS(0, NOPC, 0, 0, 0)),
 558
 559         /* BFI                  cccc 0111 110x xxxx xxxx xxxx x001 xxxx */
 560         DECODE_EMULATEX (0x0fe00070, 0x07c00010, PROBES_BITFIELD,
 561                                                  REGS(0, NOPC, 0, 0, NOPCX)),
 562
 563         DECODE_END
 564 };
 565
 566 static const union decode_item arm_cccc_01xx_table[] = {
 567         /* Load/store word and unsigned byte                            */
 568
 569         /* LDRB/STRB pc,[...]   cccc 01xx x0xx xxxx xxxx xxxx xxxx xxxx */
 570         DECODE_REJECT   (0x0c40f000, 0x0440f000),
 571
 572         /* STRT                 cccc 01x0 x010 xxxx xxxx xxxx xxxx xxxx */
 573         /* LDRT                 cccc 01x0 x011 xxxx xxxx xxxx xxxx xxxx */
 574         /* STRBT                cccc 01x0 x110 xxxx xxxx xxxx xxxx xxxx */
 575         /* LDRBT                cccc 01x0 x111 xxxx xxxx xxxx xxxx xxxx */
 576         DECODE_REJECT   (0x0d200000, 0x04200000),
 577
 578         /* STR (immediate)      cccc 010x x0x0 xxxx xxxx xxxx xxxx xxxx */
 579         /* STRB (immediate)     cccc 010x x1x0 xxxx xxxx xxxx xxxx xxxx */
 580         DECODE_EMULATEX (0x0e100000, 0x04000000, PROBES_STORE,
 581                                                  REGS(NOPCWB, ANY, 0, 0, 0)),
 582
 583         /* LDR (immediate)      cccc 010x x0x1 xxxx xxxx xxxx xxxx xxxx */
 584         /* LDRB (immediate)     cccc 010x x1x1 xxxx xxxx xxxx xxxx xxxx */
 585         DECODE_EMULATEX (0x0e100000, 0x04100000, PROBES_LOAD,
 586                                                  REGS(NOPCWB, ANY, 0, 0, 0)),
 587
 588         /* STR (register)       cccc 011x x0x0 xxxx xxxx xxxx xxxx xxxx */
 589         /* STRB (register)      cccc 011x x1x0 xxxx xxxx xxxx xxxx xxxx */
 590         DECODE_EMULATEX (0x0e100000, 0x06000000, PROBES_STORE,
 591                                                  REGS(NOPCWB, ANY, 0, 0, NOPC)),
 592
 593         /* LDR (register)       cccc 011x x0x1 xxxx xxxx xxxx xxxx xxxx */
 594         /* LDRB (register)      cccc 011x x1x1 xxxx xxxx xxxx xxxx xxxx */
 595         DECODE_EMULATEX (0x0e100000, 0x06100000, PROBES_LOAD,
 596                                                  REGS(NOPCWB, ANY, 0, 0, NOPC)),
 597
 598         DECODE_END
 599 };
 600
 601 static const union decode_item arm_cccc_100x_table[] = {
 602         /* Block data transfer instructions                             */
 603
 604         /* LDM                  cccc 100x x0x1 xxxx xxxx xxxx xxxx xxxx */
 605         /* STM                  cccc 100x x0x0 xxxx xxxx xxxx xxxx xxxx */
 606         DECODE_CUSTOM   (0x0e400000, 0x08000000, PROBES_LDMSTM),
 607
 608         /* STM (user registers) cccc 100x x1x0 xxxx xxxx xxxx xxxx xxxx */
 609         /* LDM (user registers) cccc 100x x1x1 xxxx 0xxx xxxx xxxx xxxx */
 610         /* LDM (exception ret)  cccc 100x x1x1 xxxx 1xxx xxxx xxxx xxxx */
 611         DECODE_END
 612 };
 613
 614 const union decode_item probes_decode_arm_table[] = {
 615         /*
 616          * Unconditional instructions
 617          *                      1111 xxxx xxxx xxxx xxxx xxxx xxxx xxxx
 618          */
 619         DECODE_TABLE    (0xf0000000, 0xf0000000, arm_1111_table),
 620
 621         /*
 622          * Miscellaneous instructions
 623          *                      cccc 0001 0xx0 xxxx xxxx xxxx 0xxx xxxx
 624          */
 625         DECODE_TABLE    (0x0f900080, 0x01000000, arm_cccc_0001_0xx0____0xxx_table),
 626
 627         /*
 628          * Halfword multiply and multiply-accumulate
 629          *                      cccc 0001 0xx0 xxxx xxxx xxxx 1xx0 xxxx
 630          */
 631         DECODE_TABLE    (0x0f900090, 0x01000080, arm_cccc_0001_0xx0____1xx0_table),
 632
 633         /*
 634          * Multiply and multiply-accumulate
 635          *                      cccc 0000 xxxx xxxx xxxx xxxx 1001 xxxx
 636          */
 637         DECODE_TABLE    (0x0f0000f0, 0x00000090, arm_cccc_0000_____1001_table),
 638
 639         /*
 640          * Synchronization primitives
 641          *                      cccc 0001 xxxx xxxx xxxx xxxx 1001 xxxx
 642          */
 643         DECODE_TABLE    (0x0f0000f0, 0x01000090, arm_cccc_0001_____1001_table),
 644
 645         /*
 646          * Extra load/store instructions
 647          *                      cccc 000x xxxx xxxx xxxx xxxx 1xx1 xxxx
 648          */
 649         DECODE_TABLE    (0x0e000090, 0x00000090, arm_cccc_000x_____1xx1_table),
 650
 651         /*
 652          * Data-processing (register)
 653          *                      cccc 000x xxxx xxxx xxxx xxxx xxx0 xxxx
 654          * Data-processing (register-shifted register)
 655          *                      cccc 000x xxxx xxxx xxxx xxxx 0xx1 xxxx
 656          */
 657         DECODE_TABLE    (0x0e000000, 0x00000000, arm_cccc_000x_table),
 658
 659         /*
 660          * Data-processing (immediate)
 661          *                      cccc 001x xxxx xxxx xxxx xxxx xxxx xxxx
 662          */
 663         DECODE_TABLE    (0x0e000000, 0x02000000, arm_cccc_001x_table),
 664
 665         /*
 666          * Media instructions
 667          *                      cccc 011x xxxx xxxx xxxx xxxx xxx1 xxxx
 668          */
 669         DECODE_TABLE    (0x0f000010, 0x06000010, arm_cccc_0110_____xxx1_table),
 670         DECODE_TABLE    (0x0f000010, 0x07000010, arm_cccc_0111_____xxx1_table),
 671
 672         /*
 673          * Load/store word and unsigned byte
 674          *                      cccc 01xx xxxx xxxx xxxx xxxx xxxx xxxx
 675          */
 676         DECODE_TABLE    (0x0c000000, 0x04000000, arm_cccc_01xx_table),
 677
 678         /*
 679          * Block data transfer instructions
 680          *                      cccc 100x xxxx xxxx xxxx xxxx xxxx xxxx
 681          */
 682         DECODE_TABLE    (0x0e000000, 0x08000000, arm_cccc_100x_table),
 683
 684         /* B                    cccc 1010 xxxx xxxx xxxx xxxx xxxx xxxx */
 685         /* BL                   cccc 1011 xxxx xxxx xxxx xxxx xxxx xxxx */
 686         DECODE_SIMULATE (0x0e000000, 0x0a000000, PROBES_BRANCH),
 687
 688         /*
 689          * Supervisor Call, and coprocessor instructions
 690          */
 691
 692         /* MCRR                 cccc 1100 0100 xxxx xxxx xxxx xxxx xxxx */
 693         /* MRRC                 cccc 1100 0101 xxxx xxxx xxxx xxxx xxxx */
 694         /* LDC                  cccc 110x xxx1 xxxx xxxx xxxx xxxx xxxx */
 695         /* STC                  cccc 110x xxx0 xxxx xxxx xxxx xxxx xxxx */
 696         /* CDP                  cccc 1110 xxxx xxxx xxxx xxxx xxx0 xxxx */
 697         /* MCR                  cccc 1110 xxx0 xxxx xxxx xxxx xxx1 xxxx */
 698         /* MRC                  cccc 1110 xxx1 xxxx xxxx xxxx xxx1 xxxx */
 699         /* SVC                  cccc 1111 xxxx xxxx xxxx xxxx xxxx xxxx */
 700         DECODE_REJECT   (0x0c000000, 0x0c000000),
 701
 702         DECODE_END
 703 };
 704 #ifdef CONFIG_ARM_KPROBES_TEST_MODULE
 705 EXPORT_SYMBOL_GPL(probes_decode_arm_table);
 706 #endif
 707
 708 static void __kprobes arm_singlestep(probes_opcode_t insn,
 709                 struct arch_probes_insn *asi, struct pt_regs *regs)
 710 {
 711         regs->ARM_pc += 4;
 712         asi->insn_handler(insn, asi, regs);
 713 }
 714
 715 /* Return:
 716  *   INSN_REJECTED     If instruction is one not allowed to kprobe,
 717  *   INSN_GOOD         If instruction is supported and uses instruction slot,
 718  *   INSN_GOOD_NO_SLOT If instruction is supported but doesn't use its slot.
 719  *
 720  * For instructions we don't want to kprobe (INSN_REJECTED return result):
 721  *   These are generally ones that modify the processor state making
 722  *   them "hard" to simulate such as switches processor modes or
 723  *   make accesses in alternate modes.  Any of these could be simulated
 724  *   if the work was put into it, but low return considering they
 725  *   should also be very rare.
 726  */
 727 enum probes_insn __kprobes
 728 arm_probes_decode_insn(probes_opcode_t insn, struct arch_probes_insn *asi,
 729                        bool emulate, const union decode_action *actions,
 730                        const struct decode_checker *checkers[])
 731 {
 732         asi->insn_singlestep = arm_singlestep;
 733         asi->insn_check_cc = probes_condition_checks[insn>>28];
 734         return probes_decode_insn(insn, asi, probes_decode_arm_table, false,
 735                                   emulate, actions, checkers);
 736 }