1 /* arch/arm/plat-s5pc1xx/include/plat/regs-clock.h
3 * Copyright 2009 Samsung Electronics Co.
4 * Byungho Min <bhmin@samsung.com>
6 * S5PC1XX clock register definitions
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #ifndef __PLAT_REGS_CLOCK_H
14 #define __PLAT_REGS_CLOCK_H __FILE__
16 #define S5PC100_CLKREG(x) (S5PC1XX_VA_CLK + (x))
17 #define S5PC100_CLKREG_OTHER(x) (S5PC1XX_VA_CLK_OTHER + (x))
19 /* s5pc100 register for clock */
20 #define S5PC100_APLL_LOCK S5PC100_CLKREG(0x00)
21 #define S5PC100_MPLL_LOCK S5PC100_CLKREG(0x04)
22 #define S5PC100_EPLL_LOCK S5PC100_CLKREG(0x08)
23 #define S5PC100_HPLL_LOCK S5PC100_CLKREG(0x0C)
25 #define S5PC100_APLL_CON S5PC100_CLKREG(0x100)
26 #define S5PC100_MPLL_CON S5PC100_CLKREG(0x104)
27 #define S5PC100_EPLL_CON S5PC100_CLKREG(0x108)
28 #define S5PC100_HPLL_CON S5PC100_CLKREG(0x10C)
30 #define S5PC100_CLKSRC0 S5PC100_CLKREG(0x200)
31 #define S5PC100_CLKSRC1 S5PC100_CLKREG(0x204)
32 #define S5PC100_CLKSRC2 S5PC100_CLKREG(0x208)
33 #define S5PC100_CLKSRC3 S5PC100_CLKREG(0x20C)
35 #define S5PC100_CLKDIV0 S5PC100_CLKREG(0x300)
36 #define S5PC100_CLKDIV1 S5PC100_CLKREG(0x304)
37 #define S5PC100_CLKDIV2 S5PC100_CLKREG(0x308)
38 #define S5PC100_CLKDIV3 S5PC100_CLKREG(0x30C)
39 #define S5PC100_CLKDIV4 S5PC100_CLKREG(0x310)
41 #define S5PC100_CLK_OUT S5PC100_CLKREG(0x400)
43 #define S5PC100_CLKGATE_D00 S5PC100_CLKREG(0x500)
44 #define S5PC100_CLKGATE_D01 S5PC100_CLKREG(0x504)
45 #define S5PC100_CLKGATE_D02 S5PC100_CLKREG(0x508)
47 #define S5PC100_CLKGATE_D10 S5PC100_CLKREG(0x520)
48 #define S5PC100_CLKGATE_D11 S5PC100_CLKREG(0x524)
49 #define S5PC100_CLKGATE_D12 S5PC100_CLKREG(0x528)
50 #define S5PC100_CLKGATE_D13 S5PC100_CLKREG(0x52C)
51 #define S5PC100_CLKGATE_D14 S5PC100_CLKREG(0x530)
52 #define S5PC100_CLKGATE_D15 S5PC100_CLKREG(0x534)
54 #define S5PC100_CLKGATE_D20 S5PC100_CLKREG(0x540)
56 #define S5PC100_SCLKGATE0 S5PC100_CLKREG(0x560)
57 #define S5PC100_SCLKGATE1 S5PC100_CLKREG(0x564)
60 #define S5PC100_EPLL_EN (1<<31)
61 #define S5PC100_EPLL_MASK 0xffffffff
62 #define S5PC100_EPLLVAL(_m, _p, _s) ((_m) << 16 | ((_p) << 8) | ((_s)))
64 /* CLKSRC0..CLKSRC3 -> mostly removed due to clksrc updates */
65 #define S5PC100_CLKSRC1_CLK48M_MASK (0x1<<24)
66 #define S5PC100_CLKSRC1_CLK48M_SHIFT (24)
69 #define S5PC100_CLKDIV0_APLL_MASK (0x1<<0)
70 #define S5PC100_CLKDIV0_APLL_SHIFT (0)
71 #define S5PC100_CLKDIV0_ARM_MASK (0x7<<4)
72 #define S5PC100_CLKDIV0_ARM_SHIFT (4)
73 #define S5PC100_CLKDIV0_D0_MASK (0x7<<8)
74 #define S5PC100_CLKDIV0_D0_SHIFT (8)
75 #define S5PC100_CLKDIV0_PCLKD0_MASK (0x7<<12)
76 #define S5PC100_CLKDIV0_PCLKD0_SHIFT (12)
77 #define S5PC100_CLKDIV0_SECSS_MASK (0x7<<16)
78 #define S5PC100_CLKDIV0_SECSS_SHIFT (16)
80 /* CLKDIV1 (OneNAND clock only used in one place, removed) */
81 #define S5PC100_CLKDIV1_APLL2_MASK (0x7<<0)
82 #define S5PC100_CLKDIV1_APLL2_SHIFT (0)
83 #define S5PC100_CLKDIV1_MPLL_MASK (0x3<<4)
84 #define S5PC100_CLKDIV1_MPLL_SHIFT (4)
85 #define S5PC100_CLKDIV1_MPLL2_MASK (0x1<<8)
86 #define S5PC100_CLKDIV1_MPLL2_SHIFT (8)
87 #define S5PC100_CLKDIV1_D1_MASK (0x7<<12)
88 #define S5PC100_CLKDIV1_D1_SHIFT (12)
89 #define S5PC100_CLKDIV1_PCLKD1_MASK (0x7<<16)
90 #define S5PC100_CLKDIV1_PCLKD1_SHIFT (16)
91 #define S5PC100_CLKDIV1_CAM_MASK (0x1F<<24)
92 #define S5PC100_CLKDIV1_CAM_SHIFT (24)
94 /* CLKDIV2 => removed in clksrc update */
95 /* CLKDIV3 => removed in clksrc update, or not needed */
96 /* CLKDIV4 => removed in clksrc update, or not needed */
98 /* HCLKD0/PCLKD0 Clock Gate 0 Registers */
99 #define S5PC100_CLKGATE_D00_INTC (1<<0)
100 #define S5PC100_CLKGATE_D00_TZIC (1<<1)
101 #define S5PC100_CLKGATE_D00_CFCON (1<<2)
102 #define S5PC100_CLKGATE_D00_MDMA (1<<3)
103 #define S5PC100_CLKGATE_D00_G2D (1<<4)
104 #define S5PC100_CLKGATE_D00_SECSS (1<<5)
105 #define S5PC100_CLKGATE_D00_CSSYS (1<<6)
107 /* HCLKD0/PCLKD0 Clock Gate 1 Registers */
108 #define S5PC100_CLKGATE_D01_DMC (1<<0)
109 #define S5PC100_CLKGATE_D01_SROMC (1<<1)
110 #define S5PC100_CLKGATE_D01_ONENAND (1<<2)
111 #define S5PC100_CLKGATE_D01_NFCON (1<<3)
112 #define S5PC100_CLKGATE_D01_INTMEM (1<<4)
113 #define S5PC100_CLKGATE_D01_EBI (1<<5)
115 /* PCLKD0 Clock Gate 2 Registers */
116 #define S5PC100_CLKGATE_D02_SECKEY (1<<1)
117 #define S5PC100_CLKGATE_D02_SDM (1<<2)
119 /* HCLKD1/PCLKD1 Clock Gate 0 Registers */
120 #define S5PC100_CLKGATE_D10_PDMA0 (1<<0)
121 #define S5PC100_CLKGATE_D10_PDMA1 (1<<1)
122 #define S5PC100_CLKGATE_D10_USBHOST (1<<2)
123 #define S5PC100_CLKGATE_D10_USBOTG (1<<3)
124 #define S5PC100_CLKGATE_D10_MODEMIF (1<<4)
125 #define S5PC100_CLKGATE_D10_HSMMC0 (1<<5)
126 #define S5PC100_CLKGATE_D10_HSMMC1 (1<<6)
127 #define S5PC100_CLKGATE_D10_HSMMC2 (1<<7)
129 /* HCLKD1/PCLKD1 Clock Gate 1 Registers */
130 #define S5PC100_CLKGATE_D11_LCD (1<<0)
131 #define S5PC100_CLKGATE_D11_ROTATOR (1<<1)
132 #define S5PC100_CLKGATE_D11_FIMC0 (1<<2)
133 #define S5PC100_CLKGATE_D11_FIMC1 (1<<3)
134 #define S5PC100_CLKGATE_D11_FIMC2 (1<<4)
135 #define S5PC100_CLKGATE_D11_JPEG (1<<5)
136 #define S5PC100_CLKGATE_D11_DSI (1<<6)
137 #define S5PC100_CLKGATE_D11_CSI (1<<7)
138 #define S5PC100_CLKGATE_D11_G3D (1<<8)
140 /* HCLKD1/PCLKD1 Clock Gate 2 Registers */
141 #define S5PC100_CLKGATE_D12_TV (1<<0)
142 #define S5PC100_CLKGATE_D12_VP (1<<1)
143 #define S5PC100_CLKGATE_D12_MIXER (1<<2)
144 #define S5PC100_CLKGATE_D12_HDMI (1<<3)
145 #define S5PC100_CLKGATE_D12_MFC (1<<4)
147 /* HCLKD1/PCLKD1 Clock Gate 3 Registers */
148 #define S5PC100_CLKGATE_D13_CHIPID (1<<0)
149 #define S5PC100_CLKGATE_D13_GPIO (1<<1)
150 #define S5PC100_CLKGATE_D13_APC (1<<2)
151 #define S5PC100_CLKGATE_D13_IEC (1<<3)
152 #define S5PC100_CLKGATE_D13_PWM (1<<6)
153 #define S5PC100_CLKGATE_D13_SYSTIMER (1<<7)
154 #define S5PC100_CLKGATE_D13_WDT (1<<8)
155 #define S5PC100_CLKGATE_D13_RTC (1<<9)
157 /* HCLKD1/PCLKD1 Clock Gate 4 Registers */
158 #define S5PC100_CLKGATE_D14_UART0 (1<<0)
159 #define S5PC100_CLKGATE_D14_UART1 (1<<1)
160 #define S5PC100_CLKGATE_D14_UART2 (1<<2)
161 #define S5PC100_CLKGATE_D14_UART3 (1<<3)
162 #define S5PC100_CLKGATE_D14_IIC (1<<4)
163 #define S5PC100_CLKGATE_D14_HDMI_IIC (1<<5)
164 #define S5PC100_CLKGATE_D14_SPI0 (1<<6)
165 #define S5PC100_CLKGATE_D14_SPI1 (1<<7)
166 #define S5PC100_CLKGATE_D14_SPI2 (1<<8)
167 #define S5PC100_CLKGATE_D14_IRDA (1<<9)
168 #define S5PC100_CLKGATE_D14_CCAN0 (1<<10)
169 #define S5PC100_CLKGATE_D14_CCAN1 (1<<11)
170 #define S5PC100_CLKGATE_D14_HSITX (1<<12)
171 #define S5PC100_CLKGATE_D14_HSIRX (1<<13)
173 /* HCLKD1/PCLKD1 Clock Gate 5 Registers */
174 #define S5PC100_CLKGATE_D15_IIS0 (1<<0)
175 #define S5PC100_CLKGATE_D15_IIS1 (1<<1)
176 #define S5PC100_CLKGATE_D15_IIS2 (1<<2)
177 #define S5PC100_CLKGATE_D15_AC97 (1<<3)
178 #define S5PC100_CLKGATE_D15_PCM0 (1<<4)
179 #define S5PC100_CLKGATE_D15_PCM1 (1<<5)
180 #define S5PC100_CLKGATE_D15_SPDIF (1<<6)
181 #define S5PC100_CLKGATE_D15_TSADC (1<<7)
182 #define S5PC100_CLKGATE_D15_KEYIF (1<<8)
183 #define S5PC100_CLKGATE_D15_CG (1<<9)
185 /* HCLKD2 Clock Gate 0 Registers */
186 #define S5PC100_CLKGATE_D20_HCLKD2 (1<<0)
187 #define S5PC100_CLKGATE_D20_I2SD2 (1<<1)
189 /* Special Clock Gate 0 Registers */
190 #define S5PC100_CLKGATE_SCLK0_HPM (1<<0)
191 #define S5PC100_CLKGATE_SCLK0_PWI (1<<1)
192 #define S5PC100_CLKGATE_SCLK0_ONENAND (1<<2)
193 #define S5PC100_CLKGATE_SCLK0_UART (1<<3)
194 #define S5PC100_CLKGATE_SCLK0_SPI0 (1<<4)
195 #define S5PC100_CLKGATE_SCLK0_SPI1 (1<<5)
196 #define S5PC100_CLKGATE_SCLK0_SPI2 (1<<6)
197 #define S5PC100_CLKGATE_SCLK0_SPI0_48 (1<<7)
198 #define S5PC100_CLKGATE_SCLK0_SPI1_48 (1<<8)
199 #define S5PC100_CLKGATE_SCLK0_SPI2_48 (1<<9)
200 #define S5PC100_CLKGATE_SCLK0_IRDA (1<<10)
201 #define S5PC100_CLKGATE_SCLK0_USBHOST (1<<11)
202 #define S5PC100_CLKGATE_SCLK0_MMC0 (1<<12)
203 #define S5PC100_CLKGATE_SCLK0_MMC1 (1<<13)
204 #define S5PC100_CLKGATE_SCLK0_MMC2 (1<<14)
205 #define S5PC100_CLKGATE_SCLK0_MMC0_48 (1<<15)
206 #define S5PC100_CLKGATE_SCLK0_MMC1_48 (1<<16)
207 #define S5PC100_CLKGATE_SCLK0_MMC2_48 (1<<17)
209 /* Special Clock Gate 1 Registers */
210 #define S5PC100_CLKGATE_SCLK1_LCD (1<<0)
211 #define S5PC100_CLKGATE_SCLK1_FIMC0 (1<<1)
212 #define S5PC100_CLKGATE_SCLK1_FIMC1 (1<<2)
213 #define S5PC100_CLKGATE_SCLK1_FIMC2 (1<<3)
214 #define S5PC100_CLKGATE_SCLK1_TV54 (1<<4)
215 #define S5PC100_CLKGATE_SCLK1_VDAC54 (1<<5)
216 #define S5PC100_CLKGATE_SCLK1_MIXER (1<<6)
217 #define S5PC100_CLKGATE_SCLK1_HDMI (1<<7)
218 #define S5PC100_CLKGATE_SCLK1_AUDIO0 (1<<8)
219 #define S5PC100_CLKGATE_SCLK1_AUDIO1 (1<<9)
220 #define S5PC100_CLKGATE_SCLK1_AUDIO2 (1<<10)
221 #define S5PC100_CLKGATE_SCLK1_SPDIF (1<<11)
222 #define S5PC100_CLKGATE_SCLK1_CAM (1<<12)
224 #define S5PC100_SWRESET S5PC100_CLKREG_OTHER(0x000)
225 #define S5PC100_OND_SWRESET S5PC100_CLKREG_OTHER(0x008)
226 #define S5PC100_GEN_CTRL S5PC100_CLKREG_OTHER(0x100)
227 #define S5PC100_GEN_STATUS S5PC100_CLKREG_OTHER(0x104)
228 #define S5PC100_MEM_SYS_CFG S5PC100_CLKREG_OTHER(0x200)
229 #define S5PC100_CAM_MUX_SEL S5PC100_CLKREG_OTHER(0x300)
230 #define S5PC100_MIXER_OUT_SEL S5PC100_CLKREG_OTHER(0x304)
231 #define S5PC100_LPMP_MODE_SEL S5PC100_CLKREG_OTHER(0x308)
232 #define S5PC100_MIPI_PHY_CON0 S5PC100_CLKREG_OTHER(0x400)
233 #define S5PC100_MIPI_PHY_CON1 S5PC100_CLKREG_OTHER(0x414)
234 #define S5PC100_HDMI_PHY_CON0 S5PC100_CLKREG_OTHER(0x420)
236 #define S5PC100_SWRESET_RESETVAL 0xc100
237 #define S5PC100_OTHER_SYS_INT 24
238 #define S5PC100_OTHER_STA_TYPE 23
239 #define STA_TYPE_EXPON 0
240 #define STA_TYPE_SFR 1
242 #define S5PC100_SLEEP_CFG_OSC_EN 0
244 /* OTHERS Resgister */
245 #define S5PC100_OTHERS_USB_SIG_MASK (1 << 16)
246 #define S5PC100_OTHERS_MIPI_DPHY_EN (1 << 28)
248 /* MIPI D-PHY Control Register 0 */
249 #define S5PC100_MIPI_PHY_CON0_M_RESETN (1 << 1)
250 #define S5PC100_MIPI_PHY_CON0_S_RESETN (1 << 0)
252 #endif /* _PLAT_REGS_CLOCK_H */