Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
[pandora-kernel.git] / arch / arm / plat-omap / sram.c
1 /*
2  * linux/arch/arm/plat-omap/sram.c
3  *
4  * OMAP SRAM detection and management
5  *
6  * Copyright (C) 2005 Nokia Corporation
7  * Written by Tony Lindgren <tony@atomide.com>
8  *
9  * Copyright (C) 2009 Texas Instruments
10  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11  *
12  * This program is free software; you can redistribute it and/or modify
13  * it under the terms of the GNU General Public License version 2 as
14  * published by the Free Software Foundation.
15  */
16 #undef DEBUG
17
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/io.h>
22 #include <linux/omapfb.h>
23
24 #include <asm/tlb.h>
25 #include <asm/cacheflush.h>
26
27 #include <asm/mach/map.h>
28
29 #include <plat/sram.h>
30 #include <plat/board.h>
31 #include <plat/cpu.h>
32 #include <plat/vram.h>
33
34 #include "sram.h"
35 #include "fb.h"
36
37 /* XXX These "sideways" includes are a sign that something is wrong */
38 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
39 # include "../mach-omap2/prm2xxx_3xxx.h"
40 # include "../mach-omap2/sdrc.h"
41 #endif
42
43 #define OMAP1_SRAM_PA           0x20000000
44 #define OMAP1_SRAM_VA           VMALLOC_END
45 #define OMAP2_SRAM_PUB_PA       (OMAP2_SRAM_PA + 0xf800)
46 #define OMAP2_SRAM_VA           0xfe400000
47 #define OMAP2_SRAM_PUB_VA       (OMAP2_SRAM_VA + 0x800)
48 #define OMAP3_SRAM_VA           0xfe400000
49 #define OMAP3_SRAM_PUB_PA       (OMAP3_SRAM_PA + 0x8000)
50 #define OMAP3_SRAM_PUB_VA       (OMAP3_SRAM_VA + 0x8000)
51 #define OMAP4_SRAM_VA           0xfe400000
52 #define OMAP4_SRAM_PUB_PA       (OMAP4_SRAM_PA + 0x4000)
53 #define OMAP4_SRAM_PUB_VA       (OMAP4_SRAM_VA + 0x4000)
54
55 #if defined(CONFIG_ARCH_OMAP2PLUS)
56 #define SRAM_BOOTLOADER_SZ      0x00
57 #else
58 #define SRAM_BOOTLOADER_SZ      0x80
59 #endif
60
61 #define OMAP24XX_VA_REQINFOPERM0        OMAP2_L3_IO_ADDRESS(0x68005048)
62 #define OMAP24XX_VA_READPERM0           OMAP2_L3_IO_ADDRESS(0x68005050)
63 #define OMAP24XX_VA_WRITEPERM0          OMAP2_L3_IO_ADDRESS(0x68005058)
64
65 #define OMAP34XX_VA_REQINFOPERM0        OMAP2_L3_IO_ADDRESS(0x68012848)
66 #define OMAP34XX_VA_READPERM0           OMAP2_L3_IO_ADDRESS(0x68012850)
67 #define OMAP34XX_VA_WRITEPERM0          OMAP2_L3_IO_ADDRESS(0x68012858)
68 #define OMAP34XX_VA_ADDR_MATCH2         OMAP2_L3_IO_ADDRESS(0x68012880)
69 #define OMAP34XX_VA_SMS_RG_ATT0         OMAP2_L3_IO_ADDRESS(0x6C000048)
70
71 #define GP_DEVICE               0x300
72
73 #define ROUND_DOWN(value,boundary)      ((value) & (~((boundary)-1)))
74
75 static unsigned long omap_sram_start;
76 static unsigned long omap_sram_base;
77 static unsigned long omap_sram_size;
78 static unsigned long omap_sram_ceil;
79
80 /*
81  * Depending on the target RAMFS firewall setup, the public usable amount of
82  * SRAM varies.  The default accessible size for all device types is 2k. A GP
83  * device allows ARM11 but not other initiators for full size. This
84  * functionality seems ok until some nice security API happens.
85  */
86 static int is_sram_locked(void)
87 {
88         if (OMAP2_DEVICE_TYPE_GP == omap_type()) {
89                 /* RAMFW: R/W access to all initiators for all qualifier sets */
90                 if (cpu_is_omap242x()) {
91                         __raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
92                         __raw_writel(0xCFDE, OMAP24XX_VA_READPERM0);  /* all i-read */
93                         __raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
94                 }
95                 if (cpu_is_omap34xx()) {
96                         __raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
97                         __raw_writel(0xFFFF, OMAP34XX_VA_READPERM0);  /* all i-read */
98                         __raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
99                         __raw_writel(0x0, OMAP34XX_VA_ADDR_MATCH2);
100                         __raw_writel(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
101                 }
102                 return 0;
103         } else
104                 return 1; /* assume locked with no PPA or security driver */
105 }
106
107 /*
108  * The amount of SRAM depends on the core type.
109  * Note that we cannot try to test for SRAM here because writes
110  * to secure SRAM will hang the system. Also the SRAM is not
111  * yet mapped at this point.
112  */
113 static void __init omap_detect_sram(void)
114 {
115         unsigned long reserved;
116
117         if (cpu_class_is_omap2()) {
118                 if (is_sram_locked()) {
119                         if (cpu_is_omap34xx()) {
120                                 omap_sram_base = OMAP3_SRAM_PUB_VA;
121                                 omap_sram_start = OMAP3_SRAM_PUB_PA;
122                                 if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) ||
123                                     (omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
124                                         omap_sram_size = 0x7000; /* 28K */
125                                 } else {
126                                         omap_sram_size = 0x8000; /* 32K */
127                                 }
128                         } else if (cpu_is_omap44xx()) {
129                                 omap_sram_base = OMAP4_SRAM_PUB_VA;
130                                 omap_sram_start = OMAP4_SRAM_PUB_PA;
131                                 omap_sram_size = 0xa000; /* 40K */
132                         } else {
133                                 omap_sram_base = OMAP2_SRAM_PUB_VA;
134                                 omap_sram_start = OMAP2_SRAM_PUB_PA;
135                                 omap_sram_size = 0x800; /* 2K */
136                         }
137                 } else {
138                         if (cpu_is_omap34xx()) {
139                                 omap_sram_base = OMAP3_SRAM_VA;
140                                 omap_sram_start = OMAP3_SRAM_PA;
141                                 omap_sram_size = 0x10000; /* 64K */
142                         } else if (cpu_is_omap44xx()) {
143                                 omap_sram_base = OMAP4_SRAM_VA;
144                                 omap_sram_start = OMAP4_SRAM_PA;
145                                 omap_sram_size = 0xe000; /* 56K */
146                         } else {
147                                 omap_sram_base = OMAP2_SRAM_VA;
148                                 omap_sram_start = OMAP2_SRAM_PA;
149                                 if (cpu_is_omap242x())
150                                         omap_sram_size = 0xa0000; /* 640K */
151                                 else if (cpu_is_omap243x())
152                                         omap_sram_size = 0x10000; /* 64K */
153                         }
154                 }
155         } else {
156                 omap_sram_base = OMAP1_SRAM_VA;
157                 omap_sram_start = OMAP1_SRAM_PA;
158
159                 if (cpu_is_omap7xx())
160                         omap_sram_size = 0x32000;       /* 200K */
161                 else if (cpu_is_omap15xx())
162                         omap_sram_size = 0x30000;       /* 192K */
163                 else if (cpu_is_omap1610() || cpu_is_omap1621() ||
164                      cpu_is_omap1710())
165                         omap_sram_size = 0x4000;        /* 16K */
166                 else if (cpu_is_omap1611())
167                         omap_sram_size = SZ_256K;
168                 else {
169                         pr_err("Could not detect SRAM size\n");
170                         omap_sram_size = 0x4000;
171                 }
172         }
173         reserved = omapfb_reserve_sram(omap_sram_start, omap_sram_base,
174                                        omap_sram_size,
175                                        omap_sram_start + SRAM_BOOTLOADER_SZ,
176                                        omap_sram_size - SRAM_BOOTLOADER_SZ);
177         omap_sram_size -= reserved;
178
179         reserved = omap_vram_reserve_sram(omap_sram_start, omap_sram_base,
180                         omap_sram_size,
181                         omap_sram_start + SRAM_BOOTLOADER_SZ,
182                         omap_sram_size - SRAM_BOOTLOADER_SZ);
183         omap_sram_size -= reserved;
184
185         omap_sram_ceil = omap_sram_base + omap_sram_size;
186 }
187
188 static struct map_desc omap_sram_io_desc[] __initdata = {
189         {       /* .length gets filled in at runtime */
190                 .virtual        = OMAP1_SRAM_VA,
191                 .pfn            = __phys_to_pfn(OMAP1_SRAM_PA),
192                 .type           = MT_MEMORY
193         }
194 };
195
196 /*
197  * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
198  */
199 static void __init omap_map_sram(void)
200 {
201         unsigned long base;
202
203         if (omap_sram_size == 0)
204                 return;
205
206         if (cpu_is_omap34xx()) {
207                 /*
208                  * SRAM must be marked as non-cached on OMAP3 since the
209                  * CORE DPLL M2 divider change code (in SRAM) runs with the
210                  * SDRAM controller disabled, and if it is marked cached,
211                  * the ARM may attempt to write cache lines back to SDRAM
212                  * which will cause the system to hang.
213                  */
214                 omap_sram_io_desc[0].type = MT_MEMORY_NONCACHED;
215         }
216
217         omap_sram_io_desc[0].virtual = omap_sram_base;
218         base = omap_sram_start;
219         base = ROUND_DOWN(base, PAGE_SIZE);
220         omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
221         omap_sram_io_desc[0].length = ROUND_DOWN(omap_sram_size, PAGE_SIZE);
222         iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc));
223
224         pr_info("SRAM: Mapped pa 0x%08llx to va 0x%08lx size: 0x%lx\n",
225                 (long long) __pfn_to_phys(omap_sram_io_desc[0].pfn),
226                 omap_sram_io_desc[0].virtual,
227                 omap_sram_io_desc[0].length);
228
229         /*
230          * Normally devicemaps_init() would flush caches and tlb after
231          * mdesc->map_io(), but since we're called from map_io(), we
232          * must do it here.
233          */
234         local_flush_tlb_all();
235         flush_cache_all();
236
237         /*
238          * Looks like we need to preserve some bootloader code at the
239          * beginning of SRAM for jumping to flash for reboot to work...
240          */
241         memset((void *)omap_sram_base + SRAM_BOOTLOADER_SZ, 0,
242                omap_sram_size - SRAM_BOOTLOADER_SZ);
243 }
244
245 /*
246  * Memory allocator for SRAM: calculates the new ceiling address
247  * for pushing a function using the fncpy API.
248  *
249  * Note that fncpy requires the returned address to be aligned
250  * to an 8-byte boundary.
251  */
252 void *omap_sram_push_address(unsigned long size)
253 {
254         if (size > (omap_sram_ceil - (omap_sram_base + SRAM_BOOTLOADER_SZ))) {
255                 pr_err("Not enough space in SRAM\n");
256                 return NULL;
257         }
258
259         omap_sram_ceil -= size;
260         omap_sram_ceil = ROUND_DOWN(omap_sram_ceil, FNCPY_ALIGN);
261
262         return (void *)omap_sram_ceil;
263 }
264
265 #ifdef CONFIG_ARCH_OMAP1
266
267 static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl);
268
269 void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl)
270 {
271         BUG_ON(!_omap_sram_reprogram_clock);
272         _omap_sram_reprogram_clock(dpllctl, ckctl);
273 }
274
275 static int __init omap1_sram_init(void)
276 {
277         _omap_sram_reprogram_clock =
278                         omap_sram_push(omap1_sram_reprogram_clock,
279                                         omap1_sram_reprogram_clock_sz);
280
281         return 0;
282 }
283
284 #else
285 #define omap1_sram_init()       do {} while (0)
286 #endif
287
288 #if defined(CONFIG_ARCH_OMAP2)
289
290 static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
291                               u32 base_cs, u32 force_unlock);
292
293 void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
294                    u32 base_cs, u32 force_unlock)
295 {
296         BUG_ON(!_omap2_sram_ddr_init);
297         _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl,
298                              base_cs, force_unlock);
299 }
300
301 static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val,
302                                           u32 mem_type);
303
304 void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type)
305 {
306         BUG_ON(!_omap2_sram_reprogram_sdrc);
307         _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type);
308 }
309
310 static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
311
312 u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
313 {
314         BUG_ON(!_omap2_set_prcm);
315         return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
316 }
317 #endif
318
319 #ifdef CONFIG_SOC_OMAP2420
320 static int __init omap242x_sram_init(void)
321 {
322         _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init,
323                                         omap242x_sram_ddr_init_sz);
324
325         _omap2_sram_reprogram_sdrc = omap_sram_push(omap242x_sram_reprogram_sdrc,
326                                             omap242x_sram_reprogram_sdrc_sz);
327
328         _omap2_set_prcm = omap_sram_push(omap242x_sram_set_prcm,
329                                          omap242x_sram_set_prcm_sz);
330
331         return 0;
332 }
333 #else
334 static inline int omap242x_sram_init(void)
335 {
336         return 0;
337 }
338 #endif
339
340 #ifdef CONFIG_SOC_OMAP2430
341 static int __init omap243x_sram_init(void)
342 {
343         _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init,
344                                         omap243x_sram_ddr_init_sz);
345
346         _omap2_sram_reprogram_sdrc = omap_sram_push(omap243x_sram_reprogram_sdrc,
347                                             omap243x_sram_reprogram_sdrc_sz);
348
349         _omap2_set_prcm = omap_sram_push(omap243x_sram_set_prcm,
350                                          omap243x_sram_set_prcm_sz);
351
352         return 0;
353 }
354 #else
355 static inline int omap243x_sram_init(void)
356 {
357         return 0;
358 }
359 #endif
360
361 #ifdef CONFIG_ARCH_OMAP3
362
363 static u32 (*_omap3_sram_configure_core_dpll)(
364                         u32 m2, u32 unlock_dll, u32 f, u32 inc,
365                         u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
366                         u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
367                         u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
368                         u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
369
370 u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
371                         u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
372                         u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
373                         u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
374                         u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1)
375 {
376         BUG_ON(!_omap3_sram_configure_core_dpll);
377         return _omap3_sram_configure_core_dpll(
378                         m2, unlock_dll, f, inc,
379                         sdrc_rfr_ctrl_0, sdrc_actim_ctrl_a_0,
380                         sdrc_actim_ctrl_b_0, sdrc_mr_0,
381                         sdrc_rfr_ctrl_1, sdrc_actim_ctrl_a_1,
382                         sdrc_actim_ctrl_b_1, sdrc_mr_1);
383 }
384
385 #ifdef CONFIG_PM
386 void omap3_sram_restore_context(void)
387 {
388         omap_sram_ceil = omap_sram_base + omap_sram_size;
389
390         _omap3_sram_configure_core_dpll =
391                 omap_sram_push(omap3_sram_configure_core_dpll,
392                                omap3_sram_configure_core_dpll_sz);
393         omap_push_sram_idle();
394 }
395 #endif /* CONFIG_PM */
396
397 static int __init omap34xx_sram_init(void)
398 {
399         _omap3_sram_configure_core_dpll =
400                 omap_sram_push(omap3_sram_configure_core_dpll,
401                                omap3_sram_configure_core_dpll_sz);
402         omap_push_sram_idle();
403         return 0;
404 }
405 #else
406 static inline int omap34xx_sram_init(void)
407 {
408         return 0;
409 }
410 #endif
411
412 int __init omap_sram_init(void)
413 {
414         omap_detect_sram();
415         omap_map_sram();
416
417         if (!(cpu_class_is_omap2()))
418                 omap1_sram_init();
419         else if (cpu_is_omap242x())
420                 omap242x_sram_init();
421         else if (cpu_is_omap2430())
422                 omap243x_sram_init();
423         else if (cpu_is_omap34xx())
424                 omap34xx_sram_init();
425
426         return 0;
427 }