arch/arm/plat-omap/sram.c

   1 /*
   2  * linux/arch/arm/plat-omap/sram.c
   3  *
   4  * OMAP SRAM detection and management
   5  *
   6  * Copyright (C) 2005 Nokia Corporation
   7  * Written by Tony Lindgren <tony@atomide.com>
   8  *
   9  * Copyright (C) 2009 Texas Instruments
  10  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  */
  16 #undef DEBUG
  17
  18 #include <linux/module.h>
  19 #include <linux/kernel.h>
  20 #include <linux/init.h>
  21 #include <linux/io.h>
  22 #include <linux/omapfb.h>
  23
  24 #include <asm/tlb.h>
  25 #include <asm/cacheflush.h>
  26
  27 #include <asm/mach/map.h>
  28
  29 #include <plat/sram.h>
  30 #include <plat/board.h>
  31 #include <plat/cpu.h>
  32 #include <plat/vram.h>
  33
  34 #include "sram.h"
  35 #include "fb.h"
  36 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
  37 # include "../mach-omap2/prm.h"
  38 # include "../mach-omap2/cm.h"
  39 # include "../mach-omap2/sdrc.h"
  40 #endif
  41
  42 #define OMAP1_SRAM_PA           0x20000000
  43 #define OMAP1_SRAM_VA           VMALLOC_END
  44 #define OMAP2_SRAM_PUB_PA       (OMAP2_SRAM_PA + 0xf800)
  45 #define OMAP2_SRAM_VA           0xfe400000
  46 #define OMAP2_SRAM_PUB_VA       (OMAP2_SRAM_VA + 0x800)
  47 #define OMAP3_SRAM_VA           0xfe400000
  48 #define OMAP3_SRAM_PUB_PA       (OMAP3_SRAM_PA + 0x8000)
  49 #define OMAP3_SRAM_PUB_VA       (OMAP3_SRAM_VA + 0x8000)
  50 #define OMAP4_SRAM_VA           0xfe400000
  51 #define OMAP4_SRAM_PUB_PA       (OMAP4_SRAM_PA + 0x4000)
  52 #define OMAP4_SRAM_PUB_VA       (OMAP4_SRAM_VA + 0x4000)
  53
  54 #if defined(CONFIG_ARCH_OMAP2PLUS)
  55 #define SRAM_BOOTLOADER_SZ      0x00
  56 #else
  57 #define SRAM_BOOTLOADER_SZ      0x80
  58 #endif
  59
  60 #define OMAP24XX_VA_REQINFOPERM0        OMAP2_L3_IO_ADDRESS(0x68005048)
  61 #define OMAP24XX_VA_READPERM0           OMAP2_L3_IO_ADDRESS(0x68005050)
  62 #define OMAP24XX_VA_WRITEPERM0          OMAP2_L3_IO_ADDRESS(0x68005058)
  63
  64 #define OMAP34XX_VA_REQINFOPERM0        OMAP2_L3_IO_ADDRESS(0x68012848)
  65 #define OMAP34XX_VA_READPERM0           OMAP2_L3_IO_ADDRESS(0x68012850)
  66 #define OMAP34XX_VA_WRITEPERM0          OMAP2_L3_IO_ADDRESS(0x68012858)
  67 #define OMAP34XX_VA_ADDR_MATCH2         OMAP2_L3_IO_ADDRESS(0x68012880)
  68 #define OMAP34XX_VA_SMS_RG_ATT0         OMAP2_L3_IO_ADDRESS(0x6C000048)
  69
  70 #define GP_DEVICE               0x300
  71
  72 #define ROUND_DOWN(value,boundary)      ((value) & (~((boundary)-1)))
  73
  74 static unsigned long omap_sram_start;
  75 static unsigned long omap_sram_base;
  76 static unsigned long omap_sram_size;
  77 static unsigned long omap_sram_ceil;
  78
  79 /*
  80  * Depending on the target RAMFS firewall setup, the public usable amount of
  81  * SRAM varies.  The default accessible size for all device types is 2k. A GP
  82  * device allows ARM11 but not other initiators for full size. This
  83  * functionality seems ok until some nice security API happens.
  84  */
  85 static int is_sram_locked(void)
  86 {
  87         if (OMAP2_DEVICE_TYPE_GP == omap_type()) {
  88                 /* RAMFW: R/W access to all initiators for all qualifier sets */
  89                 if (cpu_is_omap242x()) {
  90                         __raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
  91                         __raw_writel(0xCFDE, OMAP24XX_VA_READPERM0);  /* all i-read */
  92                         __raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
  93                 }
  94                 if (cpu_is_omap34xx()) {
  95                         __raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
  96                         __raw_writel(0xFFFF, OMAP34XX_VA_READPERM0);  /* all i-read */
  97                         __raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
  98                         __raw_writel(0x0, OMAP34XX_VA_ADDR_MATCH2);
  99                         __raw_writel(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
 100                 }
 101                 return 0;
 102         } else
 103                 return 1; /* assume locked with no PPA or security driver */
 104 }
 105
 106 /*
 107  * The amount of SRAM depends on the core type.
 108  * Note that we cannot try to test for SRAM here because writes
 109  * to secure SRAM will hang the system. Also the SRAM is not
 110  * yet mapped at this point.
 111  */
 112 static void __init omap_detect_sram(void)
 113 {
 114         unsigned long reserved;
 115
 116         if (cpu_class_is_omap2()) {
 117                 if (is_sram_locked()) {
 118                         if (cpu_is_omap34xx()) {
 119                                 omap_sram_base = OMAP3_SRAM_PUB_VA;
 120                                 omap_sram_start = OMAP3_SRAM_PUB_PA;
 121                                 if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) ||
 122                                     (omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
 123                                         omap_sram_size = 0x7000; /* 28K */
 124                                 } else {
 125                                         omap_sram_size = 0x8000; /* 32K */
 126                                 }
 127                         } else if (cpu_is_omap44xx()) {
 128                                 omap_sram_base = OMAP4_SRAM_PUB_VA;
 129                                 omap_sram_start = OMAP4_SRAM_PUB_PA;
 130                                 omap_sram_size = 0xa000; /* 40K */
 131                         } else {
 132                                 omap_sram_base = OMAP2_SRAM_PUB_VA;
 133                                 omap_sram_start = OMAP2_SRAM_PUB_PA;
 134                                 omap_sram_size = 0x800; /* 2K */
 135                         }
 136                 } else {
 137                         if (cpu_is_omap34xx()) {
 138                                 omap_sram_base = OMAP3_SRAM_VA;
 139                                 omap_sram_start = OMAP3_SRAM_PA;
 140                                 omap_sram_size = 0x10000; /* 64K */
 141                         } else if (cpu_is_omap44xx()) {
 142                                 omap_sram_base = OMAP4_SRAM_VA;
 143                                 omap_sram_start = OMAP4_SRAM_PA;
 144                                 omap_sram_size = 0xe000; /* 56K */
 145                         } else {
 146                                 omap_sram_base = OMAP2_SRAM_VA;
 147                                 omap_sram_start = OMAP2_SRAM_PA;
 148                                 if (cpu_is_omap242x())
 149                                         omap_sram_size = 0xa0000; /* 640K */
 150                                 else if (cpu_is_omap243x())
 151                                         omap_sram_size = 0x10000; /* 64K */
 152                         }
 153                 }
 154         } else {
 155                 omap_sram_base = OMAP1_SRAM_VA;
 156                 omap_sram_start = OMAP1_SRAM_PA;
 157
 158                 if (cpu_is_omap7xx())
 159                         omap_sram_size = 0x32000;       /* 200K */
 160                 else if (cpu_is_omap15xx())
 161                         omap_sram_size = 0x30000;       /* 192K */
 162                 else if (cpu_is_omap1610() || cpu_is_omap1621() ||
 163                      cpu_is_omap1710())
 164                         omap_sram_size = 0x4000;        /* 16K */
 165                 else if (cpu_is_omap1611())
 166                         omap_sram_size = SZ_256K;
 167                 else {
 168                         printk(KERN_ERR "Could not detect SRAM size\n");
 169                         omap_sram_size = 0x4000;
 170                 }
 171         }
 172         reserved = omapfb_reserve_sram(omap_sram_start, omap_sram_base,
 173                                        omap_sram_size,
 174                                        omap_sram_start + SRAM_BOOTLOADER_SZ,
 175                                        omap_sram_size - SRAM_BOOTLOADER_SZ);
 176         omap_sram_size -= reserved;
 177
 178         reserved = omap_vram_reserve_sram(omap_sram_start, omap_sram_base,
 179                         omap_sram_size,
 180                         omap_sram_start + SRAM_BOOTLOADER_SZ,
 181                         omap_sram_size - SRAM_BOOTLOADER_SZ);
 182         omap_sram_size -= reserved;
 183
 184         omap_sram_ceil = omap_sram_base + omap_sram_size;
 185 }
 186
 187 static struct map_desc omap_sram_io_desc[] __initdata = {
 188         {       /* .length gets filled in at runtime */
 189                 .virtual        = OMAP1_SRAM_VA,
 190                 .pfn            = __phys_to_pfn(OMAP1_SRAM_PA),
 191                 .type           = MT_MEMORY
 192         }
 193 };
 194
 195 /*
 196  * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
 197  */
 198 static void __init omap_map_sram(void)
 199 {
 200         unsigned long base;
 201
 202         if (omap_sram_size == 0)
 203                 return;
 204
 205         if (cpu_is_omap34xx()) {
 206                 /*
 207                  * SRAM must be marked as non-cached on OMAP3 since the
 208                  * CORE DPLL M2 divider change code (in SRAM) runs with the
 209                  * SDRAM controller disabled, and if it is marked cached,
 210                  * the ARM may attempt to write cache lines back to SDRAM
 211                  * which will cause the system to hang.
 212                  */
 213                 omap_sram_io_desc[0].type = MT_MEMORY_NONCACHED;
 214         }
 215
 216         omap_sram_io_desc[0].virtual = omap_sram_base;
 217         base = omap_sram_start;
 218         base = ROUND_DOWN(base, PAGE_SIZE);
 219         omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
 220         omap_sram_io_desc[0].length = ROUND_DOWN(omap_sram_size, PAGE_SIZE);
 221         iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc));
 222
 223         printk(KERN_INFO "SRAM: Mapped pa 0x%08lx to va 0x%08lx size: 0x%lx\n",
 224         __pfn_to_phys(omap_sram_io_desc[0].pfn),
 225         omap_sram_io_desc[0].virtual,
 226                omap_sram_io_desc[0].length);
 227
 228         /*
 229          * Normally devicemaps_init() would flush caches and tlb after
 230          * mdesc->map_io(), but since we're called from map_io(), we
 231          * must do it here.
 232          */
 233         local_flush_tlb_all();
 234         flush_cache_all();
 235
 236         /*
 237          * Looks like we need to preserve some bootloader code at the
 238          * beginning of SRAM for jumping to flash for reboot to work...
 239          */
 240         memset((void *)omap_sram_base + SRAM_BOOTLOADER_SZ, 0,
 241                omap_sram_size - SRAM_BOOTLOADER_SZ);
 242 }
 243
 244 void * omap_sram_push(void * start, unsigned long size)
 245 {
 246         if (size > (omap_sram_ceil - (omap_sram_base + SRAM_BOOTLOADER_SZ))) {
 247                 printk(KERN_ERR "Not enough space in SRAM\n");
 248                 return NULL;
 249         }
 250
 251         omap_sram_ceil -= size;
 252         omap_sram_ceil = ROUND_DOWN(omap_sram_ceil, sizeof(void *));
 253         memcpy((void *)omap_sram_ceil, start, size);
 254         flush_icache_range((unsigned long)omap_sram_ceil,
 255                 (unsigned long)(omap_sram_ceil + size));
 256
 257         return (void *)omap_sram_ceil;
 258 }
 259
 260 #ifdef CONFIG_ARCH_OMAP1
 261
 262 static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl);
 263
 264 void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl)
 265 {
 266         BUG_ON(!_omap_sram_reprogram_clock);
 267         _omap_sram_reprogram_clock(dpllctl, ckctl);
 268 }
 269
 270 static int __init omap1_sram_init(void)
 271 {
 272         _omap_sram_reprogram_clock =
 273                         omap_sram_push(omap1_sram_reprogram_clock,
 274                                         omap1_sram_reprogram_clock_sz);
 275
 276         return 0;
 277 }
 278
 279 #else
 280 #define omap1_sram_init()       do {} while (0)
 281 #endif
 282
 283 #if defined(CONFIG_ARCH_OMAP2)
 284
 285 static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
 286                               u32 base_cs, u32 force_unlock);
 287
 288 void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
 289                    u32 base_cs, u32 force_unlock)
 290 {
 291         BUG_ON(!_omap2_sram_ddr_init);
 292         _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl,
 293                              base_cs, force_unlock);
 294 }
 295
 296 static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val,
 297                                           u32 mem_type);
 298
 299 void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type)
 300 {
 301         BUG_ON(!_omap2_sram_reprogram_sdrc);
 302         _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type);
 303 }
 304
 305 static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
 306
 307 u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
 308 {
 309         BUG_ON(!_omap2_set_prcm);
 310         return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
 311 }
 312 #endif
 313
 314 #ifdef CONFIG_ARCH_OMAP2420
 315 static int __init omap242x_sram_init(void)
 316 {
 317         _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init,
 318                                         omap242x_sram_ddr_init_sz);
 319
 320         _omap2_sram_reprogram_sdrc = omap_sram_push(omap242x_sram_reprogram_sdrc,
 321                                             omap242x_sram_reprogram_sdrc_sz);
 322
 323         _omap2_set_prcm = omap_sram_push(omap242x_sram_set_prcm,
 324                                          omap242x_sram_set_prcm_sz);
 325
 326         return 0;
 327 }
 328 #else
 329 static inline int omap242x_sram_init(void)
 330 {
 331         return 0;
 332 }
 333 #endif
 334
 335 #ifdef CONFIG_ARCH_OMAP2430
 336 static int __init omap243x_sram_init(void)
 337 {
 338         _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init,
 339                                         omap243x_sram_ddr_init_sz);
 340
 341         _omap2_sram_reprogram_sdrc = omap_sram_push(omap243x_sram_reprogram_sdrc,
 342                                             omap243x_sram_reprogram_sdrc_sz);
 343
 344         _omap2_set_prcm = omap_sram_push(omap243x_sram_set_prcm,
 345                                          omap243x_sram_set_prcm_sz);
 346
 347         return 0;
 348 }
 349 #else
 350 static inline int omap243x_sram_init(void)
 351 {
 352         return 0;
 353 }
 354 #endif
 355
 356 #ifdef CONFIG_ARCH_OMAP3
 357
 358 static u32 (*_omap3_sram_configure_core_dpll)(
 359                         u32 m2, u32 unlock_dll, u32 f, u32 inc,
 360                         u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
 361                         u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
 362                         u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
 363                         u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
 364
 365 u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
 366                         u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
 367                         u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
 368                         u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
 369                         u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1)
 370 {
 371         BUG_ON(!_omap3_sram_configure_core_dpll);
 372         return _omap3_sram_configure_core_dpll(
 373                         m2, unlock_dll, f, inc,
 374                         sdrc_rfr_ctrl_0, sdrc_actim_ctrl_a_0,
 375                         sdrc_actim_ctrl_b_0, sdrc_mr_0,
 376                         sdrc_rfr_ctrl_1, sdrc_actim_ctrl_a_1,
 377                         sdrc_actim_ctrl_b_1, sdrc_mr_1);
 378 }
 379
 380 #ifdef CONFIG_PM
 381 void omap3_sram_restore_context(void)
 382 {
 383         omap_sram_ceil = omap_sram_base + omap_sram_size;
 384
 385         _omap3_sram_configure_core_dpll =
 386                 omap_sram_push(omap3_sram_configure_core_dpll,
 387                                omap3_sram_configure_core_dpll_sz);
 388         omap_push_sram_idle();
 389 }
 390 #endif /* CONFIG_PM */
 391
 392 static int __init omap34xx_sram_init(void)
 393 {
 394         _omap3_sram_configure_core_dpll =
 395                 omap_sram_push(omap3_sram_configure_core_dpll,
 396                                omap3_sram_configure_core_dpll_sz);
 397         omap_push_sram_idle();
 398         return 0;
 399 }
 400 #else
 401 static inline int omap34xx_sram_init(void)
 402 {
 403         return 0;
 404 }
 405 #endif
 406
 407 #ifdef CONFIG_ARCH_OMAP4
 408 static int __init omap44xx_sram_init(void)
 409 {
 410         printk(KERN_ERR "FIXME: %s not implemented\n", __func__);
 411
 412         return -ENODEV;
 413 }
 414 #else
 415 static inline int omap44xx_sram_init(void)
 416 {
 417         return 0;
 418 }
 419 #endif
 420
 421 int __init omap_sram_init(void)
 422 {
 423         omap_detect_sram();
 424         omap_map_sram();
 425
 426         if (!(cpu_class_is_omap2()))
 427                 omap1_sram_init();
 428         else if (cpu_is_omap242x())
 429                 omap242x_sram_init();
 430         else if (cpu_is_omap2430())
 431                 omap243x_sram_init();
 432         else if (cpu_is_omap34xx())
 433                 omap34xx_sram_init();
 434         else if (cpu_is_omap44xx())
 435                 omap44xx_sram_init();
 436
 437         return 0;
 438 }