arch/arm/plat-omap/mcbsp.c

   1 /*
   2  * linux/arch/arm/plat-omap/mcbsp.c
   3  *
   4  * Copyright (C) 2004 Nokia Corporation
   5  * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
   6  *
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * Multichannel mode not supported.
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/init.h>
  17 #include <linux/device.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/wait.h>
  20 #include <linux/completion.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/err.h>
  23 #include <linux/clk.h>
  24 #include <linux/delay.h>
  25 #include <linux/io.h>
  26
  27 #include <mach/dma.h>
  28 #include <mach/mcbsp.h>
  29
  30 struct omap_mcbsp **mcbsp_ptr;
  31 int omap_mcbsp_count;
  32
  33 void omap_mcbsp_write(void __iomem *io_base, u16 reg, u32 val)
  34 {
  35         if (cpu_class_is_omap1() || cpu_is_omap2420())
  36                 __raw_writew((u16)val, io_base + reg);
  37         else
  38                 __raw_writel(val, io_base + reg);
  39 }
  40
  41 int omap_mcbsp_read(void __iomem *io_base, u16 reg)
  42 {
  43         if (cpu_class_is_omap1() || cpu_is_omap2420())
  44                 return __raw_readw(io_base + reg);
  45         else
  46                 return __raw_readl(io_base + reg);
  47 }
  48
  49 #define OMAP_MCBSP_READ(base, reg) \
  50                         omap_mcbsp_read(base, OMAP_MCBSP_REG_##reg)
  51 #define OMAP_MCBSP_WRITE(base, reg, val) \
  52                         omap_mcbsp_write(base, OMAP_MCBSP_REG_##reg, val)
  53
  54 #define omap_mcbsp_check_valid_id(id)   (id < omap_mcbsp_count)
  55 #define id_to_mcbsp_ptr(id)             mcbsp_ptr[id];
  56
  57 static void omap_mcbsp_dump_reg(u8 id)
  58 {
  59         struct omap_mcbsp *mcbsp = id_to_mcbsp_ptr(id);
  60
  61         dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
  62         dev_dbg(mcbsp->dev, "DRR2:  0x%04x\n",
  63                         OMAP_MCBSP_READ(mcbsp->io_base, DRR2));
  64         dev_dbg(mcbsp->dev, "DRR1:  0x%04x\n",
  65                         OMAP_MCBSP_READ(mcbsp->io_base, DRR1));
  66         dev_dbg(mcbsp->dev, "DXR2:  0x%04x\n",
  67                         OMAP_MCBSP_READ(mcbsp->io_base, DXR2));
  68         dev_dbg(mcbsp->dev, "DXR1:  0x%04x\n",
  69                         OMAP_MCBSP_READ(mcbsp->io_base, DXR1));
  70         dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n",
  71                         OMAP_MCBSP_READ(mcbsp->io_base, SPCR2));
  72         dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n",
  73                         OMAP_MCBSP_READ(mcbsp->io_base, SPCR1));
  74         dev_dbg(mcbsp->dev, "RCR2:  0x%04x\n",
  75                         OMAP_MCBSP_READ(mcbsp->io_base, RCR2));
  76         dev_dbg(mcbsp->dev, "RCR1:  0x%04x\n",
  77                         OMAP_MCBSP_READ(mcbsp->io_base, RCR1));
  78         dev_dbg(mcbsp->dev, "XCR2:  0x%04x\n",
  79                         OMAP_MCBSP_READ(mcbsp->io_base, XCR2));
  80         dev_dbg(mcbsp->dev, "XCR1:  0x%04x\n",
  81                         OMAP_MCBSP_READ(mcbsp->io_base, XCR1));
  82         dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n",
  83                         OMAP_MCBSP_READ(mcbsp->io_base, SRGR2));
  84         dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n",
  85                         OMAP_MCBSP_READ(mcbsp->io_base, SRGR1));
  86         dev_dbg(mcbsp->dev, "PCR0:  0x%04x\n",
  87                         OMAP_MCBSP_READ(mcbsp->io_base, PCR0));
  88         dev_dbg(mcbsp->dev, "***********************\n");
  89 }
  90
  91 static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
  92 {
  93         struct omap_mcbsp *mcbsp_tx = dev_id;
  94         u16 irqst_spcr2;
  95
  96         irqst_spcr2 = OMAP_MCBSP_READ(mcbsp_tx->io_base, SPCR2);
  97         dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
  98
  99         if (irqst_spcr2 & XSYNC_ERR) {
 100                 dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n",
 101                         irqst_spcr2);
 102                 /* Writing zero to XSYNC_ERR clears the IRQ */
 103                 OMAP_MCBSP_WRITE(mcbsp_tx->io_base, SPCR2,
 104                         irqst_spcr2 & ~(XSYNC_ERR));
 105         } else {
 106                 complete(&mcbsp_tx->tx_irq_completion);
 107         }
 108
 109         return IRQ_HANDLED;
 110 }
 111
 112 static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
 113 {
 114         struct omap_mcbsp *mcbsp_rx = dev_id;
 115         u16 irqst_spcr1;
 116
 117         irqst_spcr1 = OMAP_MCBSP_READ(mcbsp_rx->io_base, SPCR1);
 118         dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
 119
 120         if (irqst_spcr1 & RSYNC_ERR) {
 121                 dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n",
 122                         irqst_spcr1);
 123                 /* Writing zero to RSYNC_ERR clears the IRQ */
 124                 OMAP_MCBSP_WRITE(mcbsp_rx->io_base, SPCR1,
 125                         irqst_spcr1 & ~(RSYNC_ERR));
 126         } else {
 127                 complete(&mcbsp_rx->tx_irq_completion);
 128         }
 129
 130         return IRQ_HANDLED;
 131 }
 132
 133 static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data)
 134 {
 135         struct omap_mcbsp *mcbsp_dma_tx = data;
 136
 137         dev_dbg(mcbsp_dma_tx->dev, "TX DMA callback : 0x%x\n",
 138                 OMAP_MCBSP_READ(mcbsp_dma_tx->io_base, SPCR2));
 139
 140         /* We can free the channels */
 141         omap_free_dma(mcbsp_dma_tx->dma_tx_lch);
 142         mcbsp_dma_tx->dma_tx_lch = -1;
 143
 144         complete(&mcbsp_dma_tx->tx_dma_completion);
 145 }
 146
 147 static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
 148 {
 149         struct omap_mcbsp *mcbsp_dma_rx = data;
 150
 151         dev_dbg(mcbsp_dma_rx->dev, "RX DMA callback : 0x%x\n",
 152                 OMAP_MCBSP_READ(mcbsp_dma_rx->io_base, SPCR2));
 153
 154         /* We can free the channels */
 155         omap_free_dma(mcbsp_dma_rx->dma_rx_lch);
 156         mcbsp_dma_rx->dma_rx_lch = -1;
 157
 158         complete(&mcbsp_dma_rx->rx_dma_completion);
 159 }
 160
 161 /*
 162  * omap_mcbsp_config simply write a config to the
 163  * appropriate McBSP.
 164  * You either call this function or set the McBSP registers
 165  * by yourself before calling omap_mcbsp_start().
 166  */
 167 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
 168 {
 169         struct omap_mcbsp *mcbsp;
 170         void __iomem *io_base;
 171
 172         if (!omap_mcbsp_check_valid_id(id)) {
 173                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 174                 return;
 175         }
 176         mcbsp = id_to_mcbsp_ptr(id);
 177
 178         io_base = mcbsp->io_base;
 179         dev_dbg(mcbsp->dev, "Configuring McBSP%d  phys_base: 0x%08lx\n",
 180                         mcbsp->id, mcbsp->phys_base);
 181
 182         /* We write the given config */
 183         OMAP_MCBSP_WRITE(io_base, SPCR2, config->spcr2);
 184         OMAP_MCBSP_WRITE(io_base, SPCR1, config->spcr1);
 185         OMAP_MCBSP_WRITE(io_base, RCR2, config->rcr2);
 186         OMAP_MCBSP_WRITE(io_base, RCR1, config->rcr1);
 187         OMAP_MCBSP_WRITE(io_base, XCR2, config->xcr2);
 188         OMAP_MCBSP_WRITE(io_base, XCR1, config->xcr1);
 189         OMAP_MCBSP_WRITE(io_base, SRGR2, config->srgr2);
 190         OMAP_MCBSP_WRITE(io_base, SRGR1, config->srgr1);
 191         OMAP_MCBSP_WRITE(io_base, MCR2, config->mcr2);
 192         OMAP_MCBSP_WRITE(io_base, MCR1, config->mcr1);
 193         OMAP_MCBSP_WRITE(io_base, PCR0, config->pcr0);
 194         if (cpu_is_omap2430() || cpu_is_omap34xx()) {
 195                 OMAP_MCBSP_WRITE(io_base, XCCR, config->xccr);
 196                 OMAP_MCBSP_WRITE(io_base, RCCR, config->rccr);
 197         }
 198 }
 199 EXPORT_SYMBOL(omap_mcbsp_config);
 200
 201 #ifdef CONFIG_ARCH_OMAP34XX
 202 /*
 203  * omap_mcbsp_set_tx_threshold configures how to deal
 204  * with transmit threshold. the threshold value and handler can be
 205  * configure in here.
 206  */
 207 void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
 208 {
 209         struct omap_mcbsp *mcbsp;
 210         void __iomem *io_base;
 211
 212         if (!cpu_is_omap34xx())
 213                 return;
 214
 215         if (!omap_mcbsp_check_valid_id(id)) {
 216                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 217                 return;
 218         }
 219         mcbsp = id_to_mcbsp_ptr(id);
 220         io_base = mcbsp->io_base;
 221
 222         OMAP_MCBSP_WRITE(io_base, THRSH2, threshold);
 223 }
 224 EXPORT_SYMBOL(omap_mcbsp_set_tx_threshold);
 225
 226 /*
 227  * omap_mcbsp_set_rx_threshold configures how to deal
 228  * with receive threshold. the threshold value and handler can be
 229  * configure in here.
 230  */
 231 void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
 232 {
 233         struct omap_mcbsp *mcbsp;
 234         void __iomem *io_base;
 235
 236         if (!cpu_is_omap34xx())
 237                 return;
 238
 239         if (!omap_mcbsp_check_valid_id(id)) {
 240                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 241                 return;
 242         }
 243         mcbsp = id_to_mcbsp_ptr(id);
 244         io_base = mcbsp->io_base;
 245
 246         OMAP_MCBSP_WRITE(io_base, THRSH1, threshold);
 247 }
 248 EXPORT_SYMBOL(omap_mcbsp_set_rx_threshold);
 249
 250 /*
 251  * omap_mcbsp_get_max_tx_thres just return the current configured
 252  * maximum threshold for transmission
 253  */
 254 u16 omap_mcbsp_get_max_tx_threshold(unsigned int id)
 255 {
 256         struct omap_mcbsp *mcbsp;
 257
 258         if (!omap_mcbsp_check_valid_id(id)) {
 259                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 260                 return -ENODEV;
 261         }
 262         mcbsp = id_to_mcbsp_ptr(id);
 263
 264         return mcbsp->max_tx_thres;
 265 }
 266 EXPORT_SYMBOL(omap_mcbsp_get_max_tx_threshold);
 267
 268 /*
 269  * omap_mcbsp_get_max_rx_thres just return the current configured
 270  * maximum threshold for reception
 271  */
 272 u16 omap_mcbsp_get_max_rx_threshold(unsigned int id)
 273 {
 274         struct omap_mcbsp *mcbsp;
 275
 276         if (!omap_mcbsp_check_valid_id(id)) {
 277                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 278                 return -ENODEV;
 279         }
 280         mcbsp = id_to_mcbsp_ptr(id);
 281
 282         return mcbsp->max_rx_thres;
 283 }
 284 EXPORT_SYMBOL(omap_mcbsp_get_max_rx_threshold);
 285
 286 /*
 287  * omap_mcbsp_get_dma_op_mode just return the current configured
 288  * operating mode for the mcbsp channel
 289  */
 290 int omap_mcbsp_get_dma_op_mode(unsigned int id)
 291 {
 292         struct omap_mcbsp *mcbsp;
 293         int dma_op_mode;
 294
 295         if (!omap_mcbsp_check_valid_id(id)) {
 296                 printk(KERN_ERR "%s: Invalid id (%u)\n", __func__, id + 1);
 297                 return -ENODEV;
 298         }
 299         mcbsp = id_to_mcbsp_ptr(id);
 300
 301         spin_lock_irq(&mcbsp->lock);
 302         dma_op_mode = mcbsp->dma_op_mode;
 303         spin_unlock_irq(&mcbsp->lock);
 304
 305         return dma_op_mode;
 306 }
 307 EXPORT_SYMBOL(omap_mcbsp_get_dma_op_mode);
 308
 309 static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp)
 310 {
 311         /*
 312          * Enable wakup behavior, smart idle and all wakeups
 313          * REVISIT: some wakeups may be unnecessary
 314          */
 315         if (cpu_is_omap34xx()) {
 316                 u16 syscon;
 317
 318                 syscon = OMAP_MCBSP_READ(mcbsp->io_base, SYSCON);
 319                 syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
 320
 321                 spin_lock_irq(&mcbsp->lock);
 322                 if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) {
 323                         syscon |= (ENAWAKEUP | SIDLEMODE(0x02) |
 324                                         CLOCKACTIVITY(0x02));
 325                         OMAP_MCBSP_WRITE(mcbsp->io_base, WAKEUPEN,
 326                                         XRDYEN | RRDYEN);
 327                 } else {
 328                         syscon |= SIDLEMODE(0x01);
 329                 }
 330                 spin_unlock_irq(&mcbsp->lock);
 331
 332                 OMAP_MCBSP_WRITE(mcbsp->io_base, SYSCON, syscon);
 333         }
 334 }
 335
 336 static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp)
 337 {
 338         /*
 339          * Disable wakup behavior, smart idle and all wakeups
 340          */
 341         if (cpu_is_omap34xx()) {
 342                 u16 syscon;
 343
 344                 syscon = OMAP_MCBSP_READ(mcbsp->io_base, SYSCON);
 345                 syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
 346                 OMAP_MCBSP_WRITE(mcbsp->io_base, SYSCON, syscon);
 347
 348                 OMAP_MCBSP_WRITE(mcbsp->io_base, WAKEUPEN, 0);
 349         }
 350 }
 351 #else
 352 static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp) {}
 353 static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp) {}
 354 #endif
 355
 356 /*
 357  * We can choose between IRQ based or polled IO.
 358  * This needs to be called before omap_mcbsp_request().
 359  */
 360 int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type)
 361 {
 362         struct omap_mcbsp *mcbsp;
 363
 364         if (!omap_mcbsp_check_valid_id(id)) {
 365                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 366                 return -ENODEV;
 367         }
 368         mcbsp = id_to_mcbsp_ptr(id);
 369
 370         spin_lock(&mcbsp->lock);
 371
 372         if (!mcbsp->free) {
 373                 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
 374                         mcbsp->id);
 375                 spin_unlock(&mcbsp->lock);
 376                 return -EINVAL;
 377         }
 378
 379         mcbsp->io_type = io_type;
 380
 381         spin_unlock(&mcbsp->lock);
 382
 383         return 0;
 384 }
 385 EXPORT_SYMBOL(omap_mcbsp_set_io_type);
 386
 387 int omap_mcbsp_request(unsigned int id)
 388 {
 389         struct omap_mcbsp *mcbsp;
 390         int err;
 391
 392         if (!omap_mcbsp_check_valid_id(id)) {
 393                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 394                 return -ENODEV;
 395         }
 396         mcbsp = id_to_mcbsp_ptr(id);
 397
 398         spin_lock(&mcbsp->lock);
 399         if (!mcbsp->free) {
 400                 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
 401                         mcbsp->id);
 402                 spin_unlock(&mcbsp->lock);
 403                 return -EBUSY;
 404         }
 405
 406         mcbsp->free = 0;
 407         spin_unlock(&mcbsp->lock);
 408
 409         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
 410                 mcbsp->pdata->ops->request(id);
 411
 412         clk_enable(mcbsp->iclk);
 413         clk_enable(mcbsp->fclk);
 414
 415         /* Do procedure specific to omap34xx arch, if applicable */
 416         omap34xx_mcbsp_request(mcbsp);
 417
 418         /*
 419          * Make sure that transmitter, receiver and sample-rate generator are
 420          * not running before activating IRQs.
 421          */
 422         OMAP_MCBSP_WRITE(mcbsp->io_base, SPCR1, 0);
 423         OMAP_MCBSP_WRITE(mcbsp->io_base, SPCR2, 0);
 424
 425         if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
 426                 /* We need to get IRQs here */
 427                 init_completion(&mcbsp->tx_irq_completion);
 428                 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler,
 429                                         0, "McBSP", (void *)mcbsp);
 430                 if (err != 0) {
 431                         dev_err(mcbsp->dev, "Unable to request TX IRQ %d "
 432                                         "for McBSP%d\n", mcbsp->tx_irq,
 433                                         mcbsp->id);
 434                         return err;
 435                 }
 436
 437                 init_completion(&mcbsp->rx_irq_completion);
 438                 err = request_irq(mcbsp->rx_irq, omap_mcbsp_rx_irq_handler,
 439                                         0, "McBSP", (void *)mcbsp);
 440                 if (err != 0) {
 441                         dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
 442                                         "for McBSP%d\n", mcbsp->rx_irq,
 443                                         mcbsp->id);
 444                         free_irq(mcbsp->tx_irq, (void *)mcbsp);
 445                         return err;
 446                 }
 447         }
 448
 449         return 0;
 450 }
 451 EXPORT_SYMBOL(omap_mcbsp_request);
 452
 453 void omap_mcbsp_free(unsigned int id)
 454 {
 455         struct omap_mcbsp *mcbsp;
 456
 457         if (!omap_mcbsp_check_valid_id(id)) {
 458                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 459                 return;
 460         }
 461         mcbsp = id_to_mcbsp_ptr(id);
 462
 463         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
 464                 mcbsp->pdata->ops->free(id);
 465
 466         /* Do procedure specific to omap34xx arch, if applicable */
 467         omap34xx_mcbsp_free(mcbsp);
 468
 469         clk_disable(mcbsp->fclk);
 470         clk_disable(mcbsp->iclk);
 471
 472         if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
 473                 /* Free IRQs */
 474                 free_irq(mcbsp->rx_irq, (void *)mcbsp);
 475                 free_irq(mcbsp->tx_irq, (void *)mcbsp);
 476         }
 477
 478         spin_lock(&mcbsp->lock);
 479         if (mcbsp->free) {
 480                 dev_err(mcbsp->dev, "McBSP%d was not reserved\n",
 481                         mcbsp->id);
 482                 spin_unlock(&mcbsp->lock);
 483                 return;
 484         }
 485
 486         mcbsp->free = 1;
 487         spin_unlock(&mcbsp->lock);
 488 }
 489 EXPORT_SYMBOL(omap_mcbsp_free);
 490
 491 /*
 492  * Here we start the McBSP, by enabling transmitter, receiver or both.
 493  * If no transmitter or receiver is active prior calling, then sample-rate
 494  * generator and frame sync are started.
 495  */
 496 void omap_mcbsp_start(unsigned int id, int tx, int rx)
 497 {
 498         struct omap_mcbsp *mcbsp;
 499         void __iomem *io_base;
 500         int idle;
 501         u16 w;
 502
 503         if (!omap_mcbsp_check_valid_id(id)) {
 504                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 505                 return;
 506         }
 507         mcbsp = id_to_mcbsp_ptr(id);
 508         io_base = mcbsp->io_base;
 509
 510         mcbsp->rx_word_length = (OMAP_MCBSP_READ(io_base, RCR1) >> 5) & 0x7;
 511         mcbsp->tx_word_length = (OMAP_MCBSP_READ(io_base, XCR1) >> 5) & 0x7;
 512
 513         idle = !((OMAP_MCBSP_READ(io_base, SPCR2) |
 514                   OMAP_MCBSP_READ(io_base, SPCR1)) & 1);
 515
 516         if (idle) {
 517                 /* Start the sample generator */
 518                 w = OMAP_MCBSP_READ(io_base, SPCR2);
 519                 OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 6));
 520         }
 521
 522         /* Enable transmitter and receiver */
 523         w = OMAP_MCBSP_READ(io_base, SPCR2);
 524         OMAP_MCBSP_WRITE(io_base, SPCR2, w | (tx & 1));
 525
 526         w = OMAP_MCBSP_READ(io_base, SPCR1);
 527         OMAP_MCBSP_WRITE(io_base, SPCR1, w | (rx & 1));
 528
 529         /*
 530          * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
 531          * REVISIT: 100us may give enough time for two CLKSRG, however
 532          * due to some unknown PM related, clock gating etc. reason it
 533          * is now at 500us.
 534          */
 535         udelay(500);
 536
 537         if (idle) {
 538                 /* Start frame sync */
 539                 w = OMAP_MCBSP_READ(io_base, SPCR2);
 540                 OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 7));
 541         }
 542
 543         /* Dump McBSP Regs */
 544         omap_mcbsp_dump_reg(id);
 545 }
 546 EXPORT_SYMBOL(omap_mcbsp_start);
 547
 548 void omap_mcbsp_stop(unsigned int id, int tx, int rx)
 549 {
 550         struct omap_mcbsp *mcbsp;
 551         void __iomem *io_base;
 552         int idle;
 553         u16 w;
 554
 555         if (!omap_mcbsp_check_valid_id(id)) {
 556                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 557                 return;
 558         }
 559
 560         mcbsp = id_to_mcbsp_ptr(id);
 561         io_base = mcbsp->io_base;
 562
 563         /* Reset transmitter */
 564         w = OMAP_MCBSP_READ(io_base, SPCR2);
 565         OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(tx & 1));
 566
 567         /* Reset receiver */
 568         w = OMAP_MCBSP_READ(io_base, SPCR1);
 569         OMAP_MCBSP_WRITE(io_base, SPCR1, w & ~(rx & 1));
 570
 571         idle = !((OMAP_MCBSP_READ(io_base, SPCR2) |
 572                   OMAP_MCBSP_READ(io_base, SPCR1)) & 1);
 573
 574         if (idle) {
 575                 /* Reset the sample rate generator */
 576                 w = OMAP_MCBSP_READ(io_base, SPCR2);
 577                 OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1 << 6));
 578         }
 579 }
 580 EXPORT_SYMBOL(omap_mcbsp_stop);
 581
 582 void omap_mcbsp_xmit_enable(unsigned int id, u8 enable)
 583 {
 584         struct omap_mcbsp *mcbsp;
 585         void __iomem *io_base;
 586         u16 w;
 587
 588         if (!(cpu_is_omap2430() || cpu_is_omap34xx()))
 589                 return;
 590
 591         if (!omap_mcbsp_check_valid_id(id)) {
 592                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 593                 return;
 594         }
 595
 596         mcbsp = id_to_mcbsp_ptr(id);
 597         io_base = mcbsp->io_base;
 598
 599         w = OMAP_MCBSP_READ(io_base, XCCR);
 600
 601         if (enable)
 602                 OMAP_MCBSP_WRITE(io_base, XCCR, w & ~(XDISABLE));
 603         else
 604                 OMAP_MCBSP_WRITE(io_base, XCCR, w | XDISABLE);
 605 }
 606 EXPORT_SYMBOL(omap_mcbsp_xmit_enable);
 607
 608 void omap_mcbsp_recv_enable(unsigned int id, u8 enable)
 609 {
 610         struct omap_mcbsp *mcbsp;
 611         void __iomem *io_base;
 612         u16 w;
 613
 614         if (!(cpu_is_omap2430() || cpu_is_omap34xx()))
 615                 return;
 616
 617         if (!omap_mcbsp_check_valid_id(id)) {
 618                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 619                 return;
 620         }
 621
 622         mcbsp = id_to_mcbsp_ptr(id);
 623         io_base = mcbsp->io_base;
 624
 625         w = OMAP_MCBSP_READ(io_base, RCCR);
 626
 627         if (enable)
 628                 OMAP_MCBSP_WRITE(io_base, RCCR, w & ~(RDISABLE));
 629         else
 630                 OMAP_MCBSP_WRITE(io_base, RCCR, w | RDISABLE);
 631 }
 632 EXPORT_SYMBOL(omap_mcbsp_recv_enable);
 633
 634 /* polled mcbsp i/o operations */
 635 int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
 636 {
 637         struct omap_mcbsp *mcbsp;
 638         void __iomem *base;
 639
 640         if (!omap_mcbsp_check_valid_id(id)) {
 641                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 642                 return -ENODEV;
 643         }
 644
 645         mcbsp = id_to_mcbsp_ptr(id);
 646         base = mcbsp->io_base;
 647
 648         writew(buf, base + OMAP_MCBSP_REG_DXR1);
 649         /* if frame sync error - clear the error */
 650         if (readw(base + OMAP_MCBSP_REG_SPCR2) & XSYNC_ERR) {
 651                 /* clear error */
 652                 writew(readw(base + OMAP_MCBSP_REG_SPCR2) & (~XSYNC_ERR),
 653                        base + OMAP_MCBSP_REG_SPCR2);
 654                 /* resend */
 655                 return -1;
 656         } else {
 657                 /* wait for transmit confirmation */
 658                 int attemps = 0;
 659                 while (!(readw(base + OMAP_MCBSP_REG_SPCR2) & XRDY)) {
 660                         if (attemps++ > 1000) {
 661                                 writew(readw(base + OMAP_MCBSP_REG_SPCR2) &
 662                                        (~XRST),
 663                                        base + OMAP_MCBSP_REG_SPCR2);
 664                                 udelay(10);
 665                                 writew(readw(base + OMAP_MCBSP_REG_SPCR2) |
 666                                        (XRST),
 667                                        base + OMAP_MCBSP_REG_SPCR2);
 668                                 udelay(10);
 669                                 dev_err(mcbsp->dev, "Could not write to"
 670                                         " McBSP%d Register\n", mcbsp->id);
 671                                 return -2;
 672                         }
 673                 }
 674         }
 675
 676         return 0;
 677 }
 678 EXPORT_SYMBOL(omap_mcbsp_pollwrite);
 679
 680 int omap_mcbsp_pollread(unsigned int id, u16 *buf)
 681 {
 682         struct omap_mcbsp *mcbsp;
 683         void __iomem *base;
 684
 685         if (!omap_mcbsp_check_valid_id(id)) {
 686                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 687                 return -ENODEV;
 688         }
 689         mcbsp = id_to_mcbsp_ptr(id);
 690
 691         base = mcbsp->io_base;
 692         /* if frame sync error - clear the error */
 693         if (readw(base + OMAP_MCBSP_REG_SPCR1) & RSYNC_ERR) {
 694                 /* clear error */
 695                 writew(readw(base + OMAP_MCBSP_REG_SPCR1) & (~RSYNC_ERR),
 696                        base + OMAP_MCBSP_REG_SPCR1);
 697                 /* resend */
 698                 return -1;
 699         } else {
 700                 /* wait for recieve confirmation */
 701                 int attemps = 0;
 702                 while (!(readw(base + OMAP_MCBSP_REG_SPCR1) & RRDY)) {
 703                         if (attemps++ > 1000) {
 704                                 writew(readw(base + OMAP_MCBSP_REG_SPCR1) &
 705                                        (~RRST),
 706                                        base + OMAP_MCBSP_REG_SPCR1);
 707                                 udelay(10);
 708                                 writew(readw(base + OMAP_MCBSP_REG_SPCR1) |
 709                                        (RRST),
 710                                        base + OMAP_MCBSP_REG_SPCR1);
 711                                 udelay(10);
 712                                 dev_err(mcbsp->dev, "Could not read from"
 713                                         " McBSP%d Register\n", mcbsp->id);
 714                                 return -2;
 715                         }
 716                 }
 717         }
 718         *buf = readw(base + OMAP_MCBSP_REG_DRR1);
 719
 720         return 0;
 721 }
 722 EXPORT_SYMBOL(omap_mcbsp_pollread);
 723
 724 /*
 725  * IRQ based word transmission.
 726  */
 727 void omap_mcbsp_xmit_word(unsigned int id, u32 word)
 728 {
 729         struct omap_mcbsp *mcbsp;
 730         void __iomem *io_base;
 731         omap_mcbsp_word_length word_length;
 732
 733         if (!omap_mcbsp_check_valid_id(id)) {
 734                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 735                 return;
 736         }
 737
 738         mcbsp = id_to_mcbsp_ptr(id);
 739         io_base = mcbsp->io_base;
 740         word_length = mcbsp->tx_word_length;
 741
 742         wait_for_completion(&mcbsp->tx_irq_completion);
 743
 744         if (word_length > OMAP_MCBSP_WORD_16)
 745                 OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16);
 746         OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff);
 747 }
 748 EXPORT_SYMBOL(omap_mcbsp_xmit_word);
 749
 750 u32 omap_mcbsp_recv_word(unsigned int id)
 751 {
 752         struct omap_mcbsp *mcbsp;
 753         void __iomem *io_base;
 754         u16 word_lsb, word_msb = 0;
 755         omap_mcbsp_word_length word_length;
 756
 757         if (!omap_mcbsp_check_valid_id(id)) {
 758                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 759                 return -ENODEV;
 760         }
 761         mcbsp = id_to_mcbsp_ptr(id);
 762
 763         word_length = mcbsp->rx_word_length;
 764         io_base = mcbsp->io_base;
 765
 766         wait_for_completion(&mcbsp->rx_irq_completion);
 767
 768         if (word_length > OMAP_MCBSP_WORD_16)
 769                 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
 770         word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
 771
 772         return (word_lsb | (word_msb << 16));
 773 }
 774 EXPORT_SYMBOL(omap_mcbsp_recv_word);
 775
 776 int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
 777 {
 778         struct omap_mcbsp *mcbsp;
 779         void __iomem *io_base;
 780         omap_mcbsp_word_length tx_word_length;
 781         omap_mcbsp_word_length rx_word_length;
 782         u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
 783
 784         if (!omap_mcbsp_check_valid_id(id)) {
 785                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 786                 return -ENODEV;
 787         }
 788         mcbsp = id_to_mcbsp_ptr(id);
 789         io_base = mcbsp->io_base;
 790         tx_word_length = mcbsp->tx_word_length;
 791         rx_word_length = mcbsp->rx_word_length;
 792
 793         if (tx_word_length != rx_word_length)
 794                 return -EINVAL;
 795
 796         /* First we wait for the transmitter to be ready */
 797         spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
 798         while (!(spcr2 & XRDY)) {
 799                 spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
 800                 if (attempts++ > 1000) {
 801                         /* We must reset the transmitter */
 802                         OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 & (~XRST));
 803                         udelay(10);
 804                         OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
 805                         udelay(10);
 806                         dev_err(mcbsp->dev, "McBSP%d transmitter not "
 807                                 "ready\n", mcbsp->id);
 808                         return -EAGAIN;
 809                 }
 810         }
 811
 812         /* Now we can push the data */
 813         if (tx_word_length > OMAP_MCBSP_WORD_16)
 814                 OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16);
 815         OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff);
 816
 817         /* We wait for the receiver to be ready */
 818         spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
 819         while (!(spcr1 & RRDY)) {
 820                 spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
 821                 if (attempts++ > 1000) {
 822                         /* We must reset the receiver */
 823                         OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 & (~RRST));
 824                         udelay(10);
 825                         OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
 826                         udelay(10);
 827                         dev_err(mcbsp->dev, "McBSP%d receiver not "
 828                                 "ready\n", mcbsp->id);
 829                         return -EAGAIN;
 830                 }
 831         }
 832
 833         /* Receiver is ready, let's read the dummy data */
 834         if (rx_word_length > OMAP_MCBSP_WORD_16)
 835                 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
 836         word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
 837
 838         return 0;
 839 }
 840 EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll);
 841
 842 int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
 843 {
 844         struct omap_mcbsp *mcbsp;
 845         u32 clock_word = 0;
 846         void __iomem *io_base;
 847         omap_mcbsp_word_length tx_word_length;
 848         omap_mcbsp_word_length rx_word_length;
 849         u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
 850
 851         if (!omap_mcbsp_check_valid_id(id)) {
 852                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 853                 return -ENODEV;
 854         }
 855
 856         mcbsp = id_to_mcbsp_ptr(id);
 857         io_base = mcbsp->io_base;
 858
 859         tx_word_length = mcbsp->tx_word_length;
 860         rx_word_length = mcbsp->rx_word_length;
 861
 862         if (tx_word_length != rx_word_length)
 863                 return -EINVAL;
 864
 865         /* First we wait for the transmitter to be ready */
 866         spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
 867         while (!(spcr2 & XRDY)) {
 868                 spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
 869                 if (attempts++ > 1000) {
 870                         /* We must reset the transmitter */
 871                         OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 & (~XRST));
 872                         udelay(10);
 873                         OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
 874                         udelay(10);
 875                         dev_err(mcbsp->dev, "McBSP%d transmitter not "
 876                                 "ready\n", mcbsp->id);
 877                         return -EAGAIN;
 878                 }
 879         }
 880
 881         /* We first need to enable the bus clock */
 882         if (tx_word_length > OMAP_MCBSP_WORD_16)
 883                 OMAP_MCBSP_WRITE(io_base, DXR2, clock_word >> 16);
 884         OMAP_MCBSP_WRITE(io_base, DXR1, clock_word & 0xffff);
 885
 886         /* We wait for the receiver to be ready */
 887         spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
 888         while (!(spcr1 & RRDY)) {
 889                 spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
 890                 if (attempts++ > 1000) {
 891                         /* We must reset the receiver */
 892                         OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 & (~RRST));
 893                         udelay(10);
 894                         OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
 895                         udelay(10);
 896                         dev_err(mcbsp->dev, "McBSP%d receiver not "
 897                                 "ready\n", mcbsp->id);
 898                         return -EAGAIN;
 899                 }
 900         }
 901
 902         /* Receiver is ready, there is something for us */
 903         if (rx_word_length > OMAP_MCBSP_WORD_16)
 904                 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
 905         word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
 906
 907         word[0] = (word_lsb | (word_msb << 16));
 908
 909         return 0;
 910 }
 911 EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll);
 912
 913 /*
 914  * Simple DMA based buffer rx/tx routines.
 915  * Nothing fancy, just a single buffer tx/rx through DMA.
 916  * The DMA resources are released once the transfer is done.
 917  * For anything fancier, you should use your own customized DMA
 918  * routines and callbacks.
 919  */
 920 int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer,
 921                                 unsigned int length)
 922 {
 923         struct omap_mcbsp *mcbsp;
 924         int dma_tx_ch;
 925         int src_port = 0;
 926         int dest_port = 0;
 927         int sync_dev = 0;
 928
 929         if (!omap_mcbsp_check_valid_id(id)) {
 930                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 931                 return -ENODEV;
 932         }
 933         mcbsp = id_to_mcbsp_ptr(id);
 934
 935         if (omap_request_dma(mcbsp->dma_tx_sync, "McBSP TX",
 936                                 omap_mcbsp_tx_dma_callback,
 937                                 mcbsp,
 938                                 &dma_tx_ch)) {
 939                 dev_err(mcbsp->dev, " Unable to request DMA channel for "
 940                                 "McBSP%d TX. Trying IRQ based TX\n",
 941                                 mcbsp->id);
 942                 return -EAGAIN;
 943         }
 944         mcbsp->dma_tx_lch = dma_tx_ch;
 945
 946         dev_err(mcbsp->dev, "McBSP%d TX DMA on channel %d\n", mcbsp->id,
 947                 dma_tx_ch);
 948
 949         init_completion(&mcbsp->tx_dma_completion);
 950
 951         if (cpu_class_is_omap1()) {
 952                 src_port = OMAP_DMA_PORT_TIPB;
 953                 dest_port = OMAP_DMA_PORT_EMIFF;
 954         }
 955         if (cpu_class_is_omap2())
 956                 sync_dev = mcbsp->dma_tx_sync;
 957
 958         omap_set_dma_transfer_params(mcbsp->dma_tx_lch,
 959                                      OMAP_DMA_DATA_TYPE_S16,
 960                                      length >> 1, 1,
 961                                      OMAP_DMA_SYNC_ELEMENT,
 962          sync_dev, 0);
 963
 964         omap_set_dma_dest_params(mcbsp->dma_tx_lch,
 965                                  src_port,
 966                                  OMAP_DMA_AMODE_CONSTANT,
 967                                  mcbsp->phys_base + OMAP_MCBSP_REG_DXR1,
 968                                  0, 0);
 969
 970         omap_set_dma_src_params(mcbsp->dma_tx_lch,
 971                                 dest_port,
 972                                 OMAP_DMA_AMODE_POST_INC,
 973                                 buffer,
 974                                 0, 0);
 975
 976         omap_start_dma(mcbsp->dma_tx_lch);
 977         wait_for_completion(&mcbsp->tx_dma_completion);
 978
 979         return 0;
 980 }
 981 EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
 982
 983 int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer,
 984                                 unsigned int length)
 985 {
 986         struct omap_mcbsp *mcbsp;
 987         int dma_rx_ch;
 988         int src_port = 0;
 989         int dest_port = 0;
 990         int sync_dev = 0;
 991
 992         if (!omap_mcbsp_check_valid_id(id)) {
 993                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 994                 return -ENODEV;
 995         }
 996         mcbsp = id_to_mcbsp_ptr(id);
 997
 998         if (omap_request_dma(mcbsp->dma_rx_sync, "McBSP RX",
 999                                 omap_mcbsp_rx_dma_callback,
1000                                 mcbsp,
1001                                 &dma_rx_ch)) {
1002                 dev_err(mcbsp->dev, "Unable to request DMA channel for "
1003                                 "McBSP%d RX. Trying IRQ based RX\n",
1004                                 mcbsp->id);
1005                 return -EAGAIN;
1006         }
1007         mcbsp->dma_rx_lch = dma_rx_ch;
1008
1009         dev_err(mcbsp->dev, "McBSP%d RX DMA on channel %d\n", mcbsp->id,
1010                 dma_rx_ch);
1011
1012         init_completion(&mcbsp->rx_dma_completion);
1013
1014         if (cpu_class_is_omap1()) {
1015                 src_port = OMAP_DMA_PORT_TIPB;
1016                 dest_port = OMAP_DMA_PORT_EMIFF;
1017         }
1018         if (cpu_class_is_omap2())
1019                 sync_dev = mcbsp->dma_rx_sync;
1020
1021         omap_set_dma_transfer_params(mcbsp->dma_rx_lch,
1022                                         OMAP_DMA_DATA_TYPE_S16,
1023                                         length >> 1, 1,
1024                                         OMAP_DMA_SYNC_ELEMENT,
1025                                         sync_dev, 0);
1026
1027         omap_set_dma_src_params(mcbsp->dma_rx_lch,
1028                                 src_port,
1029                                 OMAP_DMA_AMODE_CONSTANT,
1030                                 mcbsp->phys_base + OMAP_MCBSP_REG_DRR1,
1031                                 0, 0);
1032
1033         omap_set_dma_dest_params(mcbsp->dma_rx_lch,
1034                                         dest_port,
1035                                         OMAP_DMA_AMODE_POST_INC,
1036                                         buffer,
1037                                         0, 0);
1038
1039         omap_start_dma(mcbsp->dma_rx_lch);
1040         wait_for_completion(&mcbsp->rx_dma_completion);
1041
1042         return 0;
1043 }
1044 EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
1045
1046 /*
1047  * SPI wrapper.
1048  * Since SPI setup is much simpler than the generic McBSP one,
1049  * this wrapper just need an omap_mcbsp_spi_cfg structure as an input.
1050  * Once this is done, you can call omap_mcbsp_start().
1051  */
1052 void omap_mcbsp_set_spi_mode(unsigned int id,
1053                                 const struct omap_mcbsp_spi_cfg *spi_cfg)
1054 {
1055         struct omap_mcbsp *mcbsp;
1056         struct omap_mcbsp_reg_cfg mcbsp_cfg;
1057
1058         if (!omap_mcbsp_check_valid_id(id)) {
1059                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1060                 return;
1061         }
1062         mcbsp = id_to_mcbsp_ptr(id);
1063
1064         memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg));
1065
1066         /* SPI has only one frame */
1067         mcbsp_cfg.rcr1 |= (RWDLEN1(spi_cfg->word_length) | RFRLEN1(0));
1068         mcbsp_cfg.xcr1 |= (XWDLEN1(spi_cfg->word_length) | XFRLEN1(0));
1069
1070         /* Clock stop mode */
1071         if (spi_cfg->clk_stp_mode == OMAP_MCBSP_CLK_STP_MODE_NO_DELAY)
1072                 mcbsp_cfg.spcr1 |= (1 << 12);
1073         else
1074                 mcbsp_cfg.spcr1 |= (3 << 11);
1075
1076         /* Set clock parities */
1077         if (spi_cfg->rx_clock_polarity == OMAP_MCBSP_CLK_RISING)
1078                 mcbsp_cfg.pcr0 |= CLKRP;
1079         else
1080                 mcbsp_cfg.pcr0 &= ~CLKRP;
1081
1082         if (spi_cfg->tx_clock_polarity == OMAP_MCBSP_CLK_RISING)
1083                 mcbsp_cfg.pcr0 &= ~CLKXP;
1084         else
1085                 mcbsp_cfg.pcr0 |= CLKXP;
1086
1087         /* Set SCLKME to 0 and CLKSM to 1 */
1088         mcbsp_cfg.pcr0 &= ~SCLKME;
1089         mcbsp_cfg.srgr2 |= CLKSM;
1090
1091         /* Set FSXP */
1092         if (spi_cfg->fsx_polarity == OMAP_MCBSP_FS_ACTIVE_HIGH)
1093                 mcbsp_cfg.pcr0 &= ~FSXP;
1094         else
1095                 mcbsp_cfg.pcr0 |= FSXP;
1096
1097         if (spi_cfg->spi_mode == OMAP_MCBSP_SPI_MASTER) {
1098                 mcbsp_cfg.pcr0 |= CLKXM;
1099                 mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div - 1);
1100                 mcbsp_cfg.pcr0 |= FSXM;
1101                 mcbsp_cfg.srgr2 &= ~FSGM;
1102                 mcbsp_cfg.xcr2 |= XDATDLY(1);
1103                 mcbsp_cfg.rcr2 |= RDATDLY(1);
1104         } else {
1105                 mcbsp_cfg.pcr0 &= ~CLKXM;
1106                 mcbsp_cfg.srgr1 |= CLKGDV(1);
1107                 mcbsp_cfg.pcr0 &= ~FSXM;
1108                 mcbsp_cfg.xcr2 &= ~XDATDLY(3);
1109                 mcbsp_cfg.rcr2 &= ~RDATDLY(3);
1110         }
1111
1112         mcbsp_cfg.xcr2 &= ~XPHASE;
1113         mcbsp_cfg.rcr2 &= ~RPHASE;
1114
1115         omap_mcbsp_config(id, &mcbsp_cfg);
1116 }
1117 EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);
1118
1119 #ifdef CONFIG_ARCH_OMAP34XX
1120 #define max_thres(m)                    (mcbsp->pdata->buffer_size)
1121 #define valid_threshold(m, val)         ((val) <= max_thres(m))
1122 #define THRESHOLD_PROP_BUILDER(prop)                                    \
1123 static ssize_t prop##_show(struct device *dev,                          \
1124                         struct device_attribute *attr, char *buf)       \
1125 {                                                                       \
1126         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);                \
1127                                                                         \
1128         return sprintf(buf, "%u\n", mcbsp->prop);                       \
1129 }                                                                       \
1130                                                                         \
1131 static ssize_t prop##_store(struct device *dev,                         \
1132                                 struct device_attribute *attr,          \
1133                                 const char *buf, size_t size)           \
1134 {                                                                       \
1135         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);                \
1136         unsigned long val;                                              \
1137         int status;                                                     \
1138                                                                         \
1139         status = strict_strtoul(buf, 0, &val);                          \
1140         if (status)                                                     \
1141                 return status;                                          \
1142                                                                         \
1143         if (!valid_threshold(mcbsp, val))                               \
1144                 return -EDOM;                                           \
1145                                                                         \
1146         mcbsp->prop = val;                                              \
1147         return size;                                                    \
1148 }                                                                       \
1149                                                                         \
1150 static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store);
1151
1152 THRESHOLD_PROP_BUILDER(max_tx_thres);
1153 THRESHOLD_PROP_BUILDER(max_rx_thres);
1154
1155 static ssize_t dma_op_mode_show(struct device *dev,
1156                         struct device_attribute *attr, char *buf)
1157 {
1158         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1159         int dma_op_mode;
1160
1161         spin_lock_irq(&mcbsp->lock);
1162         dma_op_mode = mcbsp->dma_op_mode;
1163         spin_unlock_irq(&mcbsp->lock);
1164
1165         return sprintf(buf, "current mode: %d\n"
1166                         "possible mode values are:\n"
1167                         "%d - %s\n"
1168                         "%d - %s\n"
1169                         "%d - %s\n",
1170                         dma_op_mode,
1171                         MCBSP_DMA_MODE_ELEMENT, "element mode",
1172                         MCBSP_DMA_MODE_THRESHOLD, "threshold mode",
1173                         MCBSP_DMA_MODE_FRAME, "frame mode");
1174 }
1175
1176 static ssize_t dma_op_mode_store(struct device *dev,
1177                                 struct device_attribute *attr,
1178                                 const char *buf, size_t size)
1179 {
1180         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1181         unsigned long val;
1182         int status;
1183
1184         status = strict_strtoul(buf, 0, &val);
1185         if (status)
1186                 return status;
1187
1188         spin_lock_irq(&mcbsp->lock);
1189
1190         if (!mcbsp->free) {
1191                 size = -EBUSY;
1192                 goto unlock;
1193         }
1194
1195         if (val > MCBSP_DMA_MODE_FRAME || val < MCBSP_DMA_MODE_ELEMENT) {
1196                 size = -EINVAL;
1197                 goto unlock;
1198         }
1199
1200         mcbsp->dma_op_mode = val;
1201
1202 unlock:
1203         spin_unlock_irq(&mcbsp->lock);
1204
1205         return size;
1206 }
1207
1208 static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store);
1209
1210 static const struct attribute *additional_attrs[] = {
1211         &dev_attr_max_tx_thres.attr,
1212         &dev_attr_max_rx_thres.attr,
1213         &dev_attr_dma_op_mode.attr,
1214         NULL,
1215 };
1216
1217 static const struct attribute_group additional_attr_group = {
1218         .attrs = (struct attribute **)additional_attrs,
1219 };
1220
1221 static inline int __devinit omap_additional_add(struct device *dev)
1222 {
1223         return sysfs_create_group(&dev->kobj, &additional_attr_group);
1224 }
1225
1226 static inline void __devexit omap_additional_remove(struct device *dev)
1227 {
1228         sysfs_remove_group(&dev->kobj, &additional_attr_group);
1229 }
1230
1231 static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp)
1232 {
1233         mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
1234         if (cpu_is_omap34xx()) {
1235                 mcbsp->max_tx_thres = max_thres(mcbsp);
1236                 mcbsp->max_rx_thres = max_thres(mcbsp);
1237                 /*
1238                  * REVISIT: Set dmap_op_mode to THRESHOLD as default
1239                  * for mcbsp2 instances.
1240                  */
1241                 if (omap_additional_add(mcbsp->dev))
1242                         dev_warn(mcbsp->dev,
1243                                 "Unable to create additional controls\n");
1244         } else {
1245                 mcbsp->max_tx_thres = -EINVAL;
1246                 mcbsp->max_rx_thres = -EINVAL;
1247         }
1248 }
1249
1250 static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp)
1251 {
1252         if (cpu_is_omap34xx())
1253                 omap_additional_remove(mcbsp->dev);
1254 }
1255 #else
1256 static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp) {}
1257 static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp) {}
1258 #endif /* CONFIG_ARCH_OMAP34XX */
1259
1260 /*
1261  * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
1262  * 730 has only 2 McBSP, and both of them are MPU peripherals.
1263  */
1264 static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
1265 {
1266         struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data;
1267         struct omap_mcbsp *mcbsp;
1268         int id = pdev->id - 1;
1269         int ret = 0;
1270
1271         if (!pdata) {
1272                 dev_err(&pdev->dev, "McBSP device initialized without"
1273                                 "platform data\n");
1274                 ret = -EINVAL;
1275                 goto exit;
1276         }
1277
1278         dev_dbg(&pdev->dev, "Initializing OMAP McBSP (%d).\n", pdev->id);
1279
1280         if (id >= omap_mcbsp_count) {
1281                 dev_err(&pdev->dev, "Invalid McBSP device id (%d)\n", id);
1282                 ret = -EINVAL;
1283                 goto exit;
1284         }
1285
1286         mcbsp = kzalloc(sizeof(struct omap_mcbsp), GFP_KERNEL);
1287         if (!mcbsp) {
1288                 ret = -ENOMEM;
1289                 goto exit;
1290         }
1291
1292         spin_lock_init(&mcbsp->lock);
1293         mcbsp->id = id + 1;
1294         mcbsp->free = 1;
1295         mcbsp->dma_tx_lch = -1;
1296         mcbsp->dma_rx_lch = -1;
1297
1298         mcbsp->phys_base = pdata->phys_base;
1299         mcbsp->io_base = ioremap(pdata->phys_base, SZ_4K);
1300         if (!mcbsp->io_base) {
1301                 ret = -ENOMEM;
1302                 goto err_ioremap;
1303         }
1304
1305         /* Default I/O is IRQ based */
1306         mcbsp->io_type = OMAP_MCBSP_IRQ_IO;
1307         mcbsp->tx_irq = pdata->tx_irq;
1308         mcbsp->rx_irq = pdata->rx_irq;
1309         mcbsp->dma_rx_sync = pdata->dma_rx_sync;
1310         mcbsp->dma_tx_sync = pdata->dma_tx_sync;
1311
1312         mcbsp->iclk = clk_get(&pdev->dev, "ick");
1313         if (IS_ERR(mcbsp->iclk)) {
1314                 ret = PTR_ERR(mcbsp->iclk);
1315                 dev_err(&pdev->dev, "unable to get ick: %d\n", ret);
1316                 goto err_iclk;
1317         }
1318
1319         mcbsp->fclk = clk_get(&pdev->dev, "fck");
1320         if (IS_ERR(mcbsp->fclk)) {
1321                 ret = PTR_ERR(mcbsp->fclk);
1322                 dev_err(&pdev->dev, "unable to get fck: %d\n", ret);
1323                 goto err_fclk;
1324         }
1325
1326         mcbsp->pdata = pdata;
1327         mcbsp->dev = &pdev->dev;
1328         mcbsp_ptr[id] = mcbsp;
1329         platform_set_drvdata(pdev, mcbsp);
1330
1331         /* Initialize mcbsp properties for OMAP34XX if needed / applicable */
1332         omap34xx_device_init(mcbsp);
1333
1334         return 0;
1335
1336 err_fclk:
1337         clk_put(mcbsp->iclk);
1338 err_iclk:
1339         iounmap(mcbsp->io_base);
1340 err_ioremap:
1341         kfree(mcbsp);
1342 exit:
1343         return ret;
1344 }
1345
1346 static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
1347 {
1348         struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
1349
1350         platform_set_drvdata(pdev, NULL);
1351         if (mcbsp) {
1352
1353                 if (mcbsp->pdata && mcbsp->pdata->ops &&
1354                                 mcbsp->pdata->ops->free)
1355                         mcbsp->pdata->ops->free(mcbsp->id);
1356
1357                 omap34xx_device_exit(mcbsp);
1358
1359                 clk_disable(mcbsp->fclk);
1360                 clk_disable(mcbsp->iclk);
1361                 clk_put(mcbsp->fclk);
1362                 clk_put(mcbsp->iclk);
1363
1364                 iounmap(mcbsp->io_base);
1365
1366                 mcbsp->fclk = NULL;
1367                 mcbsp->iclk = NULL;
1368                 mcbsp->free = 0;
1369                 mcbsp->dev = NULL;
1370         }
1371
1372         return 0;
1373 }
1374
1375 static struct platform_driver omap_mcbsp_driver = {
1376         .probe          = omap_mcbsp_probe,
1377         .remove         = __devexit_p(omap_mcbsp_remove),
1378         .driver         = {
1379                 .name   = "omap-mcbsp",
1380         },
1381 };
1382
1383 int __init omap_mcbsp_init(void)
1384 {
1385         /* Register the McBSP driver */
1386         return platform_driver_register(&omap_mcbsp_driver);
1387 }