arch/arm/plat-omap/mcbsp.c

   1 /*
   2  * linux/arch/arm/plat-omap/mcbsp.c
   3  *
   4  * Copyright (C) 2004 Nokia Corporation
   5  * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
   6  *
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * Multichannel mode not supported.
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/init.h>
  17 #include <linux/device.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/err.h>
  21 #include <linux/clk.h>
  22 #include <linux/delay.h>
  23 #include <linux/io.h>
  24 #include <linux/slab.h>
  25
  26 #include <plat/mcbsp.h>
  27 #include <linux/pm_runtime.h>
  28
  29 /* XXX These "sideways" includes are a sign that something is wrong */
  30 #include "../mach-omap2/cm2xxx_3xxx.h"
  31 #include "../mach-omap2/cm-regbits-34xx.h"
  32
  33 struct omap_mcbsp **mcbsp_ptr;
  34 int omap_mcbsp_count, omap_mcbsp_cache_size;
  35
  36 static void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
  37 {
  38         void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step;
  39
  40         if (mcbsp->pdata->reg_size == 2) {
  41                 ((u16 *)mcbsp->reg_cache)[reg] = (u16)val;
  42                 __raw_writew((u16)val, addr);
  43         } else {
  44                 ((u32 *)mcbsp->reg_cache)[reg] = val;
  45                 __raw_writel(val, addr);
  46         }
  47 }
  48
  49 static int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache)
  50 {
  51         void __iomem *addr = mcbsp->io_base + reg * mcbsp->pdata->reg_step;
  52
  53         if (mcbsp->pdata->reg_size == 2) {
  54                 return !from_cache ? __raw_readw(addr) :
  55                                      ((u16 *)mcbsp->reg_cache)[reg];
  56         } else {
  57                 return !from_cache ? __raw_readl(addr) :
  58                                      ((u32 *)mcbsp->reg_cache)[reg];
  59         }
  60 }
  61
  62 #ifdef CONFIG_ARCH_OMAP3
  63 static void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
  64 {
  65         __raw_writel(val, mcbsp->st_data->io_base_st + reg);
  66 }
  67
  68 static int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg)
  69 {
  70         return __raw_readl(mcbsp->st_data->io_base_st + reg);
  71 }
  72 #endif
  73
  74 #define MCBSP_READ(mcbsp, reg) \
  75                 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 0)
  76 #define MCBSP_WRITE(mcbsp, reg, val) \
  77                 omap_mcbsp_write(mcbsp, OMAP_MCBSP_REG_##reg, val)
  78 #define MCBSP_READ_CACHE(mcbsp, reg) \
  79                 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1)
  80
  81 #define MCBSP_ST_READ(mcbsp, reg) \
  82                         omap_mcbsp_st_read(mcbsp, OMAP_ST_REG_##reg)
  83 #define MCBSP_ST_WRITE(mcbsp, reg, val) \
  84                         omap_mcbsp_st_write(mcbsp, OMAP_ST_REG_##reg, val)
  85
  86 static void omap_mcbsp_dump_reg(u8 id)
  87 {
  88         struct omap_mcbsp *mcbsp = id_to_mcbsp_ptr(id);
  89
  90         dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
  91         dev_dbg(mcbsp->dev, "DRR2:  0x%04x\n",
  92                         MCBSP_READ(mcbsp, DRR2));
  93         dev_dbg(mcbsp->dev, "DRR1:  0x%04x\n",
  94                         MCBSP_READ(mcbsp, DRR1));
  95         dev_dbg(mcbsp->dev, "DXR2:  0x%04x\n",
  96                         MCBSP_READ(mcbsp, DXR2));
  97         dev_dbg(mcbsp->dev, "DXR1:  0x%04x\n",
  98                         MCBSP_READ(mcbsp, DXR1));
  99         dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n",
 100                         MCBSP_READ(mcbsp, SPCR2));
 101         dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n",
 102                         MCBSP_READ(mcbsp, SPCR1));
 103         dev_dbg(mcbsp->dev, "RCR2:  0x%04x\n",
 104                         MCBSP_READ(mcbsp, RCR2));
 105         dev_dbg(mcbsp->dev, "RCR1:  0x%04x\n",
 106                         MCBSP_READ(mcbsp, RCR1));
 107         dev_dbg(mcbsp->dev, "XCR2:  0x%04x\n",
 108                         MCBSP_READ(mcbsp, XCR2));
 109         dev_dbg(mcbsp->dev, "XCR1:  0x%04x\n",
 110                         MCBSP_READ(mcbsp, XCR1));
 111         dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n",
 112                         MCBSP_READ(mcbsp, SRGR2));
 113         dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n",
 114                         MCBSP_READ(mcbsp, SRGR1));
 115         dev_dbg(mcbsp->dev, "PCR0:  0x%04x\n",
 116                         MCBSP_READ(mcbsp, PCR0));
 117         dev_dbg(mcbsp->dev, "***********************\n");
 118 }
 119
 120 static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
 121 {
 122         struct omap_mcbsp *mcbsp_tx = dev_id;
 123         u16 irqst_spcr2;
 124
 125         irqst_spcr2 = MCBSP_READ(mcbsp_tx, SPCR2);
 126         dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
 127
 128         if (irqst_spcr2 & XSYNC_ERR) {
 129                 dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n",
 130                         irqst_spcr2);
 131                 /* Writing zero to XSYNC_ERR clears the IRQ */
 132                 MCBSP_WRITE(mcbsp_tx, SPCR2, MCBSP_READ_CACHE(mcbsp_tx, SPCR2));
 133         }
 134
 135         return IRQ_HANDLED;
 136 }
 137
 138 static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
 139 {
 140         struct omap_mcbsp *mcbsp_rx = dev_id;
 141         u16 irqst_spcr1;
 142
 143         irqst_spcr1 = MCBSP_READ(mcbsp_rx, SPCR1);
 144         dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
 145
 146         if (irqst_spcr1 & RSYNC_ERR) {
 147                 dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n",
 148                         irqst_spcr1);
 149                 /* Writing zero to RSYNC_ERR clears the IRQ */
 150                 MCBSP_WRITE(mcbsp_rx, SPCR1, MCBSP_READ_CACHE(mcbsp_rx, SPCR1));
 151         }
 152
 153         return IRQ_HANDLED;
 154 }
 155
 156 /*
 157  * omap_mcbsp_config simply write a config to the
 158  * appropriate McBSP.
 159  * You either call this function or set the McBSP registers
 160  * by yourself before calling omap_mcbsp_start().
 161  */
 162 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
 163 {
 164         struct omap_mcbsp *mcbsp;
 165
 166         if (!omap_mcbsp_check_valid_id(id)) {
 167                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 168                 return;
 169         }
 170         mcbsp = id_to_mcbsp_ptr(id);
 171
 172         dev_dbg(mcbsp->dev, "Configuring McBSP%d  phys_base: 0x%08lx\n",
 173                         mcbsp->id, mcbsp->phys_base);
 174
 175         /* We write the given config */
 176         MCBSP_WRITE(mcbsp, SPCR2, config->spcr2);
 177         MCBSP_WRITE(mcbsp, SPCR1, config->spcr1);
 178         MCBSP_WRITE(mcbsp, RCR2, config->rcr2);
 179         MCBSP_WRITE(mcbsp, RCR1, config->rcr1);
 180         MCBSP_WRITE(mcbsp, XCR2, config->xcr2);
 181         MCBSP_WRITE(mcbsp, XCR1, config->xcr1);
 182         MCBSP_WRITE(mcbsp, SRGR2, config->srgr2);
 183         MCBSP_WRITE(mcbsp, SRGR1, config->srgr1);
 184         MCBSP_WRITE(mcbsp, MCR2, config->mcr2);
 185         MCBSP_WRITE(mcbsp, MCR1, config->mcr1);
 186         MCBSP_WRITE(mcbsp, PCR0, config->pcr0);
 187         if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
 188                 MCBSP_WRITE(mcbsp, XCCR, config->xccr);
 189                 MCBSP_WRITE(mcbsp, RCCR, config->rccr);
 190         }
 191 }
 192 EXPORT_SYMBOL(omap_mcbsp_config);
 193
 194 /**
 195  * omap_mcbsp_dma_params - returns the dma channel number
 196  * @id - mcbsp id
 197  * @stream - indicates the direction of data flow (rx or tx)
 198  *
 199  * Returns the dma channel number for the rx channel or tx channel
 200  * based on the value of @stream for the requested mcbsp given by @id
 201  */
 202 int omap_mcbsp_dma_ch_params(unsigned int id, unsigned int stream)
 203 {
 204         struct omap_mcbsp *mcbsp;
 205
 206         if (!omap_mcbsp_check_valid_id(id)) {
 207                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 208                 return -ENODEV;
 209         }
 210         mcbsp = id_to_mcbsp_ptr(id);
 211
 212         if (stream)
 213                 return mcbsp->dma_rx_sync;
 214         else
 215                 return mcbsp->dma_tx_sync;
 216 }
 217 EXPORT_SYMBOL(omap_mcbsp_dma_ch_params);
 218
 219 /**
 220  * omap_mcbsp_dma_reg_params - returns the address of mcbsp data register
 221  * @id - mcbsp id
 222  * @stream - indicates the direction of data flow (rx or tx)
 223  *
 224  * Returns the address of mcbsp data transmit register or data receive register
 225  * to be used by DMA for transferring/receiving data based on the value of
 226  * @stream for the requested mcbsp given by @id
 227  */
 228 int omap_mcbsp_dma_reg_params(unsigned int id, unsigned int stream)
 229 {
 230         struct omap_mcbsp *mcbsp;
 231         int data_reg;
 232
 233         if (!omap_mcbsp_check_valid_id(id)) {
 234                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 235                 return -ENODEV;
 236         }
 237         mcbsp = id_to_mcbsp_ptr(id);
 238
 239         if (mcbsp->pdata->reg_size == 2) {
 240                 if (stream)
 241                         data_reg = OMAP_MCBSP_REG_DRR1;
 242                 else
 243                         data_reg = OMAP_MCBSP_REG_DXR1;
 244         } else {
 245                 if (stream)
 246                         data_reg = OMAP_MCBSP_REG_DRR;
 247                 else
 248                         data_reg = OMAP_MCBSP_REG_DXR;
 249         }
 250
 251         return mcbsp->phys_dma_base + data_reg * mcbsp->pdata->reg_step;
 252 }
 253 EXPORT_SYMBOL(omap_mcbsp_dma_reg_params);
 254
 255 #ifdef CONFIG_ARCH_OMAP3
 256 static void omap_st_on(struct omap_mcbsp *mcbsp)
 257 {
 258         unsigned int w;
 259
 260         /*
 261          * Sidetone uses McBSP ICLK - which must not idle when sidetones
 262          * are enabled or sidetones start sounding ugly.
 263          */
 264         w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
 265         w &= ~(1 << (mcbsp->id - 2));
 266         omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
 267
 268         /* Enable McBSP Sidetone */
 269         w = MCBSP_READ(mcbsp, SSELCR);
 270         MCBSP_WRITE(mcbsp, SSELCR, w | SIDETONEEN);
 271
 272         /* Enable Sidetone from Sidetone Core */
 273         w = MCBSP_ST_READ(mcbsp, SSELCR);
 274         MCBSP_ST_WRITE(mcbsp, SSELCR, w | ST_SIDETONEEN);
 275 }
 276
 277 static void omap_st_off(struct omap_mcbsp *mcbsp)
 278 {
 279         unsigned int w;
 280
 281         w = MCBSP_ST_READ(mcbsp, SSELCR);
 282         MCBSP_ST_WRITE(mcbsp, SSELCR, w & ~(ST_SIDETONEEN));
 283
 284         w = MCBSP_READ(mcbsp, SSELCR);
 285         MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN));
 286
 287         w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
 288         w |= 1 << (mcbsp->id - 2);
 289         omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
 290 }
 291
 292 static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir)
 293 {
 294         u16 val, i;
 295
 296         val = MCBSP_ST_READ(mcbsp, SSELCR);
 297
 298         if (val & ST_COEFFWREN)
 299                 MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
 300
 301         MCBSP_ST_WRITE(mcbsp, SSELCR, val | ST_COEFFWREN);
 302
 303         for (i = 0; i < 128; i++)
 304                 MCBSP_ST_WRITE(mcbsp, SFIRCR, fir[i]);
 305
 306         i = 0;
 307
 308         val = MCBSP_ST_READ(mcbsp, SSELCR);
 309         while (!(val & ST_COEFFWRDONE) && (++i < 1000))
 310                 val = MCBSP_ST_READ(mcbsp, SSELCR);
 311
 312         MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
 313
 314         if (i == 1000)
 315                 dev_err(mcbsp->dev, "McBSP FIR load error!\n");
 316 }
 317
 318 static void omap_st_chgain(struct omap_mcbsp *mcbsp)
 319 {
 320         u16 w;
 321         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 322
 323         w = MCBSP_ST_READ(mcbsp, SSELCR);
 324
 325         MCBSP_ST_WRITE(mcbsp, SGAINCR, ST_CH0GAIN(st_data->ch0gain) | \
 326                       ST_CH1GAIN(st_data->ch1gain));
 327 }
 328
 329 int omap_st_set_chgain(unsigned int id, int channel, s16 chgain)
 330 {
 331         struct omap_mcbsp *mcbsp;
 332         struct omap_mcbsp_st_data *st_data;
 333         int ret = 0;
 334
 335         if (!omap_mcbsp_check_valid_id(id)) {
 336                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 337                 return -ENODEV;
 338         }
 339
 340         mcbsp = id_to_mcbsp_ptr(id);
 341         st_data = mcbsp->st_data;
 342
 343         if (!st_data)
 344                 return -ENOENT;
 345
 346         spin_lock_irq(&mcbsp->lock);
 347         if (channel == 0)
 348                 st_data->ch0gain = chgain;
 349         else if (channel == 1)
 350                 st_data->ch1gain = chgain;
 351         else
 352                 ret = -EINVAL;
 353
 354         if (st_data->enabled)
 355                 omap_st_chgain(mcbsp);
 356         spin_unlock_irq(&mcbsp->lock);
 357
 358         return ret;
 359 }
 360 EXPORT_SYMBOL(omap_st_set_chgain);
 361
 362 int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain)
 363 {
 364         struct omap_mcbsp *mcbsp;
 365         struct omap_mcbsp_st_data *st_data;
 366         int ret = 0;
 367
 368         if (!omap_mcbsp_check_valid_id(id)) {
 369                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 370                 return -ENODEV;
 371         }
 372
 373         mcbsp = id_to_mcbsp_ptr(id);
 374         st_data = mcbsp->st_data;
 375
 376         if (!st_data)
 377                 return -ENOENT;
 378
 379         spin_lock_irq(&mcbsp->lock);
 380         if (channel == 0)
 381                 *chgain = st_data->ch0gain;
 382         else if (channel == 1)
 383                 *chgain = st_data->ch1gain;
 384         else
 385                 ret = -EINVAL;
 386         spin_unlock_irq(&mcbsp->lock);
 387
 388         return ret;
 389 }
 390 EXPORT_SYMBOL(omap_st_get_chgain);
 391
 392 static int omap_st_start(struct omap_mcbsp *mcbsp)
 393 {
 394         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 395
 396         if (st_data && st_data->enabled && !st_data->running) {
 397                 omap_st_fir_write(mcbsp, st_data->taps);
 398                 omap_st_chgain(mcbsp);
 399
 400                 if (!mcbsp->free) {
 401                         omap_st_on(mcbsp);
 402                         st_data->running = 1;
 403                 }
 404         }
 405
 406         return 0;
 407 }
 408
 409 int omap_st_enable(unsigned int id)
 410 {
 411         struct omap_mcbsp *mcbsp;
 412         struct omap_mcbsp_st_data *st_data;
 413
 414         if (!omap_mcbsp_check_valid_id(id)) {
 415                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 416                 return -ENODEV;
 417         }
 418
 419         mcbsp = id_to_mcbsp_ptr(id);
 420         st_data = mcbsp->st_data;
 421
 422         if (!st_data)
 423                 return -ENODEV;
 424
 425         spin_lock_irq(&mcbsp->lock);
 426         st_data->enabled = 1;
 427         omap_st_start(mcbsp);
 428         spin_unlock_irq(&mcbsp->lock);
 429
 430         return 0;
 431 }
 432 EXPORT_SYMBOL(omap_st_enable);
 433
 434 static int omap_st_stop(struct omap_mcbsp *mcbsp)
 435 {
 436         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 437
 438         if (st_data && st_data->running) {
 439                 if (!mcbsp->free) {
 440                         omap_st_off(mcbsp);
 441                         st_data->running = 0;
 442                 }
 443         }
 444
 445         return 0;
 446 }
 447
 448 int omap_st_disable(unsigned int id)
 449 {
 450         struct omap_mcbsp *mcbsp;
 451         struct omap_mcbsp_st_data *st_data;
 452         int ret = 0;
 453
 454         if (!omap_mcbsp_check_valid_id(id)) {
 455                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 456                 return -ENODEV;
 457         }
 458
 459         mcbsp = id_to_mcbsp_ptr(id);
 460         st_data = mcbsp->st_data;
 461
 462         if (!st_data)
 463                 return -ENODEV;
 464
 465         spin_lock_irq(&mcbsp->lock);
 466         omap_st_stop(mcbsp);
 467         st_data->enabled = 0;
 468         spin_unlock_irq(&mcbsp->lock);
 469
 470         return ret;
 471 }
 472 EXPORT_SYMBOL(omap_st_disable);
 473
 474 int omap_st_is_enabled(unsigned int id)
 475 {
 476         struct omap_mcbsp *mcbsp;
 477         struct omap_mcbsp_st_data *st_data;
 478
 479         if (!omap_mcbsp_check_valid_id(id)) {
 480                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 481                 return -ENODEV;
 482         }
 483
 484         mcbsp = id_to_mcbsp_ptr(id);
 485         st_data = mcbsp->st_data;
 486
 487         if (!st_data)
 488                 return -ENODEV;
 489
 490
 491         return st_data->enabled;
 492 }
 493 EXPORT_SYMBOL(omap_st_is_enabled);
 494
 495 /*
 496  * omap_mcbsp_set_rx_threshold configures the transmit threshold in words.
 497  * The threshold parameter is 1 based, and it is converted (threshold - 1)
 498  * for the THRSH2 register.
 499  */
 500 void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
 501 {
 502         struct omap_mcbsp *mcbsp;
 503
 504         if (!cpu_is_omap34xx() && !cpu_is_omap44xx())
 505                 return;
 506
 507         if (!omap_mcbsp_check_valid_id(id)) {
 508                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 509                 return;
 510         }
 511         mcbsp = id_to_mcbsp_ptr(id);
 512
 513         if (threshold && threshold <= mcbsp->max_tx_thres)
 514                 MCBSP_WRITE(mcbsp, THRSH2, threshold - 1);
 515 }
 516 EXPORT_SYMBOL(omap_mcbsp_set_tx_threshold);
 517
 518 /*
 519  * omap_mcbsp_set_rx_threshold configures the receive threshold in words.
 520  * The threshold parameter is 1 based, and it is converted (threshold - 1)
 521  * for the THRSH1 register.
 522  */
 523 void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
 524 {
 525         struct omap_mcbsp *mcbsp;
 526
 527         if (!cpu_is_omap34xx() && !cpu_is_omap44xx())
 528                 return;
 529
 530         if (!omap_mcbsp_check_valid_id(id)) {
 531                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 532                 return;
 533         }
 534         mcbsp = id_to_mcbsp_ptr(id);
 535
 536         if (threshold && threshold <= mcbsp->max_rx_thres)
 537                 MCBSP_WRITE(mcbsp, THRSH1, threshold - 1);
 538 }
 539 EXPORT_SYMBOL(omap_mcbsp_set_rx_threshold);
 540
 541 /*
 542  * omap_mcbsp_get_max_tx_thres just return the current configured
 543  * maximum threshold for transmission
 544  */
 545 u16 omap_mcbsp_get_max_tx_threshold(unsigned int id)
 546 {
 547         struct omap_mcbsp *mcbsp;
 548
 549         if (!omap_mcbsp_check_valid_id(id)) {
 550                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 551                 return -ENODEV;
 552         }
 553         mcbsp = id_to_mcbsp_ptr(id);
 554
 555         return mcbsp->max_tx_thres;
 556 }
 557 EXPORT_SYMBOL(omap_mcbsp_get_max_tx_threshold);
 558
 559 /*
 560  * omap_mcbsp_get_max_rx_thres just return the current configured
 561  * maximum threshold for reception
 562  */
 563 u16 omap_mcbsp_get_max_rx_threshold(unsigned int id)
 564 {
 565         struct omap_mcbsp *mcbsp;
 566
 567         if (!omap_mcbsp_check_valid_id(id)) {
 568                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 569                 return -ENODEV;
 570         }
 571         mcbsp = id_to_mcbsp_ptr(id);
 572
 573         return mcbsp->max_rx_thres;
 574 }
 575 EXPORT_SYMBOL(omap_mcbsp_get_max_rx_threshold);
 576
 577 u16 omap_mcbsp_get_fifo_size(unsigned int id)
 578 {
 579         struct omap_mcbsp *mcbsp;
 580
 581         if (!omap_mcbsp_check_valid_id(id)) {
 582                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 583                 return -ENODEV;
 584         }
 585         mcbsp = id_to_mcbsp_ptr(id);
 586
 587         return mcbsp->pdata->buffer_size;
 588 }
 589 EXPORT_SYMBOL(omap_mcbsp_get_fifo_size);
 590
 591 /*
 592  * omap_mcbsp_get_tx_delay returns the number of used slots in the McBSP FIFO
 593  */
 594 u16 omap_mcbsp_get_tx_delay(unsigned int id)
 595 {
 596         struct omap_mcbsp *mcbsp;
 597         u16 buffstat;
 598
 599         if (!omap_mcbsp_check_valid_id(id)) {
 600                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 601                 return -ENODEV;
 602         }
 603         mcbsp = id_to_mcbsp_ptr(id);
 604
 605         /* Returns the number of free locations in the buffer */
 606         buffstat = MCBSP_READ(mcbsp, XBUFFSTAT);
 607
 608         /* Number of slots are different in McBSP ports */
 609         return mcbsp->pdata->buffer_size - buffstat;
 610 }
 611 EXPORT_SYMBOL(omap_mcbsp_get_tx_delay);
 612
 613 /*
 614  * omap_mcbsp_get_rx_delay returns the number of free slots in the McBSP FIFO
 615  * to reach the threshold value (when the DMA will be triggered to read it)
 616  */
 617 u16 omap_mcbsp_get_rx_delay(unsigned int id)
 618 {
 619         struct omap_mcbsp *mcbsp;
 620         u16 buffstat, threshold;
 621
 622         if (!omap_mcbsp_check_valid_id(id)) {
 623                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 624                 return -ENODEV;
 625         }
 626         mcbsp = id_to_mcbsp_ptr(id);
 627
 628         /* Returns the number of used locations in the buffer */
 629         buffstat = MCBSP_READ(mcbsp, RBUFFSTAT);
 630         /* RX threshold */
 631         threshold = MCBSP_READ(mcbsp, THRSH1);
 632
 633         /* Return the number of location till we reach the threshold limit */
 634         if (threshold <= buffstat)
 635                 return 0;
 636         else
 637                 return threshold - buffstat;
 638 }
 639 EXPORT_SYMBOL(omap_mcbsp_get_rx_delay);
 640
 641 /*
 642  * omap_mcbsp_get_dma_op_mode just return the current configured
 643  * operating mode for the mcbsp channel
 644  */
 645 int omap_mcbsp_get_dma_op_mode(unsigned int id)
 646 {
 647         struct omap_mcbsp *mcbsp;
 648         int dma_op_mode;
 649
 650         if (!omap_mcbsp_check_valid_id(id)) {
 651                 printk(KERN_ERR "%s: Invalid id (%u)\n", __func__, id + 1);
 652                 return -ENODEV;
 653         }
 654         mcbsp = id_to_mcbsp_ptr(id);
 655
 656         dma_op_mode = mcbsp->dma_op_mode;
 657
 658         return dma_op_mode;
 659 }
 660 EXPORT_SYMBOL(omap_mcbsp_get_dma_op_mode);
 661
 662 static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp)
 663 {
 664         /*
 665          * Enable wakup behavior, smart idle and all wakeups
 666          * REVISIT: some wakeups may be unnecessary
 667          */
 668         if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
 669                 MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
 670         }
 671 }
 672
 673 static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp)
 674 {
 675         /*
 676          * Disable wakup behavior, smart idle and all wakeups
 677          */
 678         if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
 679                 /*
 680                  * HW bug workaround - If no_idle mode is taken, we need to
 681                  * go to smart_idle before going to always_idle, or the
 682                  * device will not hit retention anymore.
 683                  */
 684
 685                 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
 686         }
 687 }
 688 #else
 689 static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp) {}
 690 static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp) {}
 691 static inline void omap_st_start(struct omap_mcbsp *mcbsp) {}
 692 static inline void omap_st_stop(struct omap_mcbsp *mcbsp) {}
 693 #endif
 694
 695 int omap_mcbsp_request(unsigned int id)
 696 {
 697         struct omap_mcbsp *mcbsp;
 698         void *reg_cache;
 699         int err;
 700
 701         if (!omap_mcbsp_check_valid_id(id)) {
 702                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 703                 return -ENODEV;
 704         }
 705         mcbsp = id_to_mcbsp_ptr(id);
 706
 707         reg_cache = kzalloc(omap_mcbsp_cache_size, GFP_KERNEL);
 708         if (!reg_cache) {
 709                 return -ENOMEM;
 710         }
 711
 712         spin_lock(&mcbsp->lock);
 713         if (!mcbsp->free) {
 714                 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
 715                         mcbsp->id);
 716                 err = -EBUSY;
 717                 goto err_kfree;
 718         }
 719
 720         mcbsp->free = false;
 721         mcbsp->reg_cache = reg_cache;
 722         spin_unlock(&mcbsp->lock);
 723
 724         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
 725                 mcbsp->pdata->ops->request(id);
 726
 727         pm_runtime_get_sync(mcbsp->dev);
 728
 729         /* Do procedure specific to omap34xx arch, if applicable */
 730         omap34xx_mcbsp_request(mcbsp);
 731
 732         /*
 733          * Make sure that transmitter, receiver and sample-rate generator are
 734          * not running before activating IRQs.
 735          */
 736         MCBSP_WRITE(mcbsp, SPCR1, 0);
 737         MCBSP_WRITE(mcbsp, SPCR2, 0);
 738
 739         err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler,
 740                                 0, "McBSP", (void *)mcbsp);
 741         if (err != 0) {
 742                 dev_err(mcbsp->dev, "Unable to request TX IRQ %d "
 743                                 "for McBSP%d\n", mcbsp->tx_irq,
 744                                 mcbsp->id);
 745                 goto err_clk_disable;
 746         }
 747
 748         if (mcbsp->rx_irq) {
 749                 err = request_irq(mcbsp->rx_irq,
 750                                 omap_mcbsp_rx_irq_handler,
 751                                 0, "McBSP", (void *)mcbsp);
 752                 if (err != 0) {
 753                         dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
 754                                         "for McBSP%d\n", mcbsp->rx_irq,
 755                                         mcbsp->id);
 756                         goto err_free_irq;
 757                 }
 758         }
 759
 760         return 0;
 761 err_free_irq:
 762         free_irq(mcbsp->tx_irq, (void *)mcbsp);
 763 err_clk_disable:
 764         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
 765                 mcbsp->pdata->ops->free(id);
 766
 767         /* Do procedure specific to omap34xx arch, if applicable */
 768         omap34xx_mcbsp_free(mcbsp);
 769
 770         pm_runtime_put_sync(mcbsp->dev);
 771
 772         spin_lock(&mcbsp->lock);
 773         mcbsp->free = true;
 774         mcbsp->reg_cache = NULL;
 775 err_kfree:
 776         spin_unlock(&mcbsp->lock);
 777         kfree(reg_cache);
 778
 779         return err;
 780 }
 781 EXPORT_SYMBOL(omap_mcbsp_request);
 782
 783 void omap_mcbsp_free(unsigned int id)
 784 {
 785         struct omap_mcbsp *mcbsp;
 786         void *reg_cache;
 787
 788         if (!omap_mcbsp_check_valid_id(id)) {
 789                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 790                 return;
 791         }
 792         mcbsp = id_to_mcbsp_ptr(id);
 793
 794         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
 795                 mcbsp->pdata->ops->free(id);
 796
 797         /* Do procedure specific to omap34xx arch, if applicable */
 798         omap34xx_mcbsp_free(mcbsp);
 799
 800         pm_runtime_put_sync(mcbsp->dev);
 801
 802         if (mcbsp->rx_irq)
 803                 free_irq(mcbsp->rx_irq, (void *)mcbsp);
 804         free_irq(mcbsp->tx_irq, (void *)mcbsp);
 805
 806         reg_cache = mcbsp->reg_cache;
 807
 808         spin_lock(&mcbsp->lock);
 809         if (mcbsp->free)
 810                 dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id);
 811         else
 812                 mcbsp->free = true;
 813         mcbsp->reg_cache = NULL;
 814         spin_unlock(&mcbsp->lock);
 815
 816         if (reg_cache)
 817                 kfree(reg_cache);
 818 }
 819 EXPORT_SYMBOL(omap_mcbsp_free);
 820
 821 /*
 822  * Here we start the McBSP, by enabling transmitter, receiver or both.
 823  * If no transmitter or receiver is active prior calling, then sample-rate
 824  * generator and frame sync are started.
 825  */
 826 void omap_mcbsp_start(unsigned int id, int tx, int rx)
 827 {
 828         struct omap_mcbsp *mcbsp;
 829         int enable_srg = 0;
 830         u16 w;
 831
 832         if (!omap_mcbsp_check_valid_id(id)) {
 833                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 834                 return;
 835         }
 836         mcbsp = id_to_mcbsp_ptr(id);
 837
 838         if (cpu_is_omap34xx())
 839                 omap_st_start(mcbsp);
 840
 841         /* Only enable SRG, if McBSP is master */
 842         w = MCBSP_READ_CACHE(mcbsp, PCR0);
 843         if (w & (FSXM | FSRM | CLKXM | CLKRM))
 844                 enable_srg = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
 845                                 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
 846
 847         if (enable_srg) {
 848                 /* Start the sample generator */
 849                 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 850                 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6));
 851         }
 852
 853         /* Enable transmitter and receiver */
 854         tx &= 1;
 855         w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 856         MCBSP_WRITE(mcbsp, SPCR2, w | tx);
 857
 858         rx &= 1;
 859         w = MCBSP_READ_CACHE(mcbsp, SPCR1);
 860         MCBSP_WRITE(mcbsp, SPCR1, w | rx);
 861
 862         /*
 863          * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
 864          * REVISIT: 100us may give enough time for two CLKSRG, however
 865          * due to some unknown PM related, clock gating etc. reason it
 866          * is now at 500us.
 867          */
 868         udelay(500);
 869
 870         if (enable_srg) {
 871                 /* Start frame sync */
 872                 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 873                 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
 874         }
 875
 876         if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
 877                 /* Release the transmitter and receiver */
 878                 w = MCBSP_READ_CACHE(mcbsp, XCCR);
 879                 w &= ~(tx ? XDISABLE : 0);
 880                 MCBSP_WRITE(mcbsp, XCCR, w);
 881                 w = MCBSP_READ_CACHE(mcbsp, RCCR);
 882                 w &= ~(rx ? RDISABLE : 0);
 883                 MCBSP_WRITE(mcbsp, RCCR, w);
 884         }
 885
 886         /* Dump McBSP Regs */
 887         omap_mcbsp_dump_reg(id);
 888 }
 889 EXPORT_SYMBOL(omap_mcbsp_start);
 890
 891 void omap_mcbsp_stop(unsigned int id, int tx, int rx)
 892 {
 893         struct omap_mcbsp *mcbsp;
 894         int idle;
 895         u16 w;
 896
 897         if (!omap_mcbsp_check_valid_id(id)) {
 898                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 899                 return;
 900         }
 901
 902         mcbsp = id_to_mcbsp_ptr(id);
 903
 904         /* Reset transmitter */
 905         tx &= 1;
 906         if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
 907                 w = MCBSP_READ_CACHE(mcbsp, XCCR);
 908                 w |= (tx ? XDISABLE : 0);
 909                 MCBSP_WRITE(mcbsp, XCCR, w);
 910         }
 911         w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 912         MCBSP_WRITE(mcbsp, SPCR2, w & ~tx);
 913
 914         /* Reset receiver */
 915         rx &= 1;
 916         if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
 917                 w = MCBSP_READ_CACHE(mcbsp, RCCR);
 918                 w |= (rx ? RDISABLE : 0);
 919                 MCBSP_WRITE(mcbsp, RCCR, w);
 920         }
 921         w = MCBSP_READ_CACHE(mcbsp, SPCR1);
 922         MCBSP_WRITE(mcbsp, SPCR1, w & ~rx);
 923
 924         idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
 925                         MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
 926
 927         if (idle) {
 928                 /* Reset the sample rate generator */
 929                 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 930                 MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6));
 931         }
 932
 933         if (cpu_is_omap34xx())
 934                 omap_st_stop(mcbsp);
 935 }
 936 EXPORT_SYMBOL(omap_mcbsp_stop);
 937
 938 /*
 939  * The following functions are only required on an OMAP1-only build.
 940  * mach-omap2/mcbsp.c contains the real functions
 941  */
 942 #ifndef CONFIG_ARCH_OMAP2PLUS
 943 int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id)
 944 {
 945         WARN(1, "%s: should never be called on an OMAP1-only kernel\n",
 946              __func__);
 947         return -EINVAL;
 948 }
 949
 950 void omap2_mcbsp1_mux_clkr_src(u8 mux)
 951 {
 952         WARN(1, "%s: should never be called on an OMAP1-only kernel\n",
 953              __func__);
 954         return;
 955 }
 956
 957 void omap2_mcbsp1_mux_fsr_src(u8 mux)
 958 {
 959         WARN(1, "%s: should never be called on an OMAP1-only kernel\n",
 960              __func__);
 961         return;
 962 }
 963 #endif
 964
 965 #ifdef CONFIG_ARCH_OMAP3
 966 #define max_thres(m)                    (mcbsp->pdata->buffer_size)
 967 #define valid_threshold(m, val)         ((val) <= max_thres(m))
 968 #define THRESHOLD_PROP_BUILDER(prop)                                    \
 969 static ssize_t prop##_show(struct device *dev,                          \
 970                         struct device_attribute *attr, char *buf)       \
 971 {                                                                       \
 972         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);                \
 973                                                                         \
 974         return sprintf(buf, "%u\n", mcbsp->prop);                       \
 975 }                                                                       \
 976                                                                         \
 977 static ssize_t prop##_store(struct device *dev,                         \
 978                                 struct device_attribute *attr,          \
 979                                 const char *buf, size_t size)           \
 980 {                                                                       \
 981         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);                \
 982         unsigned long val;                                              \
 983         int status;                                                     \
 984                                                                         \
 985         status = strict_strtoul(buf, 0, &val);                          \
 986         if (status)                                                     \
 987                 return status;                                          \
 988                                                                         \
 989         if (!valid_threshold(mcbsp, val))                               \
 990                 return -EDOM;                                           \
 991                                                                         \
 992         mcbsp->prop = val;                                              \
 993         return size;                                                    \
 994 }                                                                       \
 995                                                                         \
 996 static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store);
 997
 998 THRESHOLD_PROP_BUILDER(max_tx_thres);
 999 THRESHOLD_PROP_BUILDER(max_rx_thres);
1000
1001 static const char *dma_op_modes[] = {
1002         "element", "threshold", "frame",
1003 };
1004
1005 static ssize_t dma_op_mode_show(struct device *dev,
1006                         struct device_attribute *attr, char *buf)
1007 {
1008         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1009         int dma_op_mode, i = 0;
1010         ssize_t len = 0;
1011         const char * const *s;
1012
1013         dma_op_mode = mcbsp->dma_op_mode;
1014
1015         for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) {
1016                 if (dma_op_mode == i)
1017                         len += sprintf(buf + len, "[%s] ", *s);
1018                 else
1019                         len += sprintf(buf + len, "%s ", *s);
1020         }
1021         len += sprintf(buf + len, "\n");
1022
1023         return len;
1024 }
1025
1026 static ssize_t dma_op_mode_store(struct device *dev,
1027                                 struct device_attribute *attr,
1028                                 const char *buf, size_t size)
1029 {
1030         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1031         const char * const *s;
1032         int i = 0;
1033
1034         for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++)
1035                 if (sysfs_streq(buf, *s))
1036                         break;
1037
1038         if (i == ARRAY_SIZE(dma_op_modes))
1039                 return -EINVAL;
1040
1041         spin_lock_irq(&mcbsp->lock);
1042         if (!mcbsp->free) {
1043                 size = -EBUSY;
1044                 goto unlock;
1045         }
1046         mcbsp->dma_op_mode = i;
1047
1048 unlock:
1049         spin_unlock_irq(&mcbsp->lock);
1050
1051         return size;
1052 }
1053
1054 static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store);
1055
1056 static ssize_t st_taps_show(struct device *dev,
1057                             struct device_attribute *attr, char *buf)
1058 {
1059         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1060         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1061         ssize_t status = 0;
1062         int i;
1063
1064         spin_lock_irq(&mcbsp->lock);
1065         for (i = 0; i < st_data->nr_taps; i++)
1066                 status += sprintf(&buf[status], (i ? ", %d" : "%d"),
1067                                   st_data->taps[i]);
1068         if (i)
1069                 status += sprintf(&buf[status], "\n");
1070         spin_unlock_irq(&mcbsp->lock);
1071
1072         return status;
1073 }
1074
1075 static ssize_t st_taps_store(struct device *dev,
1076                              struct device_attribute *attr,
1077                              const char *buf, size_t size)
1078 {
1079         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1080         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1081         int val, tmp, status, i = 0;
1082
1083         spin_lock_irq(&mcbsp->lock);
1084         memset(st_data->taps, 0, sizeof(st_data->taps));
1085         st_data->nr_taps = 0;
1086
1087         do {
1088                 status = sscanf(buf, "%d%n", &val, &tmp);
1089                 if (status < 0 || status == 0) {
1090                         size = -EINVAL;
1091                         goto out;
1092                 }
1093                 if (val < -32768 || val > 32767) {
1094                         size = -EINVAL;
1095                         goto out;
1096                 }
1097                 st_data->taps[i++] = val;
1098                 buf += tmp;
1099                 if (*buf != ',')
1100                         break;
1101                 buf++;
1102         } while (1);
1103
1104         st_data->nr_taps = i;
1105
1106 out:
1107         spin_unlock_irq(&mcbsp->lock);
1108
1109         return size;
1110 }
1111
1112 static DEVICE_ATTR(st_taps, 0644, st_taps_show, st_taps_store);
1113
1114 static const struct attribute *additional_attrs[] = {
1115         &dev_attr_max_tx_thres.attr,
1116         &dev_attr_max_rx_thres.attr,
1117         &dev_attr_dma_op_mode.attr,
1118         NULL,
1119 };
1120
1121 static const struct attribute_group additional_attr_group = {
1122         .attrs = (struct attribute **)additional_attrs,
1123 };
1124
1125 static inline int __devinit omap_additional_add(struct device *dev)
1126 {
1127         return sysfs_create_group(&dev->kobj, &additional_attr_group);
1128 }
1129
1130 static inline void __devexit omap_additional_remove(struct device *dev)
1131 {
1132         sysfs_remove_group(&dev->kobj, &additional_attr_group);
1133 }
1134
1135 static const struct attribute *sidetone_attrs[] = {
1136         &dev_attr_st_taps.attr,
1137         NULL,
1138 };
1139
1140 static const struct attribute_group sidetone_attr_group = {
1141         .attrs = (struct attribute **)sidetone_attrs,
1142 };
1143
1144 static int __devinit omap_st_add(struct omap_mcbsp *mcbsp)
1145 {
1146         struct platform_device *pdev;
1147         struct resource *res;
1148         struct omap_mcbsp_st_data *st_data;
1149         int err;
1150
1151         st_data = kzalloc(sizeof(*mcbsp->st_data), GFP_KERNEL);
1152         if (!st_data) {
1153                 err = -ENOMEM;
1154                 goto err1;
1155         }
1156
1157         pdev = container_of(mcbsp->dev, struct platform_device, dev);
1158
1159         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sidetone");
1160         st_data->io_base_st = ioremap(res->start, resource_size(res));
1161         if (!st_data->io_base_st) {
1162                 err = -ENOMEM;
1163                 goto err2;
1164         }
1165
1166         err = sysfs_create_group(&mcbsp->dev->kobj, &sidetone_attr_group);
1167         if (err)
1168                 goto err3;
1169
1170         mcbsp->st_data = st_data;
1171         return 0;
1172
1173 err3:
1174         iounmap(st_data->io_base_st);
1175 err2:
1176         kfree(st_data);
1177 err1:
1178         return err;
1179
1180 }
1181
1182 static void __devexit omap_st_remove(struct omap_mcbsp *mcbsp)
1183 {
1184         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1185
1186         if (st_data) {
1187                 sysfs_remove_group(&mcbsp->dev->kobj, &sidetone_attr_group);
1188                 iounmap(st_data->io_base_st);
1189                 kfree(st_data);
1190         }
1191 }
1192
1193 static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp)
1194 {
1195         mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
1196         if (cpu_is_omap34xx()) {
1197                 /*
1198                  * Initially configure the maximum thresholds to a safe value.
1199                  * The McBSP FIFO usage with these values should not go under
1200                  * 16 locations.
1201                  * If the whole FIFO without safety buffer is used, than there
1202                  * is a possibility that the DMA will be not able to push the
1203                  * new data on time, causing channel shifts in runtime.
1204                  */
1205                 mcbsp->max_tx_thres = max_thres(mcbsp) - 0x10;
1206                 mcbsp->max_rx_thres = max_thres(mcbsp) - 0x10;
1207                 /*
1208                  * REVISIT: Set dmap_op_mode to THRESHOLD as default
1209                  * for mcbsp2 instances.
1210                  */
1211                 if (omap_additional_add(mcbsp->dev))
1212                         dev_warn(mcbsp->dev,
1213                                 "Unable to create additional controls\n");
1214
1215                 if (mcbsp->id == 2 || mcbsp->id == 3)
1216                         if (omap_st_add(mcbsp))
1217                                 dev_warn(mcbsp->dev,
1218                                  "Unable to create sidetone controls\n");
1219
1220         } else {
1221                 mcbsp->max_tx_thres = -EINVAL;
1222                 mcbsp->max_rx_thres = -EINVAL;
1223         }
1224 }
1225
1226 static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp)
1227 {
1228         if (cpu_is_omap34xx()) {
1229                 omap_additional_remove(mcbsp->dev);
1230
1231                 if (mcbsp->id == 2 || mcbsp->id == 3)
1232                         omap_st_remove(mcbsp);
1233         }
1234 }
1235 #else
1236 static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp) {}
1237 static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp) {}
1238 #endif /* CONFIG_ARCH_OMAP3 */
1239
1240 /*
1241  * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
1242  * 730 has only 2 McBSP, and both of them are MPU peripherals.
1243  */
1244 static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
1245 {
1246         struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data;
1247         struct omap_mcbsp *mcbsp;
1248         int id = pdev->id - 1;
1249         struct resource *res;
1250         int ret = 0;
1251
1252         if (!pdata) {
1253                 dev_err(&pdev->dev, "McBSP device initialized without"
1254                                 "platform data\n");
1255                 ret = -EINVAL;
1256                 goto exit;
1257         }
1258
1259         dev_dbg(&pdev->dev, "Initializing OMAP McBSP (%d).\n", pdev->id);
1260
1261         if (id >= omap_mcbsp_count) {
1262                 dev_err(&pdev->dev, "Invalid McBSP device id (%d)\n", id);
1263                 ret = -EINVAL;
1264                 goto exit;
1265         }
1266
1267         mcbsp = kzalloc(sizeof(struct omap_mcbsp), GFP_KERNEL);
1268         if (!mcbsp) {
1269                 ret = -ENOMEM;
1270                 goto exit;
1271         }
1272
1273         spin_lock_init(&mcbsp->lock);
1274         mcbsp->id = id + 1;
1275         mcbsp->free = true;
1276
1277         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
1278         if (!res) {
1279                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1280                 if (!res) {
1281                         dev_err(&pdev->dev, "%s:mcbsp%d has invalid memory"
1282                                         "resource\n", __func__, pdev->id);
1283                         ret = -ENOMEM;
1284                         goto exit;
1285                 }
1286         }
1287         mcbsp->phys_base = res->start;
1288         omap_mcbsp_cache_size = resource_size(res);
1289         mcbsp->io_base = ioremap(res->start, resource_size(res));
1290         if (!mcbsp->io_base) {
1291                 ret = -ENOMEM;
1292                 goto err_ioremap;
1293         }
1294
1295         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
1296         if (!res)
1297                 mcbsp->phys_dma_base = mcbsp->phys_base;
1298         else
1299                 mcbsp->phys_dma_base = res->start;
1300
1301         mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx");
1302         mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx");
1303
1304         /* From OMAP4 there will be a single irq line */
1305         if (mcbsp->tx_irq == -ENXIO)
1306                 mcbsp->tx_irq = platform_get_irq(pdev, 0);
1307
1308         res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1309         if (!res) {
1310                 dev_err(&pdev->dev, "%s:mcbsp%d has invalid rx DMA channel\n",
1311                                         __func__, pdev->id);
1312                 ret = -ENODEV;
1313                 goto err_res;
1314         }
1315         mcbsp->dma_rx_sync = res->start;
1316
1317         res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1318         if (!res) {
1319                 dev_err(&pdev->dev, "%s:mcbsp%d has invalid tx DMA channel\n",
1320                                         __func__, pdev->id);
1321                 ret = -ENODEV;
1322                 goto err_res;
1323         }
1324         mcbsp->dma_tx_sync = res->start;
1325
1326         mcbsp->fclk = clk_get(&pdev->dev, "fck");
1327         if (IS_ERR(mcbsp->fclk)) {
1328                 ret = PTR_ERR(mcbsp->fclk);
1329                 dev_err(&pdev->dev, "unable to get fck: %d\n", ret);
1330                 goto err_res;
1331         }
1332
1333         mcbsp->pdata = pdata;
1334         mcbsp->dev = &pdev->dev;
1335         mcbsp_ptr[id] = mcbsp;
1336         platform_set_drvdata(pdev, mcbsp);
1337         pm_runtime_enable(mcbsp->dev);
1338
1339         /* Initialize mcbsp properties for OMAP34XX if needed / applicable */
1340         omap34xx_device_init(mcbsp);
1341
1342         return 0;
1343
1344 err_res:
1345         iounmap(mcbsp->io_base);
1346 err_ioremap:
1347         kfree(mcbsp);
1348 exit:
1349         return ret;
1350 }
1351
1352 static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
1353 {
1354         struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
1355
1356         platform_set_drvdata(pdev, NULL);
1357         if (mcbsp) {
1358
1359                 if (mcbsp->pdata && mcbsp->pdata->ops &&
1360                                 mcbsp->pdata->ops->free)
1361                         mcbsp->pdata->ops->free(mcbsp->id);
1362
1363                 omap34xx_device_exit(mcbsp);
1364
1365                 clk_put(mcbsp->fclk);
1366
1367                 iounmap(mcbsp->io_base);
1368                 kfree(mcbsp);
1369         }
1370
1371         return 0;
1372 }
1373
1374 static struct platform_driver omap_mcbsp_driver = {
1375         .probe          = omap_mcbsp_probe,
1376         .remove         = __devexit_p(omap_mcbsp_remove),
1377         .driver         = {
1378                 .name   = "omap-mcbsp",
1379         },
1380 };
1381
1382 int __init omap_mcbsp_init(void)
1383 {
1384         /* Register the McBSP driver */
1385         return platform_driver_register(&omap_mcbsp_driver);
1386 }