arch/arm/plat-omap/mcbsp.c

   1 /*
   2  * linux/arch/arm/plat-omap/mcbsp.c
   3  *
   4  * Copyright (C) 2004 Nokia Corporation
   5  * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
   6  *
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * Multichannel mode not supported.
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/init.h>
  17 #include <linux/device.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/wait.h>
  20 #include <linux/completion.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/err.h>
  23 #include <linux/clk.h>
  24 #include <linux/delay.h>
  25 #include <linux/io.h>
  26
  27 #include <mach/dma.h>
  28 #include <mach/mcbsp.h>
  29
  30 struct omap_mcbsp **mcbsp_ptr;
  31 int omap_mcbsp_count;
  32
  33 void omap_mcbsp_write(void __iomem *io_base, u16 reg, u32 val)
  34 {
  35         if (cpu_class_is_omap1() || cpu_is_omap2420())
  36                 __raw_writew((u16)val, io_base + reg);
  37         else
  38                 __raw_writel(val, io_base + reg);
  39 }
  40
  41 int omap_mcbsp_read(void __iomem *io_base, u16 reg)
  42 {
  43         if (cpu_class_is_omap1() || cpu_is_omap2420())
  44                 return __raw_readw(io_base + reg);
  45         else
  46                 return __raw_readl(io_base + reg);
  47 }
  48
  49 #define OMAP_MCBSP_READ(base, reg) \
  50                         omap_mcbsp_read(base, OMAP_MCBSP_REG_##reg)
  51 #define OMAP_MCBSP_WRITE(base, reg, val) \
  52                         omap_mcbsp_write(base, OMAP_MCBSP_REG_##reg, val)
  53
  54 #define omap_mcbsp_check_valid_id(id)   (id < omap_mcbsp_count)
  55 #define id_to_mcbsp_ptr(id)             mcbsp_ptr[id];
  56
  57 static void omap_mcbsp_dump_reg(u8 id)
  58 {
  59         struct omap_mcbsp *mcbsp = id_to_mcbsp_ptr(id);
  60
  61         dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
  62         dev_dbg(mcbsp->dev, "DRR2:  0x%04x\n",
  63                         OMAP_MCBSP_READ(mcbsp->io_base, DRR2));
  64         dev_dbg(mcbsp->dev, "DRR1:  0x%04x\n",
  65                         OMAP_MCBSP_READ(mcbsp->io_base, DRR1));
  66         dev_dbg(mcbsp->dev, "DXR2:  0x%04x\n",
  67                         OMAP_MCBSP_READ(mcbsp->io_base, DXR2));
  68         dev_dbg(mcbsp->dev, "DXR1:  0x%04x\n",
  69                         OMAP_MCBSP_READ(mcbsp->io_base, DXR1));
  70         dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n",
  71                         OMAP_MCBSP_READ(mcbsp->io_base, SPCR2));
  72         dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n",
  73                         OMAP_MCBSP_READ(mcbsp->io_base, SPCR1));
  74         dev_dbg(mcbsp->dev, "RCR2:  0x%04x\n",
  75                         OMAP_MCBSP_READ(mcbsp->io_base, RCR2));
  76         dev_dbg(mcbsp->dev, "RCR1:  0x%04x\n",
  77                         OMAP_MCBSP_READ(mcbsp->io_base, RCR1));
  78         dev_dbg(mcbsp->dev, "XCR2:  0x%04x\n",
  79                         OMAP_MCBSP_READ(mcbsp->io_base, XCR2));
  80         dev_dbg(mcbsp->dev, "XCR1:  0x%04x\n",
  81                         OMAP_MCBSP_READ(mcbsp->io_base, XCR1));
  82         dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n",
  83                         OMAP_MCBSP_READ(mcbsp->io_base, SRGR2));
  84         dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n",
  85                         OMAP_MCBSP_READ(mcbsp->io_base, SRGR1));
  86         dev_dbg(mcbsp->dev, "PCR0:  0x%04x\n",
  87                         OMAP_MCBSP_READ(mcbsp->io_base, PCR0));
  88         dev_dbg(mcbsp->dev, "***********************\n");
  89 }
  90
  91 static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
  92 {
  93         struct omap_mcbsp *mcbsp_tx = dev_id;
  94         u16 irqst_spcr2;
  95
  96         irqst_spcr2 = OMAP_MCBSP_READ(mcbsp_tx->io_base, SPCR2);
  97         dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
  98
  99         if (irqst_spcr2 & XSYNC_ERR) {
 100                 dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n",
 101                         irqst_spcr2);
 102                 /* Writing zero to XSYNC_ERR clears the IRQ */
 103                 OMAP_MCBSP_WRITE(mcbsp_tx->io_base, SPCR2,
 104                         irqst_spcr2 & ~(XSYNC_ERR));
 105         } else {
 106                 complete(&mcbsp_tx->tx_irq_completion);
 107         }
 108
 109         return IRQ_HANDLED;
 110 }
 111
 112 static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
 113 {
 114         struct omap_mcbsp *mcbsp_rx = dev_id;
 115         u16 irqst_spcr1;
 116
 117         irqst_spcr1 = OMAP_MCBSP_READ(mcbsp_rx->io_base, SPCR1);
 118         dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
 119
 120         if (irqst_spcr1 & RSYNC_ERR) {
 121                 dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n",
 122                         irqst_spcr1);
 123                 /* Writing zero to RSYNC_ERR clears the IRQ */
 124                 OMAP_MCBSP_WRITE(mcbsp_rx->io_base, SPCR1,
 125                         irqst_spcr1 & ~(RSYNC_ERR));
 126         } else {
 127                 complete(&mcbsp_rx->tx_irq_completion);
 128         }
 129
 130         return IRQ_HANDLED;
 131 }
 132
 133 static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data)
 134 {
 135         struct omap_mcbsp *mcbsp_dma_tx = data;
 136
 137         dev_dbg(mcbsp_dma_tx->dev, "TX DMA callback : 0x%x\n",
 138                 OMAP_MCBSP_READ(mcbsp_dma_tx->io_base, SPCR2));
 139
 140         /* We can free the channels */
 141         omap_free_dma(mcbsp_dma_tx->dma_tx_lch);
 142         mcbsp_dma_tx->dma_tx_lch = -1;
 143
 144         complete(&mcbsp_dma_tx->tx_dma_completion);
 145 }
 146
 147 static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
 148 {
 149         struct omap_mcbsp *mcbsp_dma_rx = data;
 150
 151         dev_dbg(mcbsp_dma_rx->dev, "RX DMA callback : 0x%x\n",
 152                 OMAP_MCBSP_READ(mcbsp_dma_rx->io_base, SPCR2));
 153
 154         /* We can free the channels */
 155         omap_free_dma(mcbsp_dma_rx->dma_rx_lch);
 156         mcbsp_dma_rx->dma_rx_lch = -1;
 157
 158         complete(&mcbsp_dma_rx->rx_dma_completion);
 159 }
 160
 161 /*
 162  * omap_mcbsp_config simply write a config to the
 163  * appropriate McBSP.
 164  * You either call this function or set the McBSP registers
 165  * by yourself before calling omap_mcbsp_start().
 166  */
 167 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
 168 {
 169         struct omap_mcbsp *mcbsp;
 170         void __iomem *io_base;
 171
 172         if (!omap_mcbsp_check_valid_id(id)) {
 173                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 174                 return;
 175         }
 176         mcbsp = id_to_mcbsp_ptr(id);
 177
 178         io_base = mcbsp->io_base;
 179         dev_dbg(mcbsp->dev, "Configuring McBSP%d  phys_base: 0x%08lx\n",
 180                         mcbsp->id, mcbsp->phys_base);
 181
 182         /* We write the given config */
 183         OMAP_MCBSP_WRITE(io_base, SPCR2, config->spcr2);
 184         OMAP_MCBSP_WRITE(io_base, SPCR1, config->spcr1);
 185         OMAP_MCBSP_WRITE(io_base, RCR2, config->rcr2);
 186         OMAP_MCBSP_WRITE(io_base, RCR1, config->rcr1);
 187         OMAP_MCBSP_WRITE(io_base, XCR2, config->xcr2);
 188         OMAP_MCBSP_WRITE(io_base, XCR1, config->xcr1);
 189         OMAP_MCBSP_WRITE(io_base, SRGR2, config->srgr2);
 190         OMAP_MCBSP_WRITE(io_base, SRGR1, config->srgr1);
 191         OMAP_MCBSP_WRITE(io_base, MCR2, config->mcr2);
 192         OMAP_MCBSP_WRITE(io_base, MCR1, config->mcr1);
 193         OMAP_MCBSP_WRITE(io_base, PCR0, config->pcr0);
 194         if (cpu_is_omap2430() || cpu_is_omap34xx()) {
 195                 OMAP_MCBSP_WRITE(io_base, XCCR, config->xccr);
 196                 OMAP_MCBSP_WRITE(io_base, RCCR, config->rccr);
 197         }
 198 }
 199 EXPORT_SYMBOL(omap_mcbsp_config);
 200
 201 /*
 202  * We can choose between IRQ based or polled IO.
 203  * This needs to be called before omap_mcbsp_request().
 204  */
 205 int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type)
 206 {
 207         struct omap_mcbsp *mcbsp;
 208
 209         if (!omap_mcbsp_check_valid_id(id)) {
 210                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 211                 return -ENODEV;
 212         }
 213         mcbsp = id_to_mcbsp_ptr(id);
 214
 215         spin_lock(&mcbsp->lock);
 216
 217         if (!mcbsp->free) {
 218                 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
 219                         mcbsp->id);
 220                 spin_unlock(&mcbsp->lock);
 221                 return -EINVAL;
 222         }
 223
 224         mcbsp->io_type = io_type;
 225
 226         spin_unlock(&mcbsp->lock);
 227
 228         return 0;
 229 }
 230 EXPORT_SYMBOL(omap_mcbsp_set_io_type);
 231
 232 int omap_mcbsp_request(unsigned int id)
 233 {
 234         struct omap_mcbsp *mcbsp;
 235         int err;
 236
 237         if (!omap_mcbsp_check_valid_id(id)) {
 238                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 239                 return -ENODEV;
 240         }
 241         mcbsp = id_to_mcbsp_ptr(id);
 242
 243         spin_lock(&mcbsp->lock);
 244         if (!mcbsp->free) {
 245                 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
 246                         mcbsp->id);
 247                 spin_unlock(&mcbsp->lock);
 248                 return -EBUSY;
 249         }
 250
 251         mcbsp->free = 0;
 252         spin_unlock(&mcbsp->lock);
 253
 254         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
 255                 mcbsp->pdata->ops->request(id);
 256
 257         clk_enable(mcbsp->iclk);
 258         clk_enable(mcbsp->fclk);
 259
 260         /*
 261          * Make sure that transmitter, receiver and sample-rate generator are
 262          * not running before activating IRQs.
 263          */
 264         OMAP_MCBSP_WRITE(mcbsp->io_base, SPCR1, 0);
 265         OMAP_MCBSP_WRITE(mcbsp->io_base, SPCR2, 0);
 266
 267         if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
 268                 /* We need to get IRQs here */
 269                 init_completion(&mcbsp->tx_irq_completion);
 270                 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler,
 271                                         0, "McBSP", (void *)mcbsp);
 272                 if (err != 0) {
 273                         dev_err(mcbsp->dev, "Unable to request TX IRQ %d "
 274                                         "for McBSP%d\n", mcbsp->tx_irq,
 275                                         mcbsp->id);
 276                         return err;
 277                 }
 278
 279                 init_completion(&mcbsp->rx_irq_completion);
 280                 err = request_irq(mcbsp->rx_irq, omap_mcbsp_rx_irq_handler,
 281                                         0, "McBSP", (void *)mcbsp);
 282                 if (err != 0) {
 283                         dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
 284                                         "for McBSP%d\n", mcbsp->rx_irq,
 285                                         mcbsp->id);
 286                         free_irq(mcbsp->tx_irq, (void *)mcbsp);
 287                         return err;
 288                 }
 289         }
 290
 291         return 0;
 292 }
 293 EXPORT_SYMBOL(omap_mcbsp_request);
 294
 295 void omap_mcbsp_free(unsigned int id)
 296 {
 297         struct omap_mcbsp *mcbsp;
 298
 299         if (!omap_mcbsp_check_valid_id(id)) {
 300                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 301                 return;
 302         }
 303         mcbsp = id_to_mcbsp_ptr(id);
 304
 305         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
 306                 mcbsp->pdata->ops->free(id);
 307
 308         clk_disable(mcbsp->fclk);
 309         clk_disable(mcbsp->iclk);
 310
 311         if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
 312                 /* Free IRQs */
 313                 free_irq(mcbsp->rx_irq, (void *)mcbsp);
 314                 free_irq(mcbsp->tx_irq, (void *)mcbsp);
 315         }
 316
 317         spin_lock(&mcbsp->lock);
 318         if (mcbsp->free) {
 319                 dev_err(mcbsp->dev, "McBSP%d was not reserved\n",
 320                         mcbsp->id);
 321                 spin_unlock(&mcbsp->lock);
 322                 return;
 323         }
 324
 325         mcbsp->free = 1;
 326         spin_unlock(&mcbsp->lock);
 327 }
 328 EXPORT_SYMBOL(omap_mcbsp_free);
 329
 330 /*
 331  * Here we start the McBSP, by enabling transmitter, receiver or both.
 332  * If no transmitter or receiver is active prior calling, then sample-rate
 333  * generator and frame sync are started.
 334  */
 335 void omap_mcbsp_start(unsigned int id, int tx, int rx)
 336 {
 337         struct omap_mcbsp *mcbsp;
 338         void __iomem *io_base;
 339         int idle;
 340         u16 w;
 341
 342         if (!omap_mcbsp_check_valid_id(id)) {
 343                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 344                 return;
 345         }
 346         mcbsp = id_to_mcbsp_ptr(id);
 347         io_base = mcbsp->io_base;
 348
 349         mcbsp->rx_word_length = (OMAP_MCBSP_READ(io_base, RCR1) >> 5) & 0x7;
 350         mcbsp->tx_word_length = (OMAP_MCBSP_READ(io_base, XCR1) >> 5) & 0x7;
 351
 352         idle = !((OMAP_MCBSP_READ(io_base, SPCR2) |
 353                   OMAP_MCBSP_READ(io_base, SPCR1)) & 1);
 354
 355         if (idle) {
 356                 /* Start the sample generator */
 357                 w = OMAP_MCBSP_READ(io_base, SPCR2);
 358                 OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 6));
 359         }
 360
 361         /* Enable transmitter and receiver */
 362         w = OMAP_MCBSP_READ(io_base, SPCR2);
 363         OMAP_MCBSP_WRITE(io_base, SPCR2, w | (tx & 1));
 364
 365         w = OMAP_MCBSP_READ(io_base, SPCR1);
 366         OMAP_MCBSP_WRITE(io_base, SPCR1, w | (rx & 1));
 367
 368         udelay(100);
 369
 370         if (idle) {
 371                 /* Start frame sync */
 372                 w = OMAP_MCBSP_READ(io_base, SPCR2);
 373                 OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 7));
 374         }
 375
 376         /* Dump McBSP Regs */
 377         omap_mcbsp_dump_reg(id);
 378 }
 379 EXPORT_SYMBOL(omap_mcbsp_start);
 380
 381 void omap_mcbsp_stop(unsigned int id, int tx, int rx)
 382 {
 383         struct omap_mcbsp *mcbsp;
 384         void __iomem *io_base;
 385         int idle;
 386         u16 w;
 387
 388         if (!omap_mcbsp_check_valid_id(id)) {
 389                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 390                 return;
 391         }
 392
 393         mcbsp = id_to_mcbsp_ptr(id);
 394         io_base = mcbsp->io_base;
 395
 396         /* Reset transmitter */
 397         w = OMAP_MCBSP_READ(io_base, SPCR2);
 398         OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(tx & 1));
 399
 400         /* Reset receiver */
 401         w = OMAP_MCBSP_READ(io_base, SPCR1);
 402         OMAP_MCBSP_WRITE(io_base, SPCR1, w & ~(rx & 1));
 403
 404         idle = !((OMAP_MCBSP_READ(io_base, SPCR2) |
 405                   OMAP_MCBSP_READ(io_base, SPCR1)) & 1);
 406
 407         if (idle) {
 408                 /* Reset the sample rate generator */
 409                 w = OMAP_MCBSP_READ(io_base, SPCR2);
 410                 OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1 << 6));
 411         }
 412 }
 413 EXPORT_SYMBOL(omap_mcbsp_stop);
 414
 415 /* polled mcbsp i/o operations */
 416 int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
 417 {
 418         struct omap_mcbsp *mcbsp;
 419         void __iomem *base;
 420
 421         if (!omap_mcbsp_check_valid_id(id)) {
 422                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 423                 return -ENODEV;
 424         }
 425
 426         mcbsp = id_to_mcbsp_ptr(id);
 427         base = mcbsp->io_base;
 428
 429         writew(buf, base + OMAP_MCBSP_REG_DXR1);
 430         /* if frame sync error - clear the error */
 431         if (readw(base + OMAP_MCBSP_REG_SPCR2) & XSYNC_ERR) {
 432                 /* clear error */
 433                 writew(readw(base + OMAP_MCBSP_REG_SPCR2) & (~XSYNC_ERR),
 434                        base + OMAP_MCBSP_REG_SPCR2);
 435                 /* resend */
 436                 return -1;
 437         } else {
 438                 /* wait for transmit confirmation */
 439                 int attemps = 0;
 440                 while (!(readw(base + OMAP_MCBSP_REG_SPCR2) & XRDY)) {
 441                         if (attemps++ > 1000) {
 442                                 writew(readw(base + OMAP_MCBSP_REG_SPCR2) &
 443                                        (~XRST),
 444                                        base + OMAP_MCBSP_REG_SPCR2);
 445                                 udelay(10);
 446                                 writew(readw(base + OMAP_MCBSP_REG_SPCR2) |
 447                                        (XRST),
 448                                        base + OMAP_MCBSP_REG_SPCR2);
 449                                 udelay(10);
 450                                 dev_err(mcbsp->dev, "Could not write to"
 451                                         " McBSP%d Register\n", mcbsp->id);
 452                                 return -2;
 453                         }
 454                 }
 455         }
 456
 457         return 0;
 458 }
 459 EXPORT_SYMBOL(omap_mcbsp_pollwrite);
 460
 461 int omap_mcbsp_pollread(unsigned int id, u16 *buf)
 462 {
 463         struct omap_mcbsp *mcbsp;
 464         void __iomem *base;
 465
 466         if (!omap_mcbsp_check_valid_id(id)) {
 467                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 468                 return -ENODEV;
 469         }
 470         mcbsp = id_to_mcbsp_ptr(id);
 471
 472         base = mcbsp->io_base;
 473         /* if frame sync error - clear the error */
 474         if (readw(base + OMAP_MCBSP_REG_SPCR1) & RSYNC_ERR) {
 475                 /* clear error */
 476                 writew(readw(base + OMAP_MCBSP_REG_SPCR1) & (~RSYNC_ERR),
 477                        base + OMAP_MCBSP_REG_SPCR1);
 478                 /* resend */
 479                 return -1;
 480         } else {
 481                 /* wait for recieve confirmation */
 482                 int attemps = 0;
 483                 while (!(readw(base + OMAP_MCBSP_REG_SPCR1) & RRDY)) {
 484                         if (attemps++ > 1000) {
 485                                 writew(readw(base + OMAP_MCBSP_REG_SPCR1) &
 486                                        (~RRST),
 487                                        base + OMAP_MCBSP_REG_SPCR1);
 488                                 udelay(10);
 489                                 writew(readw(base + OMAP_MCBSP_REG_SPCR1) |
 490                                        (RRST),
 491                                        base + OMAP_MCBSP_REG_SPCR1);
 492                                 udelay(10);
 493                                 dev_err(mcbsp->dev, "Could not read from"
 494                                         " McBSP%d Register\n", mcbsp->id);
 495                                 return -2;
 496                         }
 497                 }
 498         }
 499         *buf = readw(base + OMAP_MCBSP_REG_DRR1);
 500
 501         return 0;
 502 }
 503 EXPORT_SYMBOL(omap_mcbsp_pollread);
 504
 505 /*
 506  * IRQ based word transmission.
 507  */
 508 void omap_mcbsp_xmit_word(unsigned int id, u32 word)
 509 {
 510         struct omap_mcbsp *mcbsp;
 511         void __iomem *io_base;
 512         omap_mcbsp_word_length word_length;
 513
 514         if (!omap_mcbsp_check_valid_id(id)) {
 515                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 516                 return;
 517         }
 518
 519         mcbsp = id_to_mcbsp_ptr(id);
 520         io_base = mcbsp->io_base;
 521         word_length = mcbsp->tx_word_length;
 522
 523         wait_for_completion(&mcbsp->tx_irq_completion);
 524
 525         if (word_length > OMAP_MCBSP_WORD_16)
 526                 OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16);
 527         OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff);
 528 }
 529 EXPORT_SYMBOL(omap_mcbsp_xmit_word);
 530
 531 u32 omap_mcbsp_recv_word(unsigned int id)
 532 {
 533         struct omap_mcbsp *mcbsp;
 534         void __iomem *io_base;
 535         u16 word_lsb, word_msb = 0;
 536         omap_mcbsp_word_length word_length;
 537
 538         if (!omap_mcbsp_check_valid_id(id)) {
 539                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 540                 return -ENODEV;
 541         }
 542         mcbsp = id_to_mcbsp_ptr(id);
 543
 544         word_length = mcbsp->rx_word_length;
 545         io_base = mcbsp->io_base;
 546
 547         wait_for_completion(&mcbsp->rx_irq_completion);
 548
 549         if (word_length > OMAP_MCBSP_WORD_16)
 550                 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
 551         word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
 552
 553         return (word_lsb | (word_msb << 16));
 554 }
 555 EXPORT_SYMBOL(omap_mcbsp_recv_word);
 556
 557 int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
 558 {
 559         struct omap_mcbsp *mcbsp;
 560         void __iomem *io_base;
 561         omap_mcbsp_word_length tx_word_length;
 562         omap_mcbsp_word_length rx_word_length;
 563         u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
 564
 565         if (!omap_mcbsp_check_valid_id(id)) {
 566                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 567                 return -ENODEV;
 568         }
 569         mcbsp = id_to_mcbsp_ptr(id);
 570         io_base = mcbsp->io_base;
 571         tx_word_length = mcbsp->tx_word_length;
 572         rx_word_length = mcbsp->rx_word_length;
 573
 574         if (tx_word_length != rx_word_length)
 575                 return -EINVAL;
 576
 577         /* First we wait for the transmitter to be ready */
 578         spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
 579         while (!(spcr2 & XRDY)) {
 580                 spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
 581                 if (attempts++ > 1000) {
 582                         /* We must reset the transmitter */
 583                         OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 & (~XRST));
 584                         udelay(10);
 585                         OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
 586                         udelay(10);
 587                         dev_err(mcbsp->dev, "McBSP%d transmitter not "
 588                                 "ready\n", mcbsp->id);
 589                         return -EAGAIN;
 590                 }
 591         }
 592
 593         /* Now we can push the data */
 594         if (tx_word_length > OMAP_MCBSP_WORD_16)
 595                 OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16);
 596         OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff);
 597
 598         /* We wait for the receiver to be ready */
 599         spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
 600         while (!(spcr1 & RRDY)) {
 601                 spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
 602                 if (attempts++ > 1000) {
 603                         /* We must reset the receiver */
 604                         OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 & (~RRST));
 605                         udelay(10);
 606                         OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
 607                         udelay(10);
 608                         dev_err(mcbsp->dev, "McBSP%d receiver not "
 609                                 "ready\n", mcbsp->id);
 610                         return -EAGAIN;
 611                 }
 612         }
 613
 614         /* Receiver is ready, let's read the dummy data */
 615         if (rx_word_length > OMAP_MCBSP_WORD_16)
 616                 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
 617         word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
 618
 619         return 0;
 620 }
 621 EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll);
 622
 623 int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
 624 {
 625         struct omap_mcbsp *mcbsp;
 626         u32 clock_word = 0;
 627         void __iomem *io_base;
 628         omap_mcbsp_word_length tx_word_length;
 629         omap_mcbsp_word_length rx_word_length;
 630         u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
 631
 632         if (!omap_mcbsp_check_valid_id(id)) {
 633                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 634                 return -ENODEV;
 635         }
 636
 637         mcbsp = id_to_mcbsp_ptr(id);
 638         io_base = mcbsp->io_base;
 639
 640         tx_word_length = mcbsp->tx_word_length;
 641         rx_word_length = mcbsp->rx_word_length;
 642
 643         if (tx_word_length != rx_word_length)
 644                 return -EINVAL;
 645
 646         /* First we wait for the transmitter to be ready */
 647         spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
 648         while (!(spcr2 & XRDY)) {
 649                 spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
 650                 if (attempts++ > 1000) {
 651                         /* We must reset the transmitter */
 652                         OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 & (~XRST));
 653                         udelay(10);
 654                         OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
 655                         udelay(10);
 656                         dev_err(mcbsp->dev, "McBSP%d transmitter not "
 657                                 "ready\n", mcbsp->id);
 658                         return -EAGAIN;
 659                 }
 660         }
 661
 662         /* We first need to enable the bus clock */
 663         if (tx_word_length > OMAP_MCBSP_WORD_16)
 664                 OMAP_MCBSP_WRITE(io_base, DXR2, clock_word >> 16);
 665         OMAP_MCBSP_WRITE(io_base, DXR1, clock_word & 0xffff);
 666
 667         /* We wait for the receiver to be ready */
 668         spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
 669         while (!(spcr1 & RRDY)) {
 670                 spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
 671                 if (attempts++ > 1000) {
 672                         /* We must reset the receiver */
 673                         OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 & (~RRST));
 674                         udelay(10);
 675                         OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
 676                         udelay(10);
 677                         dev_err(mcbsp->dev, "McBSP%d receiver not "
 678                                 "ready\n", mcbsp->id);
 679                         return -EAGAIN;
 680                 }
 681         }
 682
 683         /* Receiver is ready, there is something for us */
 684         if (rx_word_length > OMAP_MCBSP_WORD_16)
 685                 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
 686         word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
 687
 688         word[0] = (word_lsb | (word_msb << 16));
 689
 690         return 0;
 691 }
 692 EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll);
 693
 694 /*
 695  * Simple DMA based buffer rx/tx routines.
 696  * Nothing fancy, just a single buffer tx/rx through DMA.
 697  * The DMA resources are released once the transfer is done.
 698  * For anything fancier, you should use your own customized DMA
 699  * routines and callbacks.
 700  */
 701 int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer,
 702                                 unsigned int length)
 703 {
 704         struct omap_mcbsp *mcbsp;
 705         int dma_tx_ch;
 706         int src_port = 0;
 707         int dest_port = 0;
 708         int sync_dev = 0;
 709
 710         if (!omap_mcbsp_check_valid_id(id)) {
 711                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 712                 return -ENODEV;
 713         }
 714         mcbsp = id_to_mcbsp_ptr(id);
 715
 716         if (omap_request_dma(mcbsp->dma_tx_sync, "McBSP TX",
 717                                 omap_mcbsp_tx_dma_callback,
 718                                 mcbsp,
 719                                 &dma_tx_ch)) {
 720                 dev_err(mcbsp->dev, " Unable to request DMA channel for "
 721                                 "McBSP%d TX. Trying IRQ based TX\n",
 722                                 mcbsp->id);
 723                 return -EAGAIN;
 724         }
 725         mcbsp->dma_tx_lch = dma_tx_ch;
 726
 727         dev_err(mcbsp->dev, "McBSP%d TX DMA on channel %d\n", mcbsp->id,
 728                 dma_tx_ch);
 729
 730         init_completion(&mcbsp->tx_dma_completion);
 731
 732         if (cpu_class_is_omap1()) {
 733                 src_port = OMAP_DMA_PORT_TIPB;
 734                 dest_port = OMAP_DMA_PORT_EMIFF;
 735         }
 736         if (cpu_class_is_omap2())
 737                 sync_dev = mcbsp->dma_tx_sync;
 738
 739         omap_set_dma_transfer_params(mcbsp->dma_tx_lch,
 740                                      OMAP_DMA_DATA_TYPE_S16,
 741                                      length >> 1, 1,
 742                                      OMAP_DMA_SYNC_ELEMENT,
 743          sync_dev, 0);
 744
 745         omap_set_dma_dest_params(mcbsp->dma_tx_lch,
 746                                  src_port,
 747                                  OMAP_DMA_AMODE_CONSTANT,
 748                                  mcbsp->phys_base + OMAP_MCBSP_REG_DXR1,
 749                                  0, 0);
 750
 751         omap_set_dma_src_params(mcbsp->dma_tx_lch,
 752                                 dest_port,
 753                                 OMAP_DMA_AMODE_POST_INC,
 754                                 buffer,
 755                                 0, 0);
 756
 757         omap_start_dma(mcbsp->dma_tx_lch);
 758         wait_for_completion(&mcbsp->tx_dma_completion);
 759
 760         return 0;
 761 }
 762 EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
 763
 764 int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer,
 765                                 unsigned int length)
 766 {
 767         struct omap_mcbsp *mcbsp;
 768         int dma_rx_ch;
 769         int src_port = 0;
 770         int dest_port = 0;
 771         int sync_dev = 0;
 772
 773         if (!omap_mcbsp_check_valid_id(id)) {
 774                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 775                 return -ENODEV;
 776         }
 777         mcbsp = id_to_mcbsp_ptr(id);
 778
 779         if (omap_request_dma(mcbsp->dma_rx_sync, "McBSP RX",
 780                                 omap_mcbsp_rx_dma_callback,
 781                                 mcbsp,
 782                                 &dma_rx_ch)) {
 783                 dev_err(mcbsp->dev, "Unable to request DMA channel for "
 784                                 "McBSP%d RX. Trying IRQ based RX\n",
 785                                 mcbsp->id);
 786                 return -EAGAIN;
 787         }
 788         mcbsp->dma_rx_lch = dma_rx_ch;
 789
 790         dev_err(mcbsp->dev, "McBSP%d RX DMA on channel %d\n", mcbsp->id,
 791                 dma_rx_ch);
 792
 793         init_completion(&mcbsp->rx_dma_completion);
 794
 795         if (cpu_class_is_omap1()) {
 796                 src_port = OMAP_DMA_PORT_TIPB;
 797                 dest_port = OMAP_DMA_PORT_EMIFF;
 798         }
 799         if (cpu_class_is_omap2())
 800                 sync_dev = mcbsp->dma_rx_sync;
 801
 802         omap_set_dma_transfer_params(mcbsp->dma_rx_lch,
 803                                         OMAP_DMA_DATA_TYPE_S16,
 804                                         length >> 1, 1,
 805                                         OMAP_DMA_SYNC_ELEMENT,
 806                                         sync_dev, 0);
 807
 808         omap_set_dma_src_params(mcbsp->dma_rx_lch,
 809                                 src_port,
 810                                 OMAP_DMA_AMODE_CONSTANT,
 811                                 mcbsp->phys_base + OMAP_MCBSP_REG_DRR1,
 812                                 0, 0);
 813
 814         omap_set_dma_dest_params(mcbsp->dma_rx_lch,
 815                                         dest_port,
 816                                         OMAP_DMA_AMODE_POST_INC,
 817                                         buffer,
 818                                         0, 0);
 819
 820         omap_start_dma(mcbsp->dma_rx_lch);
 821         wait_for_completion(&mcbsp->rx_dma_completion);
 822
 823         return 0;
 824 }
 825 EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
 826
 827 /*
 828  * SPI wrapper.
 829  * Since SPI setup is much simpler than the generic McBSP one,
 830  * this wrapper just need an omap_mcbsp_spi_cfg structure as an input.
 831  * Once this is done, you can call omap_mcbsp_start().
 832  */
 833 void omap_mcbsp_set_spi_mode(unsigned int id,
 834                                 const struct omap_mcbsp_spi_cfg *spi_cfg)
 835 {
 836         struct omap_mcbsp *mcbsp;
 837         struct omap_mcbsp_reg_cfg mcbsp_cfg;
 838
 839         if (!omap_mcbsp_check_valid_id(id)) {
 840                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 841                 return;
 842         }
 843         mcbsp = id_to_mcbsp_ptr(id);
 844
 845         memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg));
 846
 847         /* SPI has only one frame */
 848         mcbsp_cfg.rcr1 |= (RWDLEN1(spi_cfg->word_length) | RFRLEN1(0));
 849         mcbsp_cfg.xcr1 |= (XWDLEN1(spi_cfg->word_length) | XFRLEN1(0));
 850
 851         /* Clock stop mode */
 852         if (spi_cfg->clk_stp_mode == OMAP_MCBSP_CLK_STP_MODE_NO_DELAY)
 853                 mcbsp_cfg.spcr1 |= (1 << 12);
 854         else
 855                 mcbsp_cfg.spcr1 |= (3 << 11);
 856
 857         /* Set clock parities */
 858         if (spi_cfg->rx_clock_polarity == OMAP_MCBSP_CLK_RISING)
 859                 mcbsp_cfg.pcr0 |= CLKRP;
 860         else
 861                 mcbsp_cfg.pcr0 &= ~CLKRP;
 862
 863         if (spi_cfg->tx_clock_polarity == OMAP_MCBSP_CLK_RISING)
 864                 mcbsp_cfg.pcr0 &= ~CLKXP;
 865         else
 866                 mcbsp_cfg.pcr0 |= CLKXP;
 867
 868         /* Set SCLKME to 0 and CLKSM to 1 */
 869         mcbsp_cfg.pcr0 &= ~SCLKME;
 870         mcbsp_cfg.srgr2 |= CLKSM;
 871
 872         /* Set FSXP */
 873         if (spi_cfg->fsx_polarity == OMAP_MCBSP_FS_ACTIVE_HIGH)
 874                 mcbsp_cfg.pcr0 &= ~FSXP;
 875         else
 876                 mcbsp_cfg.pcr0 |= FSXP;
 877
 878         if (spi_cfg->spi_mode == OMAP_MCBSP_SPI_MASTER) {
 879                 mcbsp_cfg.pcr0 |= CLKXM;
 880                 mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div - 1);
 881                 mcbsp_cfg.pcr0 |= FSXM;
 882                 mcbsp_cfg.srgr2 &= ~FSGM;
 883                 mcbsp_cfg.xcr2 |= XDATDLY(1);
 884                 mcbsp_cfg.rcr2 |= RDATDLY(1);
 885         } else {
 886                 mcbsp_cfg.pcr0 &= ~CLKXM;
 887                 mcbsp_cfg.srgr1 |= CLKGDV(1);
 888                 mcbsp_cfg.pcr0 &= ~FSXM;
 889                 mcbsp_cfg.xcr2 &= ~XDATDLY(3);
 890                 mcbsp_cfg.rcr2 &= ~RDATDLY(3);
 891         }
 892
 893         mcbsp_cfg.xcr2 &= ~XPHASE;
 894         mcbsp_cfg.rcr2 &= ~RPHASE;
 895
 896         omap_mcbsp_config(id, &mcbsp_cfg);
 897 }
 898 EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);
 899
 900 /*
 901  * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
 902  * 730 has only 2 McBSP, and both of them are MPU peripherals.
 903  */
 904 static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
 905 {
 906         struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data;
 907         struct omap_mcbsp *mcbsp;
 908         int id = pdev->id - 1;
 909         int ret = 0;
 910
 911         if (!pdata) {
 912                 dev_err(&pdev->dev, "McBSP device initialized without"
 913                                 "platform data\n");
 914                 ret = -EINVAL;
 915                 goto exit;
 916         }
 917
 918         dev_dbg(&pdev->dev, "Initializing OMAP McBSP (%d).\n", pdev->id);
 919
 920         if (id >= omap_mcbsp_count) {
 921                 dev_err(&pdev->dev, "Invalid McBSP device id (%d)\n", id);
 922                 ret = -EINVAL;
 923                 goto exit;
 924         }
 925
 926         mcbsp = kzalloc(sizeof(struct omap_mcbsp), GFP_KERNEL);
 927         if (!mcbsp) {
 928                 ret = -ENOMEM;
 929                 goto exit;
 930         }
 931
 932         spin_lock_init(&mcbsp->lock);
 933         mcbsp->id = id + 1;
 934         mcbsp->free = 1;
 935         mcbsp->dma_tx_lch = -1;
 936         mcbsp->dma_rx_lch = -1;
 937
 938         mcbsp->phys_base = pdata->phys_base;
 939         mcbsp->io_base = ioremap(pdata->phys_base, SZ_4K);
 940         if (!mcbsp->io_base) {
 941                 ret = -ENOMEM;
 942                 goto err_ioremap;
 943         }
 944
 945         /* Default I/O is IRQ based */
 946         mcbsp->io_type = OMAP_MCBSP_IRQ_IO;
 947         mcbsp->tx_irq = pdata->tx_irq;
 948         mcbsp->rx_irq = pdata->rx_irq;
 949         mcbsp->dma_rx_sync = pdata->dma_rx_sync;
 950         mcbsp->dma_tx_sync = pdata->dma_tx_sync;
 951
 952         mcbsp->iclk = clk_get(&pdev->dev, "ick");
 953         if (IS_ERR(mcbsp->iclk)) {
 954                 ret = PTR_ERR(mcbsp->iclk);
 955                 dev_err(&pdev->dev, "unable to get ick: %d\n", ret);
 956                 goto err_iclk;
 957         }
 958
 959         mcbsp->fclk = clk_get(&pdev->dev, "fck");
 960         if (IS_ERR(mcbsp->fclk)) {
 961                 ret = PTR_ERR(mcbsp->fclk);
 962                 dev_err(&pdev->dev, "unable to get fck: %d\n", ret);
 963                 goto err_fclk;
 964         }
 965
 966         mcbsp->pdata = pdata;
 967         mcbsp->dev = &pdev->dev;
 968         mcbsp_ptr[id] = mcbsp;
 969         platform_set_drvdata(pdev, mcbsp);
 970         return 0;
 971
 972 err_fclk:
 973         clk_put(mcbsp->iclk);
 974 err_iclk:
 975         iounmap(mcbsp->io_base);
 976 err_ioremap:
 977         kfree(mcbsp);
 978 exit:
 979         return ret;
 980 }
 981
 982 static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
 983 {
 984         struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
 985
 986         platform_set_drvdata(pdev, NULL);
 987         if (mcbsp) {
 988
 989                 if (mcbsp->pdata && mcbsp->pdata->ops &&
 990                                 mcbsp->pdata->ops->free)
 991                         mcbsp->pdata->ops->free(mcbsp->id);
 992
 993                 clk_disable(mcbsp->fclk);
 994                 clk_disable(mcbsp->iclk);
 995                 clk_put(mcbsp->fclk);
 996                 clk_put(mcbsp->iclk);
 997
 998                 iounmap(mcbsp->io_base);
 999
1000                 mcbsp->fclk = NULL;
1001                 mcbsp->iclk = NULL;
1002                 mcbsp->free = 0;
1003                 mcbsp->dev = NULL;
1004         }
1005
1006         return 0;
1007 }
1008
1009 static struct platform_driver omap_mcbsp_driver = {
1010         .probe          = omap_mcbsp_probe,
1011         .remove         = __devexit_p(omap_mcbsp_remove),
1012         .driver         = {
1013                 .name   = "omap-mcbsp",
1014         },
1015 };
1016
1017 int __init omap_mcbsp_init(void)
1018 {
1019         /* Register the McBSP driver */
1020         return platform_driver_register(&omap_mcbsp_driver);
1021 }