arch/arm/plat-omap/mcbsp.c

   1 /*
   2  * linux/arch/arm/plat-omap/mcbsp.c
   3  *
   4  * Copyright (C) 2004 Nokia Corporation
   5  * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
   6  *
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * Multichannel mode not supported.
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/init.h>
  17 #include <linux/device.h>
  18 #include <linux/wait.h>
  19 #include <linux/completion.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/err.h>
  22 #include <linux/clk.h>
  23 #include <linux/delay.h>
  24
  25 #include <asm/io.h>
  26 #include <asm/irq.h>
  27
  28 #include <asm/arch/dma.h>
  29 #include <asm/arch/mux.h>
  30 #include <asm/arch/irqs.h>
  31 #include <asm/arch/dsp_common.h>
  32 #include <asm/arch/mcbsp.h>
  33
  34 #ifdef CONFIG_MCBSP_DEBUG
  35 #define DBG(x...)       printk(x)
  36 #else
  37 #define DBG(x...)                       do { } while (0)
  38 #endif
  39
  40 struct omap_mcbsp {
  41         u32                          io_base;
  42         u8                           id;
  43         u8                           free;
  44         omap_mcbsp_word_length       rx_word_length;
  45         omap_mcbsp_word_length       tx_word_length;
  46
  47         omap_mcbsp_io_type_t         io_type; /* IRQ or poll */
  48         /* IRQ based TX/RX */
  49         int                          rx_irq;
  50         int                          tx_irq;
  51
  52         /* DMA stuff */
  53         u8                           dma_rx_sync;
  54         short                        dma_rx_lch;
  55         u8                           dma_tx_sync;
  56         short                        dma_tx_lch;
  57
  58         /* Completion queues */
  59         struct completion            tx_irq_completion;
  60         struct completion            rx_irq_completion;
  61         struct completion            tx_dma_completion;
  62         struct completion            rx_dma_completion;
  63
  64         spinlock_t                   lock;
  65 };
  66
  67 static struct omap_mcbsp mcbsp[OMAP_MAX_MCBSP_COUNT];
  68 #ifdef CONFIG_ARCH_OMAP1
  69 static struct clk *mcbsp_dsp_ck = 0;
  70 static struct clk *mcbsp_api_ck = 0;
  71 static struct clk *mcbsp_dspxor_ck = 0;
  72 #endif
  73 #ifdef CONFIG_ARCH_OMAP2
  74 static struct clk *mcbsp1_ick = 0;
  75 static struct clk *mcbsp1_fck = 0;
  76 static struct clk *mcbsp2_ick = 0;
  77 static struct clk *mcbsp2_fck = 0;
  78 #endif
  79
  80 static void omap_mcbsp_dump_reg(u8 id)
  81 {
  82         DBG("**** MCBSP%d regs ****\n", mcbsp[id].id);
  83         DBG("DRR2:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DRR2));
  84         DBG("DRR1:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DRR1));
  85         DBG("DXR2:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DXR2));
  86         DBG("DXR1:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DXR1));
  87         DBG("SPCR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR2));
  88         DBG("SPCR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR1));
  89         DBG("RCR2:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, RCR2));
  90         DBG("RCR1:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, RCR1));
  91         DBG("XCR2:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, XCR2));
  92         DBG("XCR1:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, XCR1));
  93         DBG("SRGR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR2));
  94         DBG("SRGR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR1));
  95         DBG("PCR0:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, PCR0));
  96         DBG("***********************\n");
  97 }
  98
  99 static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
 100 {
 101         struct omap_mcbsp *mcbsp_tx = dev_id;
 102
 103         DBG("TX IRQ callback : 0x%x\n",
 104             OMAP_MCBSP_READ(mcbsp_tx->io_base, SPCR2));
 105
 106         complete(&mcbsp_tx->tx_irq_completion);
 107         return IRQ_HANDLED;
 108 }
 109
 110 static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
 111 {
 112         struct omap_mcbsp *mcbsp_rx = dev_id;
 113
 114         DBG("RX IRQ callback : 0x%x\n",
 115             OMAP_MCBSP_READ(mcbsp_rx->io_base, SPCR2));
 116
 117         complete(&mcbsp_rx->rx_irq_completion);
 118         return IRQ_HANDLED;
 119 }
 120
 121 static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data)
 122 {
 123         struct omap_mcbsp *mcbsp_dma_tx = data;
 124
 125         DBG("TX DMA callback : 0x%x\n",
 126             OMAP_MCBSP_READ(mcbsp_dma_tx->io_base, SPCR2));
 127
 128         /* We can free the channels */
 129         omap_free_dma(mcbsp_dma_tx->dma_tx_lch);
 130         mcbsp_dma_tx->dma_tx_lch = -1;
 131
 132         complete(&mcbsp_dma_tx->tx_dma_completion);
 133 }
 134
 135 static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
 136 {
 137         struct omap_mcbsp *mcbsp_dma_rx = data;
 138
 139         DBG("RX DMA callback : 0x%x\n",
 140             OMAP_MCBSP_READ(mcbsp_dma_rx->io_base, SPCR2));
 141
 142         /* We can free the channels */
 143         omap_free_dma(mcbsp_dma_rx->dma_rx_lch);
 144         mcbsp_dma_rx->dma_rx_lch = -1;
 145
 146         complete(&mcbsp_dma_rx->rx_dma_completion);
 147 }
 148
 149
 150 /*
 151  * omap_mcbsp_config simply write a config to the
 152  * appropriate McBSP.
 153  * You either call this function or set the McBSP registers
 154  * by yourself before calling omap_mcbsp_start().
 155  */
 156
 157 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config)
 158 {
 159         u32 io_base = mcbsp[id].io_base;
 160
 161         DBG("OMAP-McBSP: McBSP%d  io_base: 0x%8x\n", id+1, io_base);
 162
 163         /* We write the given config */
 164         OMAP_MCBSP_WRITE(io_base, SPCR2, config->spcr2);
 165         OMAP_MCBSP_WRITE(io_base, SPCR1, config->spcr1);
 166         OMAP_MCBSP_WRITE(io_base, RCR2, config->rcr2);
 167         OMAP_MCBSP_WRITE(io_base, RCR1, config->rcr1);
 168         OMAP_MCBSP_WRITE(io_base, XCR2, config->xcr2);
 169         OMAP_MCBSP_WRITE(io_base, XCR1, config->xcr1);
 170         OMAP_MCBSP_WRITE(io_base, SRGR2, config->srgr2);
 171         OMAP_MCBSP_WRITE(io_base, SRGR1, config->srgr1);
 172         OMAP_MCBSP_WRITE(io_base, MCR2, config->mcr2);
 173         OMAP_MCBSP_WRITE(io_base, MCR1, config->mcr1);
 174         OMAP_MCBSP_WRITE(io_base, PCR0, config->pcr0);
 175 }
 176
 177
 178
 179 static int omap_mcbsp_check(unsigned int id)
 180 {
 181         if (cpu_is_omap730()) {
 182                 if (id > OMAP_MAX_MCBSP_COUNT - 1) {
 183                        printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n", id + 1);
 184                        return -1;
 185                 }
 186                 return 0;
 187         }
 188
 189         if (cpu_is_omap15xx() || cpu_is_omap16xx() || cpu_is_omap24xx()) {
 190                 if (id > OMAP_MAX_MCBSP_COUNT) {
 191                         printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n", id + 1);
 192                         return -1;
 193                 }
 194                 return 0;
 195         }
 196
 197         return -1;
 198 }
 199
 200 #ifdef CONFIG_ARCH_OMAP1
 201 static void omap_mcbsp_dsp_request(void)
 202 {
 203         if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
 204                 clk_enable(mcbsp_dsp_ck);
 205                 clk_enable(mcbsp_api_ck);
 206
 207                 /* enable 12MHz clock to mcbsp 1 & 3 */
 208                 clk_enable(mcbsp_dspxor_ck);
 209
 210                 /*
 211                  * DSP external peripheral reset
 212                  * FIXME: This should be moved to dsp code
 213                  */
 214                 __raw_writew(__raw_readw(DSP_RSTCT2) | 1 | 1 << 1,
 215                              DSP_RSTCT2);
 216         }
 217 }
 218
 219 static void omap_mcbsp_dsp_free(void)
 220 {
 221         if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
 222                 clk_disable(mcbsp_dspxor_ck);
 223                 clk_disable(mcbsp_dsp_ck);
 224                 clk_disable(mcbsp_api_ck);
 225         }
 226 }
 227 #endif
 228
 229 #ifdef CONFIG_ARCH_OMAP2
 230 static void omap2_mcbsp2_mux_setup(void)
 231 {
 232         if (cpu_is_omap2420()) {
 233                 omap_cfg_reg(Y15_24XX_MCBSP2_CLKX);
 234                 omap_cfg_reg(R14_24XX_MCBSP2_FSX);
 235                 omap_cfg_reg(W15_24XX_MCBSP2_DR);
 236                 omap_cfg_reg(V15_24XX_MCBSP2_DX);
 237                 omap_cfg_reg(V14_24XX_GPIO117);
 238         }
 239         /*
 240          * Need to add MUX settings for OMAP 2430 SDP
 241          */
 242 }
 243 #endif
 244
 245 /*
 246  * We can choose between IRQ based or polled IO.
 247  * This needs to be called before omap_mcbsp_request().
 248  */
 249 int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type)
 250 {
 251         if (omap_mcbsp_check(id) < 0)
 252                 return -EINVAL;
 253
 254         spin_lock(&mcbsp[id].lock);
 255
 256         if (!mcbsp[id].free) {
 257                 printk (KERN_ERR "OMAP-McBSP: McBSP%d is currently in use\n", id + 1);
 258                 spin_unlock(&mcbsp[id].lock);
 259                 return -EINVAL;
 260         }
 261
 262         mcbsp[id].io_type = io_type;
 263
 264         spin_unlock(&mcbsp[id].lock);
 265
 266         return 0;
 267 }
 268
 269 int omap_mcbsp_request(unsigned int id)
 270 {
 271         int err;
 272
 273         if (omap_mcbsp_check(id) < 0)
 274                 return -EINVAL;
 275
 276 #ifdef CONFIG_ARCH_OMAP1
 277         /*
 278          * On 1510, 1610 and 1710, McBSP1 and McBSP3
 279          * are DSP public peripherals.
 280          */
 281         if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3)
 282                 omap_mcbsp_dsp_request();
 283 #endif
 284
 285 #ifdef CONFIG_ARCH_OMAP2
 286         if (cpu_is_omap24xx()) {
 287                 if (id == OMAP_MCBSP1) {
 288                         clk_enable(mcbsp1_ick);
 289                         clk_enable(mcbsp1_fck);
 290                 } else {
 291                         clk_enable(mcbsp2_ick);
 292                         clk_enable(mcbsp2_fck);
 293                 }
 294         }
 295 #endif
 296
 297         spin_lock(&mcbsp[id].lock);
 298         if (!mcbsp[id].free) {
 299                 printk (KERN_ERR "OMAP-McBSP: McBSP%d is currently in use\n", id + 1);
 300                 spin_unlock(&mcbsp[id].lock);
 301                 return -1;
 302         }
 303
 304         mcbsp[id].free = 0;
 305         spin_unlock(&mcbsp[id].lock);
 306
 307         if (mcbsp[id].io_type == OMAP_MCBSP_IRQ_IO) {
 308                 /* We need to get IRQs here */
 309                 err = request_irq(mcbsp[id].tx_irq, omap_mcbsp_tx_irq_handler, 0,
 310                                   "McBSP",
 311                                   (void *) (&mcbsp[id]));
 312                 if (err != 0) {
 313                         printk(KERN_ERR "OMAP-McBSP: Unable to request TX IRQ %d for McBSP%d\n",
 314                                mcbsp[id].tx_irq, mcbsp[id].id);
 315                         return err;
 316                 }
 317
 318                 init_completion(&(mcbsp[id].tx_irq_completion));
 319
 320
 321                 err = request_irq(mcbsp[id].rx_irq, omap_mcbsp_rx_irq_handler, 0,
 322                                   "McBSP",
 323                                   (void *) (&mcbsp[id]));
 324                 if (err != 0) {
 325                         printk(KERN_ERR "OMAP-McBSP: Unable to request RX IRQ %d for McBSP%d\n",
 326                                mcbsp[id].rx_irq, mcbsp[id].id);
 327                         free_irq(mcbsp[id].tx_irq, (void *) (&mcbsp[id]));
 328                         return err;
 329                 }
 330
 331                 init_completion(&(mcbsp[id].rx_irq_completion));
 332         }
 333
 334         return 0;
 335
 336 }
 337
 338 void omap_mcbsp_free(unsigned int id)
 339 {
 340         if (omap_mcbsp_check(id) < 0)
 341                 return;
 342
 343 #ifdef CONFIG_ARCH_OMAP1
 344         if (cpu_class_is_omap1()) {
 345                 if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3)
 346                         omap_mcbsp_dsp_free();
 347         }
 348 #endif
 349
 350 #ifdef CONFIG_ARCH_OMAP2
 351         if (cpu_is_omap24xx()) {
 352                 if (id == OMAP_MCBSP1) {
 353                         clk_disable(mcbsp1_ick);
 354                         clk_disable(mcbsp1_fck);
 355                 } else {
 356                         clk_disable(mcbsp2_ick);
 357                         clk_disable(mcbsp2_fck);
 358                 }
 359         }
 360 #endif
 361
 362         spin_lock(&mcbsp[id].lock);
 363         if (mcbsp[id].free) {
 364                 printk (KERN_ERR "OMAP-McBSP: McBSP%d was not reserved\n", id + 1);
 365                 spin_unlock(&mcbsp[id].lock);
 366                 return;
 367         }
 368
 369         mcbsp[id].free = 1;
 370         spin_unlock(&mcbsp[id].lock);
 371
 372         if (mcbsp[id].io_type == OMAP_MCBSP_IRQ_IO) {
 373                 /* Free IRQs */
 374                 free_irq(mcbsp[id].rx_irq, (void *) (&mcbsp[id]));
 375                 free_irq(mcbsp[id].tx_irq, (void *) (&mcbsp[id]));
 376         }
 377 }
 378
 379 /*
 380  * Here we start the McBSP, by enabling the sample
 381  * generator, both transmitter and receivers,
 382  * and the frame sync.
 383  */
 384 void omap_mcbsp_start(unsigned int id)
 385 {
 386         u32 io_base;
 387         u16 w;
 388
 389         if (omap_mcbsp_check(id) < 0)
 390                 return;
 391
 392         io_base = mcbsp[id].io_base;
 393
 394         mcbsp[id].rx_word_length = ((OMAP_MCBSP_READ(io_base, RCR1) >> 5) & 0x7);
 395         mcbsp[id].tx_word_length = ((OMAP_MCBSP_READ(io_base, XCR1) >> 5) & 0x7);
 396
 397         /* Start the sample generator */
 398         w = OMAP_MCBSP_READ(io_base, SPCR2);
 399         OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 6));
 400
 401         /* Enable transmitter and receiver */
 402         w = OMAP_MCBSP_READ(io_base, SPCR2);
 403         OMAP_MCBSP_WRITE(io_base, SPCR2, w | 1);
 404
 405         w = OMAP_MCBSP_READ(io_base, SPCR1);
 406         OMAP_MCBSP_WRITE(io_base, SPCR1, w | 1);
 407
 408         udelay(100);
 409
 410         /* Start frame sync */
 411         w = OMAP_MCBSP_READ(io_base, SPCR2);
 412         OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 7));
 413
 414         /* Dump McBSP Regs */
 415         omap_mcbsp_dump_reg(id);
 416
 417 }
 418
 419 void omap_mcbsp_stop(unsigned int id)
 420 {
 421         u32 io_base;
 422         u16 w;
 423
 424         if (omap_mcbsp_check(id) < 0)
 425                 return;
 426
 427         io_base = mcbsp[id].io_base;
 428
 429         /* Reset transmitter */
 430         w = OMAP_MCBSP_READ(io_base, SPCR2);
 431         OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1));
 432
 433         /* Reset receiver */
 434         w = OMAP_MCBSP_READ(io_base, SPCR1);
 435         OMAP_MCBSP_WRITE(io_base, SPCR1, w & ~(1));
 436
 437         /* Reset the sample rate generator */
 438         w = OMAP_MCBSP_READ(io_base, SPCR2);
 439         OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1 << 6));
 440 }
 441
 442
 443 /* polled mcbsp i/o operations */
 444 int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
 445 {
 446         u32 base = mcbsp[id].io_base;
 447         writew(buf, base + OMAP_MCBSP_REG_DXR1);
 448         /* if frame sync error - clear the error */
 449         if (readw(base + OMAP_MCBSP_REG_SPCR2) & XSYNC_ERR) {
 450                 /* clear error */
 451                 writew(readw(base + OMAP_MCBSP_REG_SPCR2) & (~XSYNC_ERR),
 452                        base + OMAP_MCBSP_REG_SPCR2);
 453                 /* resend */
 454                 return -1;
 455         } else {
 456                 /* wait for transmit confirmation */
 457                 int attemps = 0;
 458                 while (!(readw(base + OMAP_MCBSP_REG_SPCR2) & XRDY)) {
 459                         if (attemps++ > 1000) {
 460                                 writew(readw(base + OMAP_MCBSP_REG_SPCR2) &
 461                                        (~XRST),
 462                                        base + OMAP_MCBSP_REG_SPCR2);
 463                                 udelay(10);
 464                                 writew(readw(base + OMAP_MCBSP_REG_SPCR2) |
 465                                        (XRST),
 466                                        base + OMAP_MCBSP_REG_SPCR2);
 467                                 udelay(10);
 468                                 printk(KERN_ERR
 469                                        " Could not write to McBSP Register\n");
 470                                 return -2;
 471                         }
 472                 }
 473         }
 474         return 0;
 475 }
 476
 477 int omap_mcbsp_pollread(unsigned int id, u16 * buf)
 478 {
 479         u32 base = mcbsp[id].io_base;
 480         /* if frame sync error - clear the error */
 481         if (readw(base + OMAP_MCBSP_REG_SPCR1) & RSYNC_ERR) {
 482                 /* clear error */
 483                 writew(readw(base + OMAP_MCBSP_REG_SPCR1) & (~RSYNC_ERR),
 484                        base + OMAP_MCBSP_REG_SPCR1);
 485                 /* resend */
 486                 return -1;
 487         } else {
 488                 /* wait for recieve confirmation */
 489                 int attemps = 0;
 490                 while (!(readw(base + OMAP_MCBSP_REG_SPCR1) & RRDY)) {
 491                         if (attemps++ > 1000) {
 492                                 writew(readw(base + OMAP_MCBSP_REG_SPCR1) &
 493                                        (~RRST),
 494                                        base + OMAP_MCBSP_REG_SPCR1);
 495                                 udelay(10);
 496                                 writew(readw(base + OMAP_MCBSP_REG_SPCR1) |
 497                                        (RRST),
 498                                        base + OMAP_MCBSP_REG_SPCR1);
 499                                 udelay(10);
 500                                 printk(KERN_ERR
 501                                        " Could not read from McBSP Register\n");
 502                                 return -2;
 503                         }
 504                 }
 505         }
 506         *buf = readw(base + OMAP_MCBSP_REG_DRR1);
 507         return 0;
 508 }
 509
 510 /*
 511  * IRQ based word transmission.
 512  */
 513 void omap_mcbsp_xmit_word(unsigned int id, u32 word)
 514 {
 515         u32 io_base;
 516         omap_mcbsp_word_length word_length = mcbsp[id].tx_word_length;
 517
 518         if (omap_mcbsp_check(id) < 0)
 519                 return;
 520
 521         io_base = mcbsp[id].io_base;
 522
 523         wait_for_completion(&(mcbsp[id].tx_irq_completion));
 524
 525         if (word_length > OMAP_MCBSP_WORD_16)
 526                 OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16);
 527         OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff);
 528 }
 529
 530 u32 omap_mcbsp_recv_word(unsigned int id)
 531 {
 532         u32 io_base;
 533         u16 word_lsb, word_msb = 0;
 534         omap_mcbsp_word_length word_length = mcbsp[id].rx_word_length;
 535
 536         if (omap_mcbsp_check(id) < 0)
 537                 return -EINVAL;
 538
 539         io_base = mcbsp[id].io_base;
 540
 541         wait_for_completion(&(mcbsp[id].rx_irq_completion));
 542
 543         if (word_length > OMAP_MCBSP_WORD_16)
 544                 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
 545         word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
 546
 547         return (word_lsb | (word_msb << 16));
 548 }
 549
 550
 551 int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
 552 {
 553         u32 io_base = mcbsp[id].io_base;
 554         omap_mcbsp_word_length tx_word_length = mcbsp[id].tx_word_length;
 555         omap_mcbsp_word_length rx_word_length = mcbsp[id].rx_word_length;
 556         u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
 557
 558         if (tx_word_length != rx_word_length)
 559                 return -EINVAL;
 560
 561         /* First we wait for the transmitter to be ready */
 562         spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
 563         while (!(spcr2 & XRDY)) {
 564                 spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
 565                 if (attempts++ > 1000) {
 566                         /* We must reset the transmitter */
 567                         OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 & (~XRST));
 568                         udelay(10);
 569                         OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
 570                         udelay(10);
 571                         printk("McBSP transmitter not ready\n");
 572                         return -EAGAIN;
 573                 }
 574         }
 575
 576         /* Now we can push the data */
 577         if (tx_word_length > OMAP_MCBSP_WORD_16)
 578                 OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16);
 579         OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff);
 580
 581         /* We wait for the receiver to be ready */
 582         spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
 583         while (!(spcr1 & RRDY)) {
 584                 spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
 585                 if (attempts++ > 1000) {
 586                         /* We must reset the receiver */
 587                         OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 & (~RRST));
 588                         udelay(10);
 589                         OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
 590                         udelay(10);
 591                         printk("McBSP receiver not ready\n");
 592                         return -EAGAIN;
 593                 }
 594         }
 595
 596         /* Receiver is ready, let's read the dummy data */
 597         if (rx_word_length > OMAP_MCBSP_WORD_16)
 598                 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
 599         word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
 600
 601         return 0;
 602 }
 603
 604 int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word)
 605 {
 606         u32 io_base = mcbsp[id].io_base, clock_word = 0;
 607         omap_mcbsp_word_length tx_word_length = mcbsp[id].tx_word_length;
 608         omap_mcbsp_word_length rx_word_length = mcbsp[id].rx_word_length;
 609         u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
 610
 611         if (tx_word_length != rx_word_length)
 612                 return -EINVAL;
 613
 614         /* First we wait for the transmitter to be ready */
 615         spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
 616         while (!(spcr2 & XRDY)) {
 617                 spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
 618                 if (attempts++ > 1000) {
 619                         /* We must reset the transmitter */
 620                         OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 & (~XRST));
 621                         udelay(10);
 622                         OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
 623                         udelay(10);
 624                         printk("McBSP transmitter not ready\n");
 625                         return -EAGAIN;
 626                 }
 627         }
 628
 629         /* We first need to enable the bus clock */
 630         if (tx_word_length > OMAP_MCBSP_WORD_16)
 631                 OMAP_MCBSP_WRITE(io_base, DXR2, clock_word >> 16);
 632         OMAP_MCBSP_WRITE(io_base, DXR1, clock_word & 0xffff);
 633
 634         /* We wait for the receiver to be ready */
 635         spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
 636         while (!(spcr1 & RRDY)) {
 637                 spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
 638                 if (attempts++ > 1000) {
 639                         /* We must reset the receiver */
 640                         OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 & (~RRST));
 641                         udelay(10);
 642                         OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
 643                         udelay(10);
 644                         printk("McBSP receiver not ready\n");
 645                         return -EAGAIN;
 646                 }
 647         }
 648
 649         /* Receiver is ready, there is something for us */
 650         if (rx_word_length > OMAP_MCBSP_WORD_16)
 651                 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
 652         word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
 653
 654         word[0] = (word_lsb | (word_msb << 16));
 655
 656         return 0;
 657 }
 658
 659
 660 /*
 661  * Simple DMA based buffer rx/tx routines.
 662  * Nothing fancy, just a single buffer tx/rx through DMA.
 663  * The DMA resources are released once the transfer is done.
 664  * For anything fancier, you should use your own customized DMA
 665  * routines and callbacks.
 666  */
 667 int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length)
 668 {
 669         int dma_tx_ch;
 670         int src_port = 0;
 671         int dest_port = 0;
 672         int sync_dev = 0;
 673
 674         if (omap_mcbsp_check(id) < 0)
 675                 return -EINVAL;
 676
 677         if (omap_request_dma(mcbsp[id].dma_tx_sync, "McBSP TX", omap_mcbsp_tx_dma_callback,
 678                              &mcbsp[id],
 679                              &dma_tx_ch)) {
 680                 printk("OMAP-McBSP: Unable to request DMA channel for McBSP%d TX. Trying IRQ based TX\n", id+1);
 681                 return -EAGAIN;
 682         }
 683         mcbsp[id].dma_tx_lch = dma_tx_ch;
 684
 685         DBG("TX DMA on channel %d\n", dma_tx_ch);
 686
 687         init_completion(&(mcbsp[id].tx_dma_completion));
 688
 689         if (cpu_class_is_omap1()) {
 690                 src_port = OMAP_DMA_PORT_TIPB;
 691                 dest_port = OMAP_DMA_PORT_EMIFF;
 692         }
 693         if (cpu_is_omap24xx())
 694                 sync_dev = mcbsp[id].dma_tx_sync;
 695
 696         omap_set_dma_transfer_params(mcbsp[id].dma_tx_lch,
 697                                      OMAP_DMA_DATA_TYPE_S16,
 698                                      length >> 1, 1,
 699                                      OMAP_DMA_SYNC_ELEMENT,
 700          sync_dev, 0);
 701
 702         omap_set_dma_dest_params(mcbsp[id].dma_tx_lch,
 703                                  src_port,
 704                                  OMAP_DMA_AMODE_CONSTANT,
 705                                  mcbsp[id].io_base + OMAP_MCBSP_REG_DXR1,
 706                                  0, 0);
 707
 708         omap_set_dma_src_params(mcbsp[id].dma_tx_lch,
 709                                 dest_port,
 710                                 OMAP_DMA_AMODE_POST_INC,
 711                                 buffer,
 712                                 0, 0);
 713
 714         omap_start_dma(mcbsp[id].dma_tx_lch);
 715         wait_for_completion(&(mcbsp[id].tx_dma_completion));
 716         return 0;
 717 }
 718
 719
 720 int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length)
 721 {
 722         int dma_rx_ch;
 723         int src_port = 0;
 724         int dest_port = 0;
 725         int sync_dev = 0;
 726
 727         if (omap_mcbsp_check(id) < 0)
 728                 return -EINVAL;
 729
 730         if (omap_request_dma(mcbsp[id].dma_rx_sync, "McBSP RX", omap_mcbsp_rx_dma_callback,
 731                              &mcbsp[id],
 732                              &dma_rx_ch)) {
 733                 printk("Unable to request DMA channel for McBSP%d RX. Trying IRQ based RX\n", id+1);
 734                 return -EAGAIN;
 735         }
 736         mcbsp[id].dma_rx_lch = dma_rx_ch;
 737
 738         DBG("RX DMA on channel %d\n", dma_rx_ch);
 739
 740         init_completion(&(mcbsp[id].rx_dma_completion));
 741
 742         if (cpu_class_is_omap1()) {
 743                 src_port = OMAP_DMA_PORT_TIPB;
 744                 dest_port = OMAP_DMA_PORT_EMIFF;
 745         }
 746         if (cpu_is_omap24xx())
 747                 sync_dev = mcbsp[id].dma_rx_sync;
 748
 749         omap_set_dma_transfer_params(mcbsp[id].dma_rx_lch,
 750                                      OMAP_DMA_DATA_TYPE_S16,
 751                                      length >> 1, 1,
 752                                      OMAP_DMA_SYNC_ELEMENT,
 753          sync_dev, 0);
 754
 755         omap_set_dma_src_params(mcbsp[id].dma_rx_lch,
 756                                 src_port,
 757                                 OMAP_DMA_AMODE_CONSTANT,
 758                                 mcbsp[id].io_base + OMAP_MCBSP_REG_DRR1,
 759                                 0, 0);
 760
 761         omap_set_dma_dest_params(mcbsp[id].dma_rx_lch,
 762                                  dest_port,
 763                                  OMAP_DMA_AMODE_POST_INC,
 764                                  buffer,
 765                                  0, 0);
 766
 767         omap_start_dma(mcbsp[id].dma_rx_lch);
 768         wait_for_completion(&(mcbsp[id].rx_dma_completion));
 769         return 0;
 770 }
 771
 772
 773 /*
 774  * SPI wrapper.
 775  * Since SPI setup is much simpler than the generic McBSP one,
 776  * this wrapper just need an omap_mcbsp_spi_cfg structure as an input.
 777  * Once this is done, you can call omap_mcbsp_start().
 778  */
 779 void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg)
 780 {
 781         struct omap_mcbsp_reg_cfg mcbsp_cfg;
 782
 783         if (omap_mcbsp_check(id) < 0)
 784                 return;
 785
 786         memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg));
 787
 788         /* SPI has only one frame */
 789         mcbsp_cfg.rcr1 |= (RWDLEN1(spi_cfg->word_length) | RFRLEN1(0));
 790         mcbsp_cfg.xcr1 |= (XWDLEN1(spi_cfg->word_length) | XFRLEN1(0));
 791
 792         /* Clock stop mode */
 793         if (spi_cfg->clk_stp_mode == OMAP_MCBSP_CLK_STP_MODE_NO_DELAY)
 794                 mcbsp_cfg.spcr1 |= (1 << 12);
 795         else
 796                 mcbsp_cfg.spcr1 |= (3 << 11);
 797
 798         /* Set clock parities */
 799         if (spi_cfg->rx_clock_polarity == OMAP_MCBSP_CLK_RISING)
 800                 mcbsp_cfg.pcr0 |= CLKRP;
 801         else
 802                 mcbsp_cfg.pcr0 &= ~CLKRP;
 803
 804         if (spi_cfg->tx_clock_polarity == OMAP_MCBSP_CLK_RISING)
 805                 mcbsp_cfg.pcr0 &= ~CLKXP;
 806         else
 807                 mcbsp_cfg.pcr0 |= CLKXP;
 808
 809         /* Set SCLKME to 0 and CLKSM to 1 */
 810         mcbsp_cfg.pcr0 &= ~SCLKME;
 811         mcbsp_cfg.srgr2 |= CLKSM;
 812
 813         /* Set FSXP */
 814         if (spi_cfg->fsx_polarity == OMAP_MCBSP_FS_ACTIVE_HIGH)
 815                 mcbsp_cfg.pcr0 &= ~FSXP;
 816         else
 817                 mcbsp_cfg.pcr0 |= FSXP;
 818
 819         if (spi_cfg->spi_mode == OMAP_MCBSP_SPI_MASTER) {
 820                 mcbsp_cfg.pcr0 |= CLKXM;
 821                 mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div -1);
 822                 mcbsp_cfg.pcr0 |= FSXM;
 823                 mcbsp_cfg.srgr2 &= ~FSGM;
 824                 mcbsp_cfg.xcr2 |= XDATDLY(1);
 825                 mcbsp_cfg.rcr2 |= RDATDLY(1);
 826         }
 827         else {
 828                 mcbsp_cfg.pcr0 &= ~CLKXM;
 829                 mcbsp_cfg.srgr1 |= CLKGDV(1);
 830                 mcbsp_cfg.pcr0 &= ~FSXM;
 831                 mcbsp_cfg.xcr2 &= ~XDATDLY(3);
 832                 mcbsp_cfg.rcr2 &= ~RDATDLY(3);
 833         }
 834
 835         mcbsp_cfg.xcr2 &= ~XPHASE;
 836         mcbsp_cfg.rcr2 &= ~RPHASE;
 837
 838         omap_mcbsp_config(id, &mcbsp_cfg);
 839 }
 840
 841
 842 /*
 843  * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
 844  * 730 has only 2 McBSP, and both of them are MPU peripherals.
 845  */
 846 struct omap_mcbsp_info {
 847         u32 virt_base;
 848         u8 dma_rx_sync, dma_tx_sync;
 849         u16 rx_irq, tx_irq;
 850 };
 851
 852 #ifdef CONFIG_ARCH_OMAP730
 853 static const struct omap_mcbsp_info mcbsp_730[] = {
 854         [0] = { .virt_base = io_p2v(OMAP730_MCBSP1_BASE),
 855                 .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
 856                 .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
 857                 .rx_irq = INT_730_McBSP1RX,
 858                 .tx_irq = INT_730_McBSP1TX },
 859         [1] = { .virt_base = io_p2v(OMAP730_MCBSP2_BASE),
 860                 .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
 861                 .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
 862                 .rx_irq = INT_730_McBSP2RX,
 863                 .tx_irq = INT_730_McBSP2TX },
 864 };
 865 #endif
 866
 867 #ifdef CONFIG_ARCH_OMAP15XX
 868 static const struct omap_mcbsp_info mcbsp_1510[] = {
 869         [0] = { .virt_base = OMAP1510_MCBSP1_BASE,
 870                 .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
 871                 .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
 872                 .rx_irq = INT_McBSP1RX,
 873                 .tx_irq = INT_McBSP1TX },
 874         [1] = { .virt_base = io_p2v(OMAP1510_MCBSP2_BASE),
 875                 .dma_rx_sync = OMAP_DMA_MCBSP2_RX,
 876                 .dma_tx_sync = OMAP_DMA_MCBSP2_TX,
 877                 .rx_irq = INT_1510_SPI_RX,
 878                 .tx_irq = INT_1510_SPI_TX },
 879         [2] = { .virt_base = OMAP1510_MCBSP3_BASE,
 880                 .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
 881                 .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
 882                 .rx_irq = INT_McBSP3RX,
 883                 .tx_irq = INT_McBSP3TX },
 884 };
 885 #endif
 886
 887 #if defined(CONFIG_ARCH_OMAP16XX)
 888 static const struct omap_mcbsp_info mcbsp_1610[] = {
 889         [0] = { .virt_base = OMAP1610_MCBSP1_BASE,
 890                 .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
 891                 .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
 892                 .rx_irq = INT_McBSP1RX,
 893                 .tx_irq = INT_McBSP1TX },
 894         [1] = { .virt_base = io_p2v(OMAP1610_MCBSP2_BASE),
 895                 .dma_rx_sync = OMAP_DMA_MCBSP2_RX,
 896                 .dma_tx_sync = OMAP_DMA_MCBSP2_TX,
 897                 .rx_irq = INT_1610_McBSP2_RX,
 898                 .tx_irq = INT_1610_McBSP2_TX },
 899         [2] = { .virt_base = OMAP1610_MCBSP3_BASE,
 900                 .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
 901                 .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
 902                 .rx_irq = INT_McBSP3RX,
 903                 .tx_irq = INT_McBSP3TX },
 904 };
 905 #endif
 906
 907 #if defined(CONFIG_ARCH_OMAP24XX)
 908 static const struct omap_mcbsp_info mcbsp_24xx[] = {
 909         [0] = { .virt_base = IO_ADDRESS(OMAP24XX_MCBSP1_BASE),
 910                 .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX,
 911                 .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
 912                 .rx_irq = INT_24XX_MCBSP1_IRQ_RX,
 913                 .tx_irq = INT_24XX_MCBSP1_IRQ_TX,
 914                 },
 915         [1] = { .virt_base = IO_ADDRESS(OMAP24XX_MCBSP2_BASE),
 916                 .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
 917                 .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
 918                 .rx_irq = INT_24XX_MCBSP2_IRQ_RX,
 919                 .tx_irq = INT_24XX_MCBSP2_IRQ_TX,
 920                 },
 921 };
 922 #endif
 923
 924 static int __init omap_mcbsp_init(void)
 925 {
 926         int mcbsp_count = 0, i;
 927         static const struct omap_mcbsp_info *mcbsp_info;
 928
 929         printk("Initializing OMAP McBSP system\n");
 930
 931 #ifdef CONFIG_ARCH_OMAP1
 932         mcbsp_dsp_ck = clk_get(0, "dsp_ck");
 933         if (IS_ERR(mcbsp_dsp_ck)) {
 934                 printk(KERN_ERR "mcbsp: could not acquire dsp_ck handle.\n");
 935                 return PTR_ERR(mcbsp_dsp_ck);
 936         }
 937         mcbsp_api_ck = clk_get(0, "api_ck");
 938         if (IS_ERR(mcbsp_api_ck)) {
 939                 printk(KERN_ERR "mcbsp: could not acquire api_ck handle.\n");
 940                 return PTR_ERR(mcbsp_api_ck);
 941         }
 942         mcbsp_dspxor_ck = clk_get(0, "dspxor_ck");
 943         if (IS_ERR(mcbsp_dspxor_ck)) {
 944                 printk(KERN_ERR "mcbsp: could not acquire dspxor_ck handle.\n");
 945                 return PTR_ERR(mcbsp_dspxor_ck);
 946         }
 947 #endif
 948 #ifdef CONFIG_ARCH_OMAP2
 949         mcbsp1_ick = clk_get(0, "mcbsp1_ick");
 950         if (IS_ERR(mcbsp1_ick)) {
 951                 printk(KERN_ERR "mcbsp: could not acquire mcbsp1_ick handle.\n");
 952                 return PTR_ERR(mcbsp1_ick);
 953         }
 954         mcbsp1_fck = clk_get(0, "mcbsp1_fck");
 955         if (IS_ERR(mcbsp1_fck)) {
 956                 printk(KERN_ERR "mcbsp: could not acquire mcbsp1_fck handle.\n");
 957                 return PTR_ERR(mcbsp1_fck);
 958         }
 959         mcbsp2_ick = clk_get(0, "mcbsp2_ick");
 960         if (IS_ERR(mcbsp2_ick)) {
 961                 printk(KERN_ERR "mcbsp: could not acquire mcbsp2_ick handle.\n");
 962                 return PTR_ERR(mcbsp2_ick);
 963         }
 964         mcbsp2_fck = clk_get(0, "mcbsp2_fck");
 965         if (IS_ERR(mcbsp2_fck)) {
 966                 printk(KERN_ERR "mcbsp: could not acquire mcbsp2_fck handle.\n");
 967                 return PTR_ERR(mcbsp2_fck);
 968         }
 969 #endif
 970
 971 #ifdef CONFIG_ARCH_OMAP730
 972         if (cpu_is_omap730()) {
 973                 mcbsp_info = mcbsp_730;
 974                 mcbsp_count = ARRAY_SIZE(mcbsp_730);
 975         }
 976 #endif
 977 #ifdef CONFIG_ARCH_OMAP15XX
 978         if (cpu_is_omap15xx()) {
 979                 mcbsp_info = mcbsp_1510;
 980                 mcbsp_count = ARRAY_SIZE(mcbsp_1510);
 981         }
 982 #endif
 983 #if defined(CONFIG_ARCH_OMAP16XX)
 984         if (cpu_is_omap16xx()) {
 985                 mcbsp_info = mcbsp_1610;
 986                 mcbsp_count = ARRAY_SIZE(mcbsp_1610);
 987         }
 988 #endif
 989 #if defined(CONFIG_ARCH_OMAP24XX)
 990         if (cpu_is_omap24xx()) {
 991                 mcbsp_info = mcbsp_24xx;
 992                 mcbsp_count = ARRAY_SIZE(mcbsp_24xx);
 993                 omap2_mcbsp2_mux_setup();
 994         }
 995 #endif
 996         for (i = 0; i < OMAP_MAX_MCBSP_COUNT ; i++) {
 997                 if (i >= mcbsp_count) {
 998                         mcbsp[i].io_base = 0;
 999                         mcbsp[i].free = 0;
1000                         continue;
1001                 }
1002                 mcbsp[i].id = i + 1;
1003                 mcbsp[i].free = 1;
1004                 mcbsp[i].dma_tx_lch = -1;
1005                 mcbsp[i].dma_rx_lch = -1;
1006
1007                 mcbsp[i].io_base = mcbsp_info[i].virt_base;
1008                 mcbsp[i].io_type = OMAP_MCBSP_IRQ_IO; /* Default I/O is IRQ based */
1009                 mcbsp[i].tx_irq = mcbsp_info[i].tx_irq;
1010                 mcbsp[i].rx_irq = mcbsp_info[i].rx_irq;
1011                 mcbsp[i].dma_rx_sync = mcbsp_info[i].dma_rx_sync;
1012                 mcbsp[i].dma_tx_sync = mcbsp_info[i].dma_tx_sync;
1013                 spin_lock_init(&mcbsp[i].lock);
1014         }
1015
1016         return 0;
1017 }
1018
1019 arch_initcall(omap_mcbsp_init);
1020
1021 EXPORT_SYMBOL(omap_mcbsp_config);
1022 EXPORT_SYMBOL(omap_mcbsp_request);
1023 EXPORT_SYMBOL(omap_mcbsp_set_io_type);
1024 EXPORT_SYMBOL(omap_mcbsp_free);
1025 EXPORT_SYMBOL(omap_mcbsp_start);
1026 EXPORT_SYMBOL(omap_mcbsp_stop);
1027 EXPORT_SYMBOL(omap_mcbsp_xmit_word);
1028 EXPORT_SYMBOL(omap_mcbsp_recv_word);
1029 EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
1030 EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
1031 EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll);
1032 EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll);
1033 EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);