arch/arm/plat-omap/mcbsp.c

   1 /*
   2  * linux/arch/arm/plat-omap/mcbsp.c
   3  *
   4  * Copyright (C) 2004 Nokia Corporation
   5  * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
   6  *
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * Multichannel mode not supported.
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/init.h>
  17 #include <linux/device.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/wait.h>
  20 #include <linux/completion.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/err.h>
  23 #include <linux/clk.h>
  24 #include <linux/delay.h>
  25 #include <linux/io.h>
  26
  27 #include <plat/dma.h>
  28 #include <plat/mcbsp.h>
  29
  30 #include "../mach-omap2/cm-regbits-34xx.h"
  31
  32 struct omap_mcbsp **mcbsp_ptr;
  33 int omap_mcbsp_count, omap_mcbsp_cache_size;
  34
  35 void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
  36 {
  37         if (cpu_class_is_omap1()) {
  38                 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)] = (u16)val;
  39                 __raw_writew((u16)val, mcbsp->io_base + reg);
  40         } else if (cpu_is_omap2420()) {
  41                 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)] = (u16)val;
  42                 __raw_writew((u16)val, mcbsp->io_base + reg);
  43         } else {
  44                 ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)] = val;
  45                 __raw_writel(val, mcbsp->io_base + reg);
  46         }
  47 }
  48
  49 int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache)
  50 {
  51         if (cpu_class_is_omap1()) {
  52                 return !from_cache ? __raw_readw(mcbsp->io_base + reg) :
  53                                 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)];
  54         } else if (cpu_is_omap2420()) {
  55                 return !from_cache ? __raw_readw(mcbsp->io_base + reg) :
  56                                 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)];
  57         } else {
  58                 return !from_cache ? __raw_readl(mcbsp->io_base + reg) :
  59                                 ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)];
  60         }
  61 }
  62
  63 #ifdef CONFIG_ARCH_OMAP3
  64 void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
  65 {
  66         __raw_writel(val, mcbsp->st_data->io_base_st + reg);
  67 }
  68
  69 int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg)
  70 {
  71         return __raw_readl(mcbsp->st_data->io_base_st + reg);
  72 }
  73 #endif
  74
  75 #define MCBSP_READ(mcbsp, reg) \
  76                 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 0)
  77 #define MCBSP_WRITE(mcbsp, reg, val) \
  78                 omap_mcbsp_write(mcbsp, OMAP_MCBSP_REG_##reg, val)
  79 #define MCBSP_READ_CACHE(mcbsp, reg) \
  80                 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1)
  81
  82 #define omap_mcbsp_check_valid_id(id)   (id < omap_mcbsp_count)
  83 #define id_to_mcbsp_ptr(id)             mcbsp_ptr[id];
  84
  85 #define MCBSP_ST_READ(mcbsp, reg) \
  86                         omap_mcbsp_st_read(mcbsp, OMAP_ST_REG_##reg)
  87 #define MCBSP_ST_WRITE(mcbsp, reg, val) \
  88                         omap_mcbsp_st_write(mcbsp, OMAP_ST_REG_##reg, val)
  89
  90 static void omap_mcbsp_dump_reg(u8 id)
  91 {
  92         struct omap_mcbsp *mcbsp = id_to_mcbsp_ptr(id);
  93
  94         dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
  95         dev_dbg(mcbsp->dev, "DRR2:  0x%04x\n",
  96                         MCBSP_READ(mcbsp, DRR2));
  97         dev_dbg(mcbsp->dev, "DRR1:  0x%04x\n",
  98                         MCBSP_READ(mcbsp, DRR1));
  99         dev_dbg(mcbsp->dev, "DXR2:  0x%04x\n",
 100                         MCBSP_READ(mcbsp, DXR2));
 101         dev_dbg(mcbsp->dev, "DXR1:  0x%04x\n",
 102                         MCBSP_READ(mcbsp, DXR1));
 103         dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n",
 104                         MCBSP_READ(mcbsp, SPCR2));
 105         dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n",
 106                         MCBSP_READ(mcbsp, SPCR1));
 107         dev_dbg(mcbsp->dev, "RCR2:  0x%04x\n",
 108                         MCBSP_READ(mcbsp, RCR2));
 109         dev_dbg(mcbsp->dev, "RCR1:  0x%04x\n",
 110                         MCBSP_READ(mcbsp, RCR1));
 111         dev_dbg(mcbsp->dev, "XCR2:  0x%04x\n",
 112                         MCBSP_READ(mcbsp, XCR2));
 113         dev_dbg(mcbsp->dev, "XCR1:  0x%04x\n",
 114                         MCBSP_READ(mcbsp, XCR1));
 115         dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n",
 116                         MCBSP_READ(mcbsp, SRGR2));
 117         dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n",
 118                         MCBSP_READ(mcbsp, SRGR1));
 119         dev_dbg(mcbsp->dev, "PCR0:  0x%04x\n",
 120                         MCBSP_READ(mcbsp, PCR0));
 121         dev_dbg(mcbsp->dev, "***********************\n");
 122 }
 123
 124 static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
 125 {
 126         struct omap_mcbsp *mcbsp_tx = dev_id;
 127         u16 irqst_spcr2;
 128
 129         irqst_spcr2 = MCBSP_READ(mcbsp_tx, SPCR2);
 130         dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
 131
 132         if (irqst_spcr2 & XSYNC_ERR) {
 133                 dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n",
 134                         irqst_spcr2);
 135                 /* Writing zero to XSYNC_ERR clears the IRQ */
 136                 MCBSP_WRITE(mcbsp_tx, SPCR2,
 137                             MCBSP_READ_CACHE(mcbsp_tx, SPCR2) & ~(XSYNC_ERR));
 138         } else {
 139                 complete(&mcbsp_tx->tx_irq_completion);
 140         }
 141
 142         return IRQ_HANDLED;
 143 }
 144
 145 static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
 146 {
 147         struct omap_mcbsp *mcbsp_rx = dev_id;
 148         u16 irqst_spcr1;
 149
 150         irqst_spcr1 = MCBSP_READ(mcbsp_rx, SPCR1);
 151         dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
 152
 153         if (irqst_spcr1 & RSYNC_ERR) {
 154                 dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n",
 155                         irqst_spcr1);
 156                 /* Writing zero to RSYNC_ERR clears the IRQ */
 157                 MCBSP_WRITE(mcbsp_rx, SPCR1,
 158                             MCBSP_READ_CACHE(mcbsp_rx, SPCR1) & ~(RSYNC_ERR));
 159         } else {
 160                 complete(&mcbsp_rx->tx_irq_completion);
 161         }
 162
 163         return IRQ_HANDLED;
 164 }
 165
 166 static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data)
 167 {
 168         struct omap_mcbsp *mcbsp_dma_tx = data;
 169
 170         dev_dbg(mcbsp_dma_tx->dev, "TX DMA callback : 0x%x\n",
 171                 MCBSP_READ(mcbsp_dma_tx, SPCR2));
 172
 173         /* We can free the channels */
 174         omap_free_dma(mcbsp_dma_tx->dma_tx_lch);
 175         mcbsp_dma_tx->dma_tx_lch = -1;
 176
 177         complete(&mcbsp_dma_tx->tx_dma_completion);
 178 }
 179
 180 static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
 181 {
 182         struct omap_mcbsp *mcbsp_dma_rx = data;
 183
 184         dev_dbg(mcbsp_dma_rx->dev, "RX DMA callback : 0x%x\n",
 185                 MCBSP_READ(mcbsp_dma_rx, SPCR2));
 186
 187         /* We can free the channels */
 188         omap_free_dma(mcbsp_dma_rx->dma_rx_lch);
 189         mcbsp_dma_rx->dma_rx_lch = -1;
 190
 191         complete(&mcbsp_dma_rx->rx_dma_completion);
 192 }
 193
 194 /*
 195  * omap_mcbsp_config simply write a config to the
 196  * appropriate McBSP.
 197  * You either call this function or set the McBSP registers
 198  * by yourself before calling omap_mcbsp_start().
 199  */
 200 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
 201 {
 202         struct omap_mcbsp *mcbsp;
 203
 204         if (!omap_mcbsp_check_valid_id(id)) {
 205                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 206                 return;
 207         }
 208         mcbsp = id_to_mcbsp_ptr(id);
 209
 210         dev_dbg(mcbsp->dev, "Configuring McBSP%d  phys_base: 0x%08lx\n",
 211                         mcbsp->id, mcbsp->phys_base);
 212
 213         /* We write the given config */
 214         MCBSP_WRITE(mcbsp, SPCR2, config->spcr2);
 215         MCBSP_WRITE(mcbsp, SPCR1, config->spcr1);
 216         MCBSP_WRITE(mcbsp, RCR2, config->rcr2);
 217         MCBSP_WRITE(mcbsp, RCR1, config->rcr1);
 218         MCBSP_WRITE(mcbsp, XCR2, config->xcr2);
 219         MCBSP_WRITE(mcbsp, XCR1, config->xcr1);
 220         MCBSP_WRITE(mcbsp, SRGR2, config->srgr2);
 221         MCBSP_WRITE(mcbsp, SRGR1, config->srgr1);
 222         MCBSP_WRITE(mcbsp, MCR2, config->mcr2);
 223         MCBSP_WRITE(mcbsp, MCR1, config->mcr1);
 224         MCBSP_WRITE(mcbsp, PCR0, config->pcr0);
 225         if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
 226                 MCBSP_WRITE(mcbsp, XCCR, config->xccr);
 227                 MCBSP_WRITE(mcbsp, RCCR, config->rccr);
 228         }
 229 }
 230 EXPORT_SYMBOL(omap_mcbsp_config);
 231
 232 #ifdef CONFIG_ARCH_OMAP3
 233 static void omap_st_on(struct omap_mcbsp *mcbsp)
 234 {
 235         unsigned int w;
 236
 237         /*
 238          * Sidetone uses McBSP ICLK - which must not idle when sidetones
 239          * are enabled or sidetones start sounding ugly.
 240          */
 241         w = cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
 242         w &= ~(1 << (mcbsp->id - 2));
 243         cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
 244
 245         /* Enable McBSP Sidetone */
 246         w = MCBSP_READ(mcbsp, SSELCR);
 247         MCBSP_WRITE(mcbsp, SSELCR, w | SIDETONEEN);
 248
 249         w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
 250         MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w & ~(ST_AUTOIDLE));
 251
 252         /* Enable Sidetone from Sidetone Core */
 253         w = MCBSP_ST_READ(mcbsp, SSELCR);
 254         MCBSP_ST_WRITE(mcbsp, SSELCR, w | ST_SIDETONEEN);
 255 }
 256
 257 static void omap_st_off(struct omap_mcbsp *mcbsp)
 258 {
 259         unsigned int w;
 260
 261         w = MCBSP_ST_READ(mcbsp, SSELCR);
 262         MCBSP_ST_WRITE(mcbsp, SSELCR, w & ~(ST_SIDETONEEN));
 263
 264         w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
 265         MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w | ST_AUTOIDLE);
 266
 267         w = MCBSP_READ(mcbsp, SSELCR);
 268         MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN));
 269
 270         w = cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
 271         w |= 1 << (mcbsp->id - 2);
 272         cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
 273 }
 274
 275 static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir)
 276 {
 277         u16 val, i;
 278
 279         val = MCBSP_ST_READ(mcbsp, SYSCONFIG);
 280         MCBSP_ST_WRITE(mcbsp, SYSCONFIG, val & ~(ST_AUTOIDLE));
 281
 282         val = MCBSP_ST_READ(mcbsp, SSELCR);
 283
 284         if (val & ST_COEFFWREN)
 285                 MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
 286
 287         MCBSP_ST_WRITE(mcbsp, SSELCR, val | ST_COEFFWREN);
 288
 289         for (i = 0; i < 128; i++)
 290                 MCBSP_ST_WRITE(mcbsp, SFIRCR, fir[i]);
 291
 292         i = 0;
 293
 294         val = MCBSP_ST_READ(mcbsp, SSELCR);
 295         while (!(val & ST_COEFFWRDONE) && (++i < 1000))
 296                 val = MCBSP_ST_READ(mcbsp, SSELCR);
 297
 298         MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
 299
 300         if (i == 1000)
 301                 dev_err(mcbsp->dev, "McBSP FIR load error!\n");
 302 }
 303
 304 static void omap_st_chgain(struct omap_mcbsp *mcbsp)
 305 {
 306         u16 w;
 307         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 308
 309         w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
 310         MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w & ~(ST_AUTOIDLE));
 311
 312         w = MCBSP_ST_READ(mcbsp, SSELCR);
 313
 314         MCBSP_ST_WRITE(mcbsp, SGAINCR, ST_CH0GAIN(st_data->ch0gain) | \
 315                       ST_CH1GAIN(st_data->ch1gain));
 316 }
 317
 318 int omap_st_set_chgain(unsigned int id, int channel, s16 chgain)
 319 {
 320         struct omap_mcbsp *mcbsp;
 321         struct omap_mcbsp_st_data *st_data;
 322         int ret = 0;
 323
 324         if (!omap_mcbsp_check_valid_id(id)) {
 325                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 326                 return -ENODEV;
 327         }
 328
 329         mcbsp = id_to_mcbsp_ptr(id);
 330         st_data = mcbsp->st_data;
 331
 332         if (!st_data)
 333                 return -ENOENT;
 334
 335         spin_lock_irq(&mcbsp->lock);
 336         if (channel == 0)
 337                 st_data->ch0gain = chgain;
 338         else if (channel == 1)
 339                 st_data->ch1gain = chgain;
 340         else
 341                 ret = -EINVAL;
 342
 343         if (st_data->enabled)
 344                 omap_st_chgain(mcbsp);
 345         spin_unlock_irq(&mcbsp->lock);
 346
 347         return ret;
 348 }
 349 EXPORT_SYMBOL(omap_st_set_chgain);
 350
 351 int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain)
 352 {
 353         struct omap_mcbsp *mcbsp;
 354         struct omap_mcbsp_st_data *st_data;
 355         int ret = 0;
 356
 357         if (!omap_mcbsp_check_valid_id(id)) {
 358                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 359                 return -ENODEV;
 360         }
 361
 362         mcbsp = id_to_mcbsp_ptr(id);
 363         st_data = mcbsp->st_data;
 364
 365         if (!st_data)
 366                 return -ENOENT;
 367
 368         spin_lock_irq(&mcbsp->lock);
 369         if (channel == 0)
 370                 *chgain = st_data->ch0gain;
 371         else if (channel == 1)
 372                 *chgain = st_data->ch1gain;
 373         else
 374                 ret = -EINVAL;
 375         spin_unlock_irq(&mcbsp->lock);
 376
 377         return ret;
 378 }
 379 EXPORT_SYMBOL(omap_st_get_chgain);
 380
 381 static int omap_st_start(struct omap_mcbsp *mcbsp)
 382 {
 383         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 384
 385         if (st_data && st_data->enabled && !st_data->running) {
 386                 omap_st_fir_write(mcbsp, st_data->taps);
 387                 omap_st_chgain(mcbsp);
 388
 389                 if (!mcbsp->free) {
 390                         omap_st_on(mcbsp);
 391                         st_data->running = 1;
 392                 }
 393         }
 394
 395         return 0;
 396 }
 397
 398 int omap_st_enable(unsigned int id)
 399 {
 400         struct omap_mcbsp *mcbsp;
 401         struct omap_mcbsp_st_data *st_data;
 402
 403         if (!omap_mcbsp_check_valid_id(id)) {
 404                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 405                 return -ENODEV;
 406         }
 407
 408         mcbsp = id_to_mcbsp_ptr(id);
 409         st_data = mcbsp->st_data;
 410
 411         if (!st_data)
 412                 return -ENODEV;
 413
 414         spin_lock_irq(&mcbsp->lock);
 415         st_data->enabled = 1;
 416         omap_st_start(mcbsp);
 417         spin_unlock_irq(&mcbsp->lock);
 418
 419         return 0;
 420 }
 421 EXPORT_SYMBOL(omap_st_enable);
 422
 423 static int omap_st_stop(struct omap_mcbsp *mcbsp)
 424 {
 425         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 426
 427         if (st_data && st_data->running) {
 428                 if (!mcbsp->free) {
 429                         omap_st_off(mcbsp);
 430                         st_data->running = 0;
 431                 }
 432         }
 433
 434         return 0;
 435 }
 436
 437 int omap_st_disable(unsigned int id)
 438 {
 439         struct omap_mcbsp *mcbsp;
 440         struct omap_mcbsp_st_data *st_data;
 441         int ret = 0;
 442
 443         if (!omap_mcbsp_check_valid_id(id)) {
 444                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 445                 return -ENODEV;
 446         }
 447
 448         mcbsp = id_to_mcbsp_ptr(id);
 449         st_data = mcbsp->st_data;
 450
 451         if (!st_data)
 452                 return -ENODEV;
 453
 454         spin_lock_irq(&mcbsp->lock);
 455         omap_st_stop(mcbsp);
 456         st_data->enabled = 0;
 457         spin_unlock_irq(&mcbsp->lock);
 458
 459         return ret;
 460 }
 461 EXPORT_SYMBOL(omap_st_disable);
 462
 463 int omap_st_is_enabled(unsigned int id)
 464 {
 465         struct omap_mcbsp *mcbsp;
 466         struct omap_mcbsp_st_data *st_data;
 467
 468         if (!omap_mcbsp_check_valid_id(id)) {
 469                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 470                 return -ENODEV;
 471         }
 472
 473         mcbsp = id_to_mcbsp_ptr(id);
 474         st_data = mcbsp->st_data;
 475
 476         if (!st_data)
 477                 return -ENODEV;
 478
 479
 480         return st_data->enabled;
 481 }
 482 EXPORT_SYMBOL(omap_st_is_enabled);
 483
 484 /*
 485  * omap_mcbsp_set_tx_threshold configures how to deal
 486  * with transmit threshold. the threshold value and handler can be
 487  * configure in here.
 488  */
 489 void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
 490 {
 491         struct omap_mcbsp *mcbsp;
 492
 493         if (!cpu_is_omap34xx())
 494                 return;
 495
 496         if (!omap_mcbsp_check_valid_id(id)) {
 497                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 498                 return;
 499         }
 500         mcbsp = id_to_mcbsp_ptr(id);
 501
 502         MCBSP_WRITE(mcbsp, THRSH2, threshold);
 503 }
 504 EXPORT_SYMBOL(omap_mcbsp_set_tx_threshold);
 505
 506 /*
 507  * omap_mcbsp_set_rx_threshold configures how to deal
 508  * with receive threshold. the threshold value and handler can be
 509  * configure in here.
 510  */
 511 void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
 512 {
 513         struct omap_mcbsp *mcbsp;
 514
 515         if (!cpu_is_omap34xx())
 516                 return;
 517
 518         if (!omap_mcbsp_check_valid_id(id)) {
 519                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 520                 return;
 521         }
 522         mcbsp = id_to_mcbsp_ptr(id);
 523
 524         MCBSP_WRITE(mcbsp, THRSH1, threshold);
 525 }
 526 EXPORT_SYMBOL(omap_mcbsp_set_rx_threshold);
 527
 528 /*
 529  * omap_mcbsp_get_max_tx_thres just return the current configured
 530  * maximum threshold for transmission
 531  */
 532 u16 omap_mcbsp_get_max_tx_threshold(unsigned int id)
 533 {
 534         struct omap_mcbsp *mcbsp;
 535
 536         if (!omap_mcbsp_check_valid_id(id)) {
 537                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 538                 return -ENODEV;
 539         }
 540         mcbsp = id_to_mcbsp_ptr(id);
 541
 542         return mcbsp->max_tx_thres;
 543 }
 544 EXPORT_SYMBOL(omap_mcbsp_get_max_tx_threshold);
 545
 546 /*
 547  * omap_mcbsp_get_max_rx_thres just return the current configured
 548  * maximum threshold for reception
 549  */
 550 u16 omap_mcbsp_get_max_rx_threshold(unsigned int id)
 551 {
 552         struct omap_mcbsp *mcbsp;
 553
 554         if (!omap_mcbsp_check_valid_id(id)) {
 555                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 556                 return -ENODEV;
 557         }
 558         mcbsp = id_to_mcbsp_ptr(id);
 559
 560         return mcbsp->max_rx_thres;
 561 }
 562 EXPORT_SYMBOL(omap_mcbsp_get_max_rx_threshold);
 563
 564 /*
 565  * omap_mcbsp_get_dma_op_mode just return the current configured
 566  * operating mode for the mcbsp channel
 567  */
 568 int omap_mcbsp_get_dma_op_mode(unsigned int id)
 569 {
 570         struct omap_mcbsp *mcbsp;
 571         int dma_op_mode;
 572
 573         if (!omap_mcbsp_check_valid_id(id)) {
 574                 printk(KERN_ERR "%s: Invalid id (%u)\n", __func__, id + 1);
 575                 return -ENODEV;
 576         }
 577         mcbsp = id_to_mcbsp_ptr(id);
 578
 579         dma_op_mode = mcbsp->dma_op_mode;
 580
 581         return dma_op_mode;
 582 }
 583 EXPORT_SYMBOL(omap_mcbsp_get_dma_op_mode);
 584
 585 static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp)
 586 {
 587         /*
 588          * Enable wakup behavior, smart idle and all wakeups
 589          * REVISIT: some wakeups may be unnecessary
 590          */
 591         if (cpu_is_omap34xx()) {
 592                 u16 syscon;
 593
 594                 syscon = MCBSP_READ(mcbsp, SYSCON);
 595                 syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
 596
 597                 if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) {
 598                         syscon |= (ENAWAKEUP | SIDLEMODE(0x02) |
 599                                         CLOCKACTIVITY(0x02));
 600                         MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
 601                 } else {
 602                         syscon |= SIDLEMODE(0x01);
 603                 }
 604
 605                 MCBSP_WRITE(mcbsp, SYSCON, syscon);
 606         }
 607 }
 608
 609 static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp)
 610 {
 611         /*
 612          * Disable wakup behavior, smart idle and all wakeups
 613          */
 614         if (cpu_is_omap34xx()) {
 615                 u16 syscon;
 616
 617                 syscon = MCBSP_READ(mcbsp, SYSCON);
 618                 syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
 619                 /*
 620                  * HW bug workaround - If no_idle mode is taken, we need to
 621                  * go to smart_idle before going to always_idle, or the
 622                  * device will not hit retention anymore.
 623                  */
 624                 syscon |= SIDLEMODE(0x02);
 625                 MCBSP_WRITE(mcbsp, SYSCON, syscon);
 626
 627                 syscon &= ~(SIDLEMODE(0x03));
 628                 MCBSP_WRITE(mcbsp, SYSCON, syscon);
 629
 630                 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
 631         }
 632 }
 633 #else
 634 static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp) {}
 635 static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp) {}
 636 static inline void omap_st_start(struct omap_mcbsp *mcbsp) {}
 637 static inline void omap_st_stop(struct omap_mcbsp *mcbsp) {}
 638 #endif
 639
 640 /*
 641  * We can choose between IRQ based or polled IO.
 642  * This needs to be called before omap_mcbsp_request().
 643  */
 644 int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type)
 645 {
 646         struct omap_mcbsp *mcbsp;
 647
 648         if (!omap_mcbsp_check_valid_id(id)) {
 649                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 650                 return -ENODEV;
 651         }
 652         mcbsp = id_to_mcbsp_ptr(id);
 653
 654         spin_lock(&mcbsp->lock);
 655
 656         if (!mcbsp->free) {
 657                 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
 658                         mcbsp->id);
 659                 spin_unlock(&mcbsp->lock);
 660                 return -EINVAL;
 661         }
 662
 663         mcbsp->io_type = io_type;
 664
 665         spin_unlock(&mcbsp->lock);
 666
 667         return 0;
 668 }
 669 EXPORT_SYMBOL(omap_mcbsp_set_io_type);
 670
 671 int omap_mcbsp_request(unsigned int id)
 672 {
 673         struct omap_mcbsp *mcbsp;
 674         void *reg_cache;
 675         int err;
 676
 677         if (!omap_mcbsp_check_valid_id(id)) {
 678                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 679                 return -ENODEV;
 680         }
 681         mcbsp = id_to_mcbsp_ptr(id);
 682
 683         reg_cache = kzalloc(omap_mcbsp_cache_size, GFP_KERNEL);
 684         if (!reg_cache) {
 685                 return -ENOMEM;
 686         }
 687
 688         spin_lock(&mcbsp->lock);
 689         if (!mcbsp->free) {
 690                 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
 691                         mcbsp->id);
 692                 err = -EBUSY;
 693                 goto err_kfree;
 694         }
 695
 696         mcbsp->free = 0;
 697         mcbsp->reg_cache = reg_cache;
 698         spin_unlock(&mcbsp->lock);
 699
 700         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
 701                 mcbsp->pdata->ops->request(id);
 702
 703         clk_enable(mcbsp->iclk);
 704         clk_enable(mcbsp->fclk);
 705
 706         /* Do procedure specific to omap34xx arch, if applicable */
 707         omap34xx_mcbsp_request(mcbsp);
 708
 709         /*
 710          * Make sure that transmitter, receiver and sample-rate generator are
 711          * not running before activating IRQs.
 712          */
 713         MCBSP_WRITE(mcbsp, SPCR1, 0);
 714         MCBSP_WRITE(mcbsp, SPCR2, 0);
 715
 716         if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
 717                 /* We need to get IRQs here */
 718                 init_completion(&mcbsp->tx_irq_completion);
 719                 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler,
 720                                         0, "McBSP", (void *)mcbsp);
 721                 if (err != 0) {
 722                         dev_err(mcbsp->dev, "Unable to request TX IRQ %d "
 723                                         "for McBSP%d\n", mcbsp->tx_irq,
 724                                         mcbsp->id);
 725                         goto err_clk_disable;
 726                 }
 727
 728                 init_completion(&mcbsp->rx_irq_completion);
 729                 err = request_irq(mcbsp->rx_irq, omap_mcbsp_rx_irq_handler,
 730                                         0, "McBSP", (void *)mcbsp);
 731                 if (err != 0) {
 732                         dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
 733                                         "for McBSP%d\n", mcbsp->rx_irq,
 734                                         mcbsp->id);
 735                         goto err_free_irq;
 736                 }
 737         }
 738
 739         return 0;
 740 err_free_irq:
 741         free_irq(mcbsp->tx_irq, (void *)mcbsp);
 742 err_clk_disable:
 743         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
 744                 mcbsp->pdata->ops->free(id);
 745
 746         /* Do procedure specific to omap34xx arch, if applicable */
 747         omap34xx_mcbsp_free(mcbsp);
 748
 749         clk_disable(mcbsp->fclk);
 750         clk_disable(mcbsp->iclk);
 751
 752         spin_lock(&mcbsp->lock);
 753         mcbsp->free = 1;
 754         mcbsp->reg_cache = NULL;
 755 err_kfree:
 756         spin_unlock(&mcbsp->lock);
 757         kfree(reg_cache);
 758
 759         return err;
 760 }
 761 EXPORT_SYMBOL(omap_mcbsp_request);
 762
 763 void omap_mcbsp_free(unsigned int id)
 764 {
 765         struct omap_mcbsp *mcbsp;
 766         void *reg_cache;
 767
 768         if (!omap_mcbsp_check_valid_id(id)) {
 769                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 770                 return;
 771         }
 772         mcbsp = id_to_mcbsp_ptr(id);
 773
 774         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
 775                 mcbsp->pdata->ops->free(id);
 776
 777         /* Do procedure specific to omap34xx arch, if applicable */
 778         omap34xx_mcbsp_free(mcbsp);
 779
 780         clk_disable(mcbsp->fclk);
 781         clk_disable(mcbsp->iclk);
 782
 783         if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
 784                 /* Free IRQs */
 785                 free_irq(mcbsp->rx_irq, (void *)mcbsp);
 786                 free_irq(mcbsp->tx_irq, (void *)mcbsp);
 787         }
 788
 789         reg_cache = mcbsp->reg_cache;
 790
 791         spin_lock(&mcbsp->lock);
 792         if (mcbsp->free)
 793                 dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id);
 794         else
 795                 mcbsp->free = 1;
 796         mcbsp->reg_cache = NULL;
 797         spin_unlock(&mcbsp->lock);
 798
 799         if (reg_cache)
 800                 kfree(reg_cache);
 801 }
 802 EXPORT_SYMBOL(omap_mcbsp_free);
 803
 804 /*
 805  * Here we start the McBSP, by enabling transmitter, receiver or both.
 806  * If no transmitter or receiver is active prior calling, then sample-rate
 807  * generator and frame sync are started.
 808  */
 809 void omap_mcbsp_start(unsigned int id, int tx, int rx)
 810 {
 811         struct omap_mcbsp *mcbsp;
 812         int idle;
 813         u16 w;
 814
 815         if (!omap_mcbsp_check_valid_id(id)) {
 816                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 817                 return;
 818         }
 819         mcbsp = id_to_mcbsp_ptr(id);
 820
 821         if (cpu_is_omap34xx())
 822                 omap_st_start(mcbsp);
 823
 824         mcbsp->rx_word_length = (MCBSP_READ_CACHE(mcbsp, RCR1) >> 5) & 0x7;
 825         mcbsp->tx_word_length = (MCBSP_READ_CACHE(mcbsp, XCR1) >> 5) & 0x7;
 826
 827         idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
 828                         MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
 829
 830         if (idle) {
 831                 /* Start the sample generator */
 832                 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 833                 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6));
 834         }
 835
 836         /* Enable transmitter and receiver */
 837         tx &= 1;
 838         w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 839         MCBSP_WRITE(mcbsp, SPCR2, w | tx);
 840
 841         rx &= 1;
 842         w = MCBSP_READ_CACHE(mcbsp, SPCR1);
 843         MCBSP_WRITE(mcbsp, SPCR1, w | rx);
 844
 845         /*
 846          * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
 847          * REVISIT: 100us may give enough time for two CLKSRG, however
 848          * due to some unknown PM related, clock gating etc. reason it
 849          * is now at 500us.
 850          */
 851         udelay(500);
 852
 853         if (idle) {
 854                 /* Start frame sync */
 855                 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 856                 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
 857         }
 858
 859         if (cpu_is_omap2430() || cpu_is_omap34xx()) {
 860                 /* Release the transmitter and receiver */
 861                 w = MCBSP_READ_CACHE(mcbsp, XCCR);
 862                 w &= ~(tx ? XDISABLE : 0);
 863                 MCBSP_WRITE(mcbsp, XCCR, w);
 864                 w = MCBSP_READ_CACHE(mcbsp, RCCR);
 865                 w &= ~(rx ? RDISABLE : 0);
 866                 MCBSP_WRITE(mcbsp, RCCR, w);
 867         }
 868
 869         /* Dump McBSP Regs */
 870         omap_mcbsp_dump_reg(id);
 871 }
 872 EXPORT_SYMBOL(omap_mcbsp_start);
 873
 874 void omap_mcbsp_stop(unsigned int id, int tx, int rx)
 875 {
 876         struct omap_mcbsp *mcbsp;
 877         int idle;
 878         u16 w;
 879
 880         if (!omap_mcbsp_check_valid_id(id)) {
 881                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 882                 return;
 883         }
 884
 885         mcbsp = id_to_mcbsp_ptr(id);
 886
 887         /* Reset transmitter */
 888         tx &= 1;
 889         if (cpu_is_omap2430() || cpu_is_omap34xx()) {
 890                 w = MCBSP_READ_CACHE(mcbsp, XCCR);
 891                 w |= (tx ? XDISABLE : 0);
 892                 MCBSP_WRITE(mcbsp, XCCR, w);
 893         }
 894         w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 895         MCBSP_WRITE(mcbsp, SPCR2, w & ~tx);
 896
 897         /* Reset receiver */
 898         rx &= 1;
 899         if (cpu_is_omap2430() || cpu_is_omap34xx()) {
 900                 w = MCBSP_READ_CACHE(mcbsp, RCCR);
 901                 w |= (rx ? RDISABLE : 0);
 902                 MCBSP_WRITE(mcbsp, RCCR, w);
 903         }
 904         w = MCBSP_READ_CACHE(mcbsp, SPCR1);
 905         MCBSP_WRITE(mcbsp, SPCR1, w & ~rx);
 906
 907         idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
 908                         MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
 909
 910         if (idle) {
 911                 /* Reset the sample rate generator */
 912                 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 913                 MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6));
 914         }
 915
 916         if (cpu_is_omap34xx())
 917                 omap_st_stop(mcbsp);
 918 }
 919 EXPORT_SYMBOL(omap_mcbsp_stop);
 920
 921 /* polled mcbsp i/o operations */
 922 int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
 923 {
 924         struct omap_mcbsp *mcbsp;
 925
 926         if (!omap_mcbsp_check_valid_id(id)) {
 927                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 928                 return -ENODEV;
 929         }
 930
 931         mcbsp = id_to_mcbsp_ptr(id);
 932
 933         MCBSP_WRITE(mcbsp, DXR1, buf);
 934         /* if frame sync error - clear the error */
 935         if (MCBSP_READ(mcbsp, SPCR2) & XSYNC_ERR) {
 936                 /* clear error */
 937                 MCBSP_WRITE(mcbsp, SPCR2,
 938                                 MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XSYNC_ERR));
 939                 /* resend */
 940                 return -1;
 941         } else {
 942                 /* wait for transmit confirmation */
 943                 int attemps = 0;
 944                 while (!(MCBSP_READ(mcbsp, SPCR2) & XRDY)) {
 945                         if (attemps++ > 1000) {
 946                                 MCBSP_WRITE(mcbsp, SPCR2,
 947                                                 MCBSP_READ_CACHE(mcbsp, SPCR2) &
 948                                                 (~XRST));
 949                                 udelay(10);
 950                                 MCBSP_WRITE(mcbsp, SPCR2,
 951                                                 MCBSP_READ_CACHE(mcbsp, SPCR2) |
 952                                                 (XRST));
 953                                 udelay(10);
 954                                 dev_err(mcbsp->dev, "Could not write to"
 955                                         " McBSP%d Register\n", mcbsp->id);
 956                                 return -2;
 957                         }
 958                 }
 959         }
 960
 961         return 0;
 962 }
 963 EXPORT_SYMBOL(omap_mcbsp_pollwrite);
 964
 965 int omap_mcbsp_pollread(unsigned int id, u16 *buf)
 966 {
 967         struct omap_mcbsp *mcbsp;
 968
 969         if (!omap_mcbsp_check_valid_id(id)) {
 970                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 971                 return -ENODEV;
 972         }
 973         mcbsp = id_to_mcbsp_ptr(id);
 974
 975         /* if frame sync error - clear the error */
 976         if (MCBSP_READ(mcbsp, SPCR1) & RSYNC_ERR) {
 977                 /* clear error */
 978                 MCBSP_WRITE(mcbsp, SPCR1,
 979                                 MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RSYNC_ERR));
 980                 /* resend */
 981                 return -1;
 982         } else {
 983                 /* wait for recieve confirmation */
 984                 int attemps = 0;
 985                 while (!(MCBSP_READ(mcbsp, SPCR1) & RRDY)) {
 986                         if (attemps++ > 1000) {
 987                                 MCBSP_WRITE(mcbsp, SPCR1,
 988                                                 MCBSP_READ_CACHE(mcbsp, SPCR1) &
 989                                                 (~RRST));
 990                                 udelay(10);
 991                                 MCBSP_WRITE(mcbsp, SPCR1,
 992                                                 MCBSP_READ_CACHE(mcbsp, SPCR1) |
 993                                                 (RRST));
 994                                 udelay(10);
 995                                 dev_err(mcbsp->dev, "Could not read from"
 996                                         " McBSP%d Register\n", mcbsp->id);
 997                                 return -2;
 998                         }
 999                 }
1000         }
1001         *buf = MCBSP_READ(mcbsp, DRR1);
1002
1003         return 0;
1004 }
1005 EXPORT_SYMBOL(omap_mcbsp_pollread);
1006
1007 /*
1008  * IRQ based word transmission.
1009  */
1010 void omap_mcbsp_xmit_word(unsigned int id, u32 word)
1011 {
1012         struct omap_mcbsp *mcbsp;
1013         omap_mcbsp_word_length word_length;
1014
1015         if (!omap_mcbsp_check_valid_id(id)) {
1016                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1017                 return;
1018         }
1019
1020         mcbsp = id_to_mcbsp_ptr(id);
1021         word_length = mcbsp->tx_word_length;
1022
1023         wait_for_completion(&mcbsp->tx_irq_completion);
1024
1025         if (word_length > OMAP_MCBSP_WORD_16)
1026                 MCBSP_WRITE(mcbsp, DXR2, word >> 16);
1027         MCBSP_WRITE(mcbsp, DXR1, word & 0xffff);
1028 }
1029 EXPORT_SYMBOL(omap_mcbsp_xmit_word);
1030
1031 u32 omap_mcbsp_recv_word(unsigned int id)
1032 {
1033         struct omap_mcbsp *mcbsp;
1034         u16 word_lsb, word_msb = 0;
1035         omap_mcbsp_word_length word_length;
1036
1037         if (!omap_mcbsp_check_valid_id(id)) {
1038                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1039                 return -ENODEV;
1040         }
1041         mcbsp = id_to_mcbsp_ptr(id);
1042
1043         word_length = mcbsp->rx_word_length;
1044
1045         wait_for_completion(&mcbsp->rx_irq_completion);
1046
1047         if (word_length > OMAP_MCBSP_WORD_16)
1048                 word_msb = MCBSP_READ(mcbsp, DRR2);
1049         word_lsb = MCBSP_READ(mcbsp, DRR1);
1050
1051         return (word_lsb | (word_msb << 16));
1052 }
1053 EXPORT_SYMBOL(omap_mcbsp_recv_word);
1054
1055 int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
1056 {
1057         struct omap_mcbsp *mcbsp;
1058         omap_mcbsp_word_length tx_word_length;
1059         omap_mcbsp_word_length rx_word_length;
1060         u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
1061
1062         if (!omap_mcbsp_check_valid_id(id)) {
1063                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1064                 return -ENODEV;
1065         }
1066         mcbsp = id_to_mcbsp_ptr(id);
1067         tx_word_length = mcbsp->tx_word_length;
1068         rx_word_length = mcbsp->rx_word_length;
1069
1070         if (tx_word_length != rx_word_length)
1071                 return -EINVAL;
1072
1073         /* First we wait for the transmitter to be ready */
1074         spcr2 = MCBSP_READ(mcbsp, SPCR2);
1075         while (!(spcr2 & XRDY)) {
1076                 spcr2 = MCBSP_READ(mcbsp, SPCR2);
1077                 if (attempts++ > 1000) {
1078                         /* We must reset the transmitter */
1079                         MCBSP_WRITE(mcbsp, SPCR2,
1080                                     MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XRST));
1081                         udelay(10);
1082                         MCBSP_WRITE(mcbsp, SPCR2,
1083                                     MCBSP_READ_CACHE(mcbsp, SPCR2) | XRST);
1084                         udelay(10);
1085                         dev_err(mcbsp->dev, "McBSP%d transmitter not "
1086                                 "ready\n", mcbsp->id);
1087                         return -EAGAIN;
1088                 }
1089         }
1090
1091         /* Now we can push the data */
1092         if (tx_word_length > OMAP_MCBSP_WORD_16)
1093                 MCBSP_WRITE(mcbsp, DXR2, word >> 16);
1094         MCBSP_WRITE(mcbsp, DXR1, word & 0xffff);
1095
1096         /* We wait for the receiver to be ready */
1097         spcr1 = MCBSP_READ(mcbsp, SPCR1);
1098         while (!(spcr1 & RRDY)) {
1099                 spcr1 = MCBSP_READ(mcbsp, SPCR1);
1100                 if (attempts++ > 1000) {
1101                         /* We must reset the receiver */
1102                         MCBSP_WRITE(mcbsp, SPCR1,
1103                                     MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RRST));
1104                         udelay(10);
1105                         MCBSP_WRITE(mcbsp, SPCR1,
1106                                     MCBSP_READ_CACHE(mcbsp, SPCR1) | RRST);
1107                         udelay(10);
1108                         dev_err(mcbsp->dev, "McBSP%d receiver not "
1109                                 "ready\n", mcbsp->id);
1110                         return -EAGAIN;
1111                 }
1112         }
1113
1114         /* Receiver is ready, let's read the dummy data */
1115         if (rx_word_length > OMAP_MCBSP_WORD_16)
1116                 word_msb = MCBSP_READ(mcbsp, DRR2);
1117         word_lsb = MCBSP_READ(mcbsp, DRR1);
1118
1119         return 0;
1120 }
1121 EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll);
1122
1123 int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
1124 {
1125         struct omap_mcbsp *mcbsp;
1126         u32 clock_word = 0;
1127         omap_mcbsp_word_length tx_word_length;
1128         omap_mcbsp_word_length rx_word_length;
1129         u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
1130
1131         if (!omap_mcbsp_check_valid_id(id)) {
1132                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1133                 return -ENODEV;
1134         }
1135
1136         mcbsp = id_to_mcbsp_ptr(id);
1137
1138         tx_word_length = mcbsp->tx_word_length;
1139         rx_word_length = mcbsp->rx_word_length;
1140
1141         if (tx_word_length != rx_word_length)
1142                 return -EINVAL;
1143
1144         /* First we wait for the transmitter to be ready */
1145         spcr2 = MCBSP_READ(mcbsp, SPCR2);
1146         while (!(spcr2 & XRDY)) {
1147                 spcr2 = MCBSP_READ(mcbsp, SPCR2);
1148                 if (attempts++ > 1000) {
1149                         /* We must reset the transmitter */
1150                         MCBSP_WRITE(mcbsp, SPCR2,
1151                                     MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XRST));
1152                         udelay(10);
1153                         MCBSP_WRITE(mcbsp, SPCR2,
1154                                     MCBSP_READ_CACHE(mcbsp, SPCR2) | XRST);
1155                         udelay(10);
1156                         dev_err(mcbsp->dev, "McBSP%d transmitter not "
1157                                 "ready\n", mcbsp->id);
1158                         return -EAGAIN;
1159                 }
1160         }
1161
1162         /* We first need to enable the bus clock */
1163         if (tx_word_length > OMAP_MCBSP_WORD_16)
1164                 MCBSP_WRITE(mcbsp, DXR2, clock_word >> 16);
1165         MCBSP_WRITE(mcbsp, DXR1, clock_word & 0xffff);
1166
1167         /* We wait for the receiver to be ready */
1168         spcr1 = MCBSP_READ(mcbsp, SPCR1);
1169         while (!(spcr1 & RRDY)) {
1170                 spcr1 = MCBSP_READ(mcbsp, SPCR1);
1171                 if (attempts++ > 1000) {
1172                         /* We must reset the receiver */
1173                         MCBSP_WRITE(mcbsp, SPCR1,
1174                                     MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RRST));
1175                         udelay(10);
1176                         MCBSP_WRITE(mcbsp, SPCR1,
1177                                     MCBSP_READ_CACHE(mcbsp, SPCR1) | RRST);
1178                         udelay(10);
1179                         dev_err(mcbsp->dev, "McBSP%d receiver not "
1180                                 "ready\n", mcbsp->id);
1181                         return -EAGAIN;
1182                 }
1183         }
1184
1185         /* Receiver is ready, there is something for us */
1186         if (rx_word_length > OMAP_MCBSP_WORD_16)
1187                 word_msb = MCBSP_READ(mcbsp, DRR2);
1188         word_lsb = MCBSP_READ(mcbsp, DRR1);
1189
1190         word[0] = (word_lsb | (word_msb << 16));
1191
1192         return 0;
1193 }
1194 EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll);
1195
1196 /*
1197  * Simple DMA based buffer rx/tx routines.
1198  * Nothing fancy, just a single buffer tx/rx through DMA.
1199  * The DMA resources are released once the transfer is done.
1200  * For anything fancier, you should use your own customized DMA
1201  * routines and callbacks.
1202  */
1203 int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer,
1204                                 unsigned int length)
1205 {
1206         struct omap_mcbsp *mcbsp;
1207         int dma_tx_ch;
1208         int src_port = 0;
1209         int dest_port = 0;
1210         int sync_dev = 0;
1211
1212         if (!omap_mcbsp_check_valid_id(id)) {
1213                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1214                 return -ENODEV;
1215         }
1216         mcbsp = id_to_mcbsp_ptr(id);
1217
1218         if (omap_request_dma(mcbsp->dma_tx_sync, "McBSP TX",
1219                                 omap_mcbsp_tx_dma_callback,
1220                                 mcbsp,
1221                                 &dma_tx_ch)) {
1222                 dev_err(mcbsp->dev, " Unable to request DMA channel for "
1223                                 "McBSP%d TX. Trying IRQ based TX\n",
1224                                 mcbsp->id);
1225                 return -EAGAIN;
1226         }
1227         mcbsp->dma_tx_lch = dma_tx_ch;
1228
1229         dev_err(mcbsp->dev, "McBSP%d TX DMA on channel %d\n", mcbsp->id,
1230                 dma_tx_ch);
1231
1232         init_completion(&mcbsp->tx_dma_completion);
1233
1234         if (cpu_class_is_omap1()) {
1235                 src_port = OMAP_DMA_PORT_TIPB;
1236                 dest_port = OMAP_DMA_PORT_EMIFF;
1237         }
1238         if (cpu_class_is_omap2())
1239                 sync_dev = mcbsp->dma_tx_sync;
1240
1241         omap_set_dma_transfer_params(mcbsp->dma_tx_lch,
1242                                      OMAP_DMA_DATA_TYPE_S16,
1243                                      length >> 1, 1,
1244                                      OMAP_DMA_SYNC_ELEMENT,
1245          sync_dev, 0);
1246
1247         omap_set_dma_dest_params(mcbsp->dma_tx_lch,
1248                                  src_port,
1249                                  OMAP_DMA_AMODE_CONSTANT,
1250                                  mcbsp->phys_base + OMAP_MCBSP_REG_DXR1,
1251                                  0, 0);
1252
1253         omap_set_dma_src_params(mcbsp->dma_tx_lch,
1254                                 dest_port,
1255                                 OMAP_DMA_AMODE_POST_INC,
1256                                 buffer,
1257                                 0, 0);
1258
1259         omap_start_dma(mcbsp->dma_tx_lch);
1260         wait_for_completion(&mcbsp->tx_dma_completion);
1261
1262         return 0;
1263 }
1264 EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
1265
1266 int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer,
1267                                 unsigned int length)
1268 {
1269         struct omap_mcbsp *mcbsp;
1270         int dma_rx_ch;
1271         int src_port = 0;
1272         int dest_port = 0;
1273         int sync_dev = 0;
1274
1275         if (!omap_mcbsp_check_valid_id(id)) {
1276                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1277                 return -ENODEV;
1278         }
1279         mcbsp = id_to_mcbsp_ptr(id);
1280
1281         if (omap_request_dma(mcbsp->dma_rx_sync, "McBSP RX",
1282                                 omap_mcbsp_rx_dma_callback,
1283                                 mcbsp,
1284                                 &dma_rx_ch)) {
1285                 dev_err(mcbsp->dev, "Unable to request DMA channel for "
1286                                 "McBSP%d RX. Trying IRQ based RX\n",
1287                                 mcbsp->id);
1288                 return -EAGAIN;
1289         }
1290         mcbsp->dma_rx_lch = dma_rx_ch;
1291
1292         dev_err(mcbsp->dev, "McBSP%d RX DMA on channel %d\n", mcbsp->id,
1293                 dma_rx_ch);
1294
1295         init_completion(&mcbsp->rx_dma_completion);
1296
1297         if (cpu_class_is_omap1()) {
1298                 src_port = OMAP_DMA_PORT_TIPB;
1299                 dest_port = OMAP_DMA_PORT_EMIFF;
1300         }
1301         if (cpu_class_is_omap2())
1302                 sync_dev = mcbsp->dma_rx_sync;
1303
1304         omap_set_dma_transfer_params(mcbsp->dma_rx_lch,
1305                                         OMAP_DMA_DATA_TYPE_S16,
1306                                         length >> 1, 1,
1307                                         OMAP_DMA_SYNC_ELEMENT,
1308                                         sync_dev, 0);
1309
1310         omap_set_dma_src_params(mcbsp->dma_rx_lch,
1311                                 src_port,
1312                                 OMAP_DMA_AMODE_CONSTANT,
1313                                 mcbsp->phys_base + OMAP_MCBSP_REG_DRR1,
1314                                 0, 0);
1315
1316         omap_set_dma_dest_params(mcbsp->dma_rx_lch,
1317                                         dest_port,
1318                                         OMAP_DMA_AMODE_POST_INC,
1319                                         buffer,
1320                                         0, 0);
1321
1322         omap_start_dma(mcbsp->dma_rx_lch);
1323         wait_for_completion(&mcbsp->rx_dma_completion);
1324
1325         return 0;
1326 }
1327 EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
1328
1329 /*
1330  * SPI wrapper.
1331  * Since SPI setup is much simpler than the generic McBSP one,
1332  * this wrapper just need an omap_mcbsp_spi_cfg structure as an input.
1333  * Once this is done, you can call omap_mcbsp_start().
1334  */
1335 void omap_mcbsp_set_spi_mode(unsigned int id,
1336                                 const struct omap_mcbsp_spi_cfg *spi_cfg)
1337 {
1338         struct omap_mcbsp *mcbsp;
1339         struct omap_mcbsp_reg_cfg mcbsp_cfg;
1340
1341         if (!omap_mcbsp_check_valid_id(id)) {
1342                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1343                 return;
1344         }
1345         mcbsp = id_to_mcbsp_ptr(id);
1346
1347         memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg));
1348
1349         /* SPI has only one frame */
1350         mcbsp_cfg.rcr1 |= (RWDLEN1(spi_cfg->word_length) | RFRLEN1(0));
1351         mcbsp_cfg.xcr1 |= (XWDLEN1(spi_cfg->word_length) | XFRLEN1(0));
1352
1353         /* Clock stop mode */
1354         if (spi_cfg->clk_stp_mode == OMAP_MCBSP_CLK_STP_MODE_NO_DELAY)
1355                 mcbsp_cfg.spcr1 |= (1 << 12);
1356         else
1357                 mcbsp_cfg.spcr1 |= (3 << 11);
1358
1359         /* Set clock parities */
1360         if (spi_cfg->rx_clock_polarity == OMAP_MCBSP_CLK_RISING)
1361                 mcbsp_cfg.pcr0 |= CLKRP;
1362         else
1363                 mcbsp_cfg.pcr0 &= ~CLKRP;
1364
1365         if (spi_cfg->tx_clock_polarity == OMAP_MCBSP_CLK_RISING)
1366                 mcbsp_cfg.pcr0 &= ~CLKXP;
1367         else
1368                 mcbsp_cfg.pcr0 |= CLKXP;
1369
1370         /* Set SCLKME to 0 and CLKSM to 1 */
1371         mcbsp_cfg.pcr0 &= ~SCLKME;
1372         mcbsp_cfg.srgr2 |= CLKSM;
1373
1374         /* Set FSXP */
1375         if (spi_cfg->fsx_polarity == OMAP_MCBSP_FS_ACTIVE_HIGH)
1376                 mcbsp_cfg.pcr0 &= ~FSXP;
1377         else
1378                 mcbsp_cfg.pcr0 |= FSXP;
1379
1380         if (spi_cfg->spi_mode == OMAP_MCBSP_SPI_MASTER) {
1381                 mcbsp_cfg.pcr0 |= CLKXM;
1382                 mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div - 1);
1383                 mcbsp_cfg.pcr0 |= FSXM;
1384                 mcbsp_cfg.srgr2 &= ~FSGM;
1385                 mcbsp_cfg.xcr2 |= XDATDLY(1);
1386                 mcbsp_cfg.rcr2 |= RDATDLY(1);
1387         } else {
1388                 mcbsp_cfg.pcr0 &= ~CLKXM;
1389                 mcbsp_cfg.srgr1 |= CLKGDV(1);
1390                 mcbsp_cfg.pcr0 &= ~FSXM;
1391                 mcbsp_cfg.xcr2 &= ~XDATDLY(3);
1392                 mcbsp_cfg.rcr2 &= ~RDATDLY(3);
1393         }
1394
1395         mcbsp_cfg.xcr2 &= ~XPHASE;
1396         mcbsp_cfg.rcr2 &= ~RPHASE;
1397
1398         omap_mcbsp_config(id, &mcbsp_cfg);
1399 }
1400 EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);
1401
1402 #ifdef CONFIG_ARCH_OMAP3
1403 #define max_thres(m)                    (mcbsp->pdata->buffer_size)
1404 #define valid_threshold(m, val)         ((val) <= max_thres(m))
1405 #define THRESHOLD_PROP_BUILDER(prop)                                    \
1406 static ssize_t prop##_show(struct device *dev,                          \
1407                         struct device_attribute *attr, char *buf)       \
1408 {                                                                       \
1409         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);                \
1410                                                                         \
1411         return sprintf(buf, "%u\n", mcbsp->prop);                       \
1412 }                                                                       \
1413                                                                         \
1414 static ssize_t prop##_store(struct device *dev,                         \
1415                                 struct device_attribute *attr,          \
1416                                 const char *buf, size_t size)           \
1417 {                                                                       \
1418         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);                \
1419         unsigned long val;                                              \
1420         int status;                                                     \
1421                                                                         \
1422         status = strict_strtoul(buf, 0, &val);                          \
1423         if (status)                                                     \
1424                 return status;                                          \
1425                                                                         \
1426         if (!valid_threshold(mcbsp, val))                               \
1427                 return -EDOM;                                           \
1428                                                                         \
1429         mcbsp->prop = val;                                              \
1430         return size;                                                    \
1431 }                                                                       \
1432                                                                         \
1433 static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store);
1434
1435 THRESHOLD_PROP_BUILDER(max_tx_thres);
1436 THRESHOLD_PROP_BUILDER(max_rx_thres);
1437
1438 static const char *dma_op_modes[] = {
1439         "element", "threshold", "frame",
1440 };
1441
1442 static ssize_t dma_op_mode_show(struct device *dev,
1443                         struct device_attribute *attr, char *buf)
1444 {
1445         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1446         int dma_op_mode, i = 0;
1447         ssize_t len = 0;
1448         const char * const *s;
1449
1450         dma_op_mode = mcbsp->dma_op_mode;
1451
1452         for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) {
1453                 if (dma_op_mode == i)
1454                         len += sprintf(buf + len, "[%s] ", *s);
1455                 else
1456                         len += sprintf(buf + len, "%s ", *s);
1457         }
1458         len += sprintf(buf + len, "\n");
1459
1460         return len;
1461 }
1462
1463 static ssize_t dma_op_mode_store(struct device *dev,
1464                                 struct device_attribute *attr,
1465                                 const char *buf, size_t size)
1466 {
1467         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1468         const char * const *s;
1469         int i = 0;
1470
1471         for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++)
1472                 if (sysfs_streq(buf, *s))
1473                         break;
1474
1475         if (i == ARRAY_SIZE(dma_op_modes))
1476                 return -EINVAL;
1477
1478         spin_lock_irq(&mcbsp->lock);
1479         if (!mcbsp->free) {
1480                 size = -EBUSY;
1481                 goto unlock;
1482         }
1483         mcbsp->dma_op_mode = i;
1484
1485 unlock:
1486         spin_unlock_irq(&mcbsp->lock);
1487
1488         return size;
1489 }
1490
1491 static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store);
1492
1493 static ssize_t st_taps_show(struct device *dev,
1494                             struct device_attribute *attr, char *buf)
1495 {
1496         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1497         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1498         ssize_t status = 0;
1499         int i;
1500
1501         spin_lock_irq(&mcbsp->lock);
1502         for (i = 0; i < st_data->nr_taps; i++)
1503                 status += sprintf(&buf[status], (i ? ", %d" : "%d"),
1504                                   st_data->taps[i]);
1505         if (i)
1506                 status += sprintf(&buf[status], "\n");
1507         spin_unlock_irq(&mcbsp->lock);
1508
1509         return status;
1510 }
1511
1512 static ssize_t st_taps_store(struct device *dev,
1513                              struct device_attribute *attr,
1514                              const char *buf, size_t size)
1515 {
1516         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1517         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1518         int val, tmp, status, i = 0;
1519
1520         spin_lock_irq(&mcbsp->lock);
1521         memset(st_data->taps, 0, sizeof(st_data->taps));
1522         st_data->nr_taps = 0;
1523
1524         do {
1525                 status = sscanf(buf, "%d%n", &val, &tmp);
1526                 if (status < 0 || status == 0) {
1527                         size = -EINVAL;
1528                         goto out;
1529                 }
1530                 if (val < -32768 || val > 32767) {
1531                         size = -EINVAL;
1532                         goto out;
1533                 }
1534                 st_data->taps[i++] = val;
1535                 buf += tmp;
1536                 if (*buf != ',')
1537                         break;
1538                 buf++;
1539         } while (1);
1540
1541         st_data->nr_taps = i;
1542
1543 out:
1544         spin_unlock_irq(&mcbsp->lock);
1545
1546         return size;
1547 }
1548
1549 static DEVICE_ATTR(st_taps, 0644, st_taps_show, st_taps_store);
1550
1551 static const struct attribute *additional_attrs[] = {
1552         &dev_attr_max_tx_thres.attr,
1553         &dev_attr_max_rx_thres.attr,
1554         &dev_attr_dma_op_mode.attr,
1555         NULL,
1556 };
1557
1558 static const struct attribute_group additional_attr_group = {
1559         .attrs = (struct attribute **)additional_attrs,
1560 };
1561
1562 static inline int __devinit omap_additional_add(struct device *dev)
1563 {
1564         return sysfs_create_group(&dev->kobj, &additional_attr_group);
1565 }
1566
1567 static inline void __devexit omap_additional_remove(struct device *dev)
1568 {
1569         sysfs_remove_group(&dev->kobj, &additional_attr_group);
1570 }
1571
1572 static const struct attribute *sidetone_attrs[] = {
1573         &dev_attr_st_taps.attr,
1574         NULL,
1575 };
1576
1577 static const struct attribute_group sidetone_attr_group = {
1578         .attrs = (struct attribute **)sidetone_attrs,
1579 };
1580
1581 int __devinit omap_st_add(struct omap_mcbsp *mcbsp)
1582 {
1583         struct omap_mcbsp_platform_data *pdata = mcbsp->pdata;
1584         struct omap_mcbsp_st_data *st_data;
1585         int err;
1586
1587         st_data = kzalloc(sizeof(*mcbsp->st_data), GFP_KERNEL);
1588         if (!st_data) {
1589                 err = -ENOMEM;
1590                 goto err1;
1591         }
1592
1593         st_data->io_base_st = ioremap(pdata->phys_base_st, SZ_4K);
1594         if (!st_data->io_base_st) {
1595                 err = -ENOMEM;
1596                 goto err2;
1597         }
1598
1599         err = sysfs_create_group(&mcbsp->dev->kobj, &sidetone_attr_group);
1600         if (err)
1601                 goto err3;
1602
1603         mcbsp->st_data = st_data;
1604         return 0;
1605
1606 err3:
1607         iounmap(st_data->io_base_st);
1608 err2:
1609         kfree(st_data);
1610 err1:
1611         return err;
1612
1613 }
1614
1615 static void __devexit omap_st_remove(struct omap_mcbsp *mcbsp)
1616 {
1617         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1618
1619         if (st_data) {
1620                 sysfs_remove_group(&mcbsp->dev->kobj, &sidetone_attr_group);
1621                 iounmap(st_data->io_base_st);
1622                 kfree(st_data);
1623         }
1624 }
1625
1626 static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp)
1627 {
1628         mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
1629         if (cpu_is_omap34xx()) {
1630                 mcbsp->max_tx_thres = max_thres(mcbsp);
1631                 mcbsp->max_rx_thres = max_thres(mcbsp);
1632                 /*
1633                  * REVISIT: Set dmap_op_mode to THRESHOLD as default
1634                  * for mcbsp2 instances.
1635                  */
1636                 if (omap_additional_add(mcbsp->dev))
1637                         dev_warn(mcbsp->dev,
1638                                 "Unable to create additional controls\n");
1639
1640                 if (mcbsp->id == 2 || mcbsp->id == 3)
1641                         if (omap_st_add(mcbsp))
1642                                 dev_warn(mcbsp->dev,
1643                                  "Unable to create sidetone controls\n");
1644
1645         } else {
1646                 mcbsp->max_tx_thres = -EINVAL;
1647                 mcbsp->max_rx_thres = -EINVAL;
1648         }
1649 }
1650
1651 static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp)
1652 {
1653         if (cpu_is_omap34xx()) {
1654                 omap_additional_remove(mcbsp->dev);
1655
1656                 if (mcbsp->id == 2 || mcbsp->id == 3)
1657                         omap_st_remove(mcbsp);
1658         }
1659 }
1660 #else
1661 static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp) {}
1662 static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp) {}
1663 #endif /* CONFIG_ARCH_OMAP3 */
1664
1665 /*
1666  * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
1667  * 730 has only 2 McBSP, and both of them are MPU peripherals.
1668  */
1669 static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
1670 {
1671         struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data;
1672         struct omap_mcbsp *mcbsp;
1673         int id = pdev->id - 1;
1674         int ret = 0;
1675
1676         if (!pdata) {
1677                 dev_err(&pdev->dev, "McBSP device initialized without"
1678                                 "platform data\n");
1679                 ret = -EINVAL;
1680                 goto exit;
1681         }
1682
1683         dev_dbg(&pdev->dev, "Initializing OMAP McBSP (%d).\n", pdev->id);
1684
1685         if (id >= omap_mcbsp_count) {
1686                 dev_err(&pdev->dev, "Invalid McBSP device id (%d)\n", id);
1687                 ret = -EINVAL;
1688                 goto exit;
1689         }
1690
1691         mcbsp = kzalloc(sizeof(struct omap_mcbsp), GFP_KERNEL);
1692         if (!mcbsp) {
1693                 ret = -ENOMEM;
1694                 goto exit;
1695         }
1696
1697         spin_lock_init(&mcbsp->lock);
1698         mcbsp->id = id + 1;
1699         mcbsp->free = 1;
1700         mcbsp->dma_tx_lch = -1;
1701         mcbsp->dma_rx_lch = -1;
1702
1703         mcbsp->phys_base = pdata->phys_base;
1704         mcbsp->io_base = ioremap(pdata->phys_base, SZ_4K);
1705         if (!mcbsp->io_base) {
1706                 ret = -ENOMEM;
1707                 goto err_ioremap;
1708         }
1709
1710         /* Default I/O is IRQ based */
1711         mcbsp->io_type = OMAP_MCBSP_IRQ_IO;
1712         mcbsp->tx_irq = pdata->tx_irq;
1713         mcbsp->rx_irq = pdata->rx_irq;
1714         mcbsp->dma_rx_sync = pdata->dma_rx_sync;
1715         mcbsp->dma_tx_sync = pdata->dma_tx_sync;
1716
1717         mcbsp->iclk = clk_get(&pdev->dev, "ick");
1718         if (IS_ERR(mcbsp->iclk)) {
1719                 ret = PTR_ERR(mcbsp->iclk);
1720                 dev_err(&pdev->dev, "unable to get ick: %d\n", ret);
1721                 goto err_iclk;
1722         }
1723
1724         mcbsp->fclk = clk_get(&pdev->dev, "fck");
1725         if (IS_ERR(mcbsp->fclk)) {
1726                 ret = PTR_ERR(mcbsp->fclk);
1727                 dev_err(&pdev->dev, "unable to get fck: %d\n", ret);
1728                 goto err_fclk;
1729         }
1730
1731         mcbsp->pdata = pdata;
1732         mcbsp->dev = &pdev->dev;
1733         mcbsp_ptr[id] = mcbsp;
1734         platform_set_drvdata(pdev, mcbsp);
1735
1736         /* Initialize mcbsp properties for OMAP34XX if needed / applicable */
1737         omap34xx_device_init(mcbsp);
1738
1739         return 0;
1740
1741 err_fclk:
1742         clk_put(mcbsp->iclk);
1743 err_iclk:
1744         iounmap(mcbsp->io_base);
1745 err_ioremap:
1746         kfree(mcbsp);
1747 exit:
1748         return ret;
1749 }
1750
1751 static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
1752 {
1753         struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
1754
1755         platform_set_drvdata(pdev, NULL);
1756         if (mcbsp) {
1757
1758                 if (mcbsp->pdata && mcbsp->pdata->ops &&
1759                                 mcbsp->pdata->ops->free)
1760                         mcbsp->pdata->ops->free(mcbsp->id);
1761
1762                 omap34xx_device_exit(mcbsp);
1763
1764                 clk_disable(mcbsp->fclk);
1765                 clk_disable(mcbsp->iclk);
1766                 clk_put(mcbsp->fclk);
1767                 clk_put(mcbsp->iclk);
1768
1769                 iounmap(mcbsp->io_base);
1770
1771                 mcbsp->fclk = NULL;
1772                 mcbsp->iclk = NULL;
1773                 mcbsp->free = 0;
1774                 mcbsp->dev = NULL;
1775         }
1776
1777         return 0;
1778 }
1779
1780 static struct platform_driver omap_mcbsp_driver = {
1781         .probe          = omap_mcbsp_probe,
1782         .remove         = __devexit_p(omap_mcbsp_remove),
1783         .driver         = {
1784                 .name   = "omap-mcbsp",
1785         },
1786 };
1787
1788 int __init omap_mcbsp_init(void)
1789 {
1790         /* Register the McBSP driver */
1791         return platform_driver_register(&omap_mcbsp_driver);
1792 }