arch/arm/plat-omap/mcbsp.c

   1 /*
   2  * linux/arch/arm/plat-omap/mcbsp.c
   3  *
   4  * Copyright (C) 2004 Nokia Corporation
   5  * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
   6  *
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * Multichannel mode not supported.
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/init.h>
  17 #include <linux/device.h>
  18 #include <linux/wait.h>
  19 #include <linux/completion.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/err.h>
  22 #include <linux/clk.h>
  23 #include <linux/delay.h>
  24
  25 #include <asm/io.h>
  26 #include <asm/irq.h>
  27
  28 #include <asm/arch/dma.h>
  29 #include <asm/arch/mux.h>
  30 #include <asm/arch/irqs.h>
  31 #include <asm/arch/dsp_common.h>
  32 #include <asm/arch/mcbsp.h>
  33
  34 #ifdef CONFIG_MCBSP_DEBUG
  35 #define DBG(x...)       printk(x)
  36 #else
  37 #define DBG(x...)                       do { } while (0)
  38 #endif
  39
  40 struct omap_mcbsp {
  41         u32                          io_base;
  42         u8                           id;
  43         u8                           free;
  44         omap_mcbsp_word_length       rx_word_length;
  45         omap_mcbsp_word_length       tx_word_length;
  46
  47         omap_mcbsp_io_type_t         io_type; /* IRQ or poll */
  48         /* IRQ based TX/RX */
  49         int                          rx_irq;
  50         int                          tx_irq;
  51
  52         /* DMA stuff */
  53         u8                           dma_rx_sync;
  54         short                        dma_rx_lch;
  55         u8                           dma_tx_sync;
  56         short                        dma_tx_lch;
  57
  58         /* Completion queues */
  59         struct completion            tx_irq_completion;
  60         struct completion            rx_irq_completion;
  61         struct completion            tx_dma_completion;
  62         struct completion            rx_dma_completion;
  63
  64         spinlock_t                   lock;
  65 };
  66
  67 static struct omap_mcbsp mcbsp[OMAP_MAX_MCBSP_COUNT];
  68 #ifdef CONFIG_ARCH_OMAP1
  69 static struct clk *mcbsp_dsp_ck = 0;
  70 static struct clk *mcbsp_api_ck = 0;
  71 static struct clk *mcbsp_dspxor_ck = 0;
  72 #endif
  73 #ifdef CONFIG_ARCH_OMAP2
  74 static struct clk *mcbsp1_ick = 0;
  75 static struct clk *mcbsp1_fck = 0;
  76 static struct clk *mcbsp2_ick = 0;
  77 static struct clk *mcbsp2_fck = 0;
  78 #endif
  79
  80 static void omap_mcbsp_dump_reg(u8 id)
  81 {
  82         DBG("**** MCBSP%d regs ****\n", mcbsp[id].id);
  83         DBG("DRR2:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DRR2));
  84         DBG("DRR1:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DRR1));
  85         DBG("DXR2:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DXR2));
  86         DBG("DXR1:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DXR1));
  87         DBG("SPCR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR2));
  88         DBG("SPCR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR1));
  89         DBG("RCR2:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, RCR2));
  90         DBG("RCR1:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, RCR1));
  91         DBG("XCR2:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, XCR2));
  92         DBG("XCR1:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, XCR1));
  93         DBG("SRGR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR2));
  94         DBG("SRGR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR1));
  95         DBG("PCR0:  0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, PCR0));
  96         DBG("***********************\n");
  97 }
  98
  99 static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
 100 {
 101         struct omap_mcbsp *mcbsp_tx = dev_id;
 102
 103         DBG("TX IRQ callback : 0x%x\n",
 104             OMAP_MCBSP_READ(mcbsp_tx->io_base, SPCR2));
 105
 106         complete(&mcbsp_tx->tx_irq_completion);
 107         return IRQ_HANDLED;
 108 }
 109
 110 static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
 111 {
 112         struct omap_mcbsp *mcbsp_rx = dev_id;
 113
 114         DBG("RX IRQ callback : 0x%x\n",
 115             OMAP_MCBSP_READ(mcbsp_rx->io_base, SPCR2));
 116
 117         complete(&mcbsp_rx->rx_irq_completion);
 118         return IRQ_HANDLED;
 119 }
 120
 121 static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data)
 122 {
 123         struct omap_mcbsp *mcbsp_dma_tx = data;
 124
 125         DBG("TX DMA callback : 0x%x\n",
 126             OMAP_MCBSP_READ(mcbsp_dma_tx->io_base, SPCR2));
 127
 128         /* We can free the channels */
 129         omap_free_dma(mcbsp_dma_tx->dma_tx_lch);
 130         mcbsp_dma_tx->dma_tx_lch = -1;
 131
 132         complete(&mcbsp_dma_tx->tx_dma_completion);
 133 }
 134
 135 static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
 136 {
 137         struct omap_mcbsp *mcbsp_dma_rx = data;
 138
 139         DBG("RX DMA callback : 0x%x\n",
 140             OMAP_MCBSP_READ(mcbsp_dma_rx->io_base, SPCR2));
 141
 142         /* We can free the channels */
 143         omap_free_dma(mcbsp_dma_rx->dma_rx_lch);
 144         mcbsp_dma_rx->dma_rx_lch = -1;
 145
 146         complete(&mcbsp_dma_rx->rx_dma_completion);
 147 }
 148
 149
 150 /*
 151  * omap_mcbsp_config simply write a config to the
 152  * appropriate McBSP.
 153  * You either call this function or set the McBSP registers
 154  * by yourself before calling omap_mcbsp_start().
 155  */
 156
 157 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config)
 158 {
 159         u32 io_base = mcbsp[id].io_base;
 160
 161         DBG("OMAP-McBSP: McBSP%d  io_base: 0x%8x\n", id+1, io_base);
 162
 163         /* We write the given config */
 164         OMAP_MCBSP_WRITE(io_base, SPCR2, config->spcr2);
 165         OMAP_MCBSP_WRITE(io_base, SPCR1, config->spcr1);
 166         OMAP_MCBSP_WRITE(io_base, RCR2, config->rcr2);
 167         OMAP_MCBSP_WRITE(io_base, RCR1, config->rcr1);
 168         OMAP_MCBSP_WRITE(io_base, XCR2, config->xcr2);
 169         OMAP_MCBSP_WRITE(io_base, XCR1, config->xcr1);
 170         OMAP_MCBSP_WRITE(io_base, SRGR2, config->srgr2);
 171         OMAP_MCBSP_WRITE(io_base, SRGR1, config->srgr1);
 172         OMAP_MCBSP_WRITE(io_base, MCR2, config->mcr2);
 173         OMAP_MCBSP_WRITE(io_base, MCR1, config->mcr1);
 174         OMAP_MCBSP_WRITE(io_base, PCR0, config->pcr0);
 175 }
 176
 177
 178
 179 static int omap_mcbsp_check(unsigned int id)
 180 {
 181         if (cpu_is_omap730()) {
 182                 if (id > OMAP_MAX_MCBSP_COUNT - 1) {
 183                        printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n", id + 1);
 184                        return -1;
 185                 }
 186                 return 0;
 187         }
 188
 189         if (cpu_is_omap15xx() || cpu_is_omap16xx() || cpu_is_omap24xx()) {
 190                 if (id > OMAP_MAX_MCBSP_COUNT) {
 191                         printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n", id + 1);
 192                         return -1;
 193                 }
 194                 return 0;
 195         }
 196
 197         return -1;
 198 }
 199
 200 #ifdef CONFIG_ARCH_OMAP1
 201 static void omap_mcbsp_dsp_request(void)
 202 {
 203         if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
 204                 int ret;
 205
 206                 ret = omap_dsp_request_mem();
 207                 if (ret < 0) {
 208                         printk(KERN_ERR "Could not get dsp memory: %i\n", ret);
 209                         return;
 210                 }
 211
 212                 clk_enable(mcbsp_dsp_ck);
 213                 clk_enable(mcbsp_api_ck);
 214
 215                 /* enable 12MHz clock to mcbsp 1 & 3 */
 216                 clk_enable(mcbsp_dspxor_ck);
 217
 218                 /*
 219                  * DSP external peripheral reset
 220                  * FIXME: This should be moved to dsp code
 221                  */
 222                 __raw_writew(__raw_readw(DSP_RSTCT2) | 1 | 1 << 1,
 223                              DSP_RSTCT2);
 224         }
 225 }
 226
 227 static void omap_mcbsp_dsp_free(void)
 228 {
 229         if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
 230                 omap_dsp_release_mem();
 231                 clk_disable(mcbsp_dspxor_ck);
 232                 clk_disable(mcbsp_dsp_ck);
 233                 clk_disable(mcbsp_api_ck);
 234         }
 235 }
 236 #endif
 237
 238 #ifdef CONFIG_ARCH_OMAP2
 239 static void omap2_mcbsp2_mux_setup(void)
 240 {
 241         if (cpu_is_omap2420()) {
 242                 omap_cfg_reg(Y15_24XX_MCBSP2_CLKX);
 243                 omap_cfg_reg(R14_24XX_MCBSP2_FSX);
 244                 omap_cfg_reg(W15_24XX_MCBSP2_DR);
 245                 omap_cfg_reg(V15_24XX_MCBSP2_DX);
 246                 omap_cfg_reg(V14_24XX_GPIO117);
 247         }
 248         /*
 249          * Need to add MUX settings for OMAP 2430 SDP
 250          */
 251 }
 252 #endif
 253
 254 /*
 255  * We can choose between IRQ based or polled IO.
 256  * This needs to be called before omap_mcbsp_request().
 257  */
 258 int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type)
 259 {
 260         if (omap_mcbsp_check(id) < 0)
 261                 return -EINVAL;
 262
 263         spin_lock(&mcbsp[id].lock);
 264
 265         if (!mcbsp[id].free) {
 266                 printk (KERN_ERR "OMAP-McBSP: McBSP%d is currently in use\n", id + 1);
 267                 spin_unlock(&mcbsp[id].lock);
 268                 return -EINVAL;
 269         }
 270
 271         mcbsp[id].io_type = io_type;
 272
 273         spin_unlock(&mcbsp[id].lock);
 274
 275         return 0;
 276 }
 277
 278 int omap_mcbsp_request(unsigned int id)
 279 {
 280         int err;
 281
 282         if (omap_mcbsp_check(id) < 0)
 283                 return -EINVAL;
 284
 285 #ifdef CONFIG_ARCH_OMAP1
 286         /*
 287          * On 1510, 1610 and 1710, McBSP1 and McBSP3
 288          * are DSP public peripherals.
 289          */
 290         if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3)
 291                 omap_mcbsp_dsp_request();
 292 #endif
 293
 294 #ifdef CONFIG_ARCH_OMAP2
 295         if (cpu_is_omap24xx()) {
 296                 if (id == OMAP_MCBSP1) {
 297                         clk_enable(mcbsp1_ick);
 298                         clk_enable(mcbsp1_fck);
 299                 } else {
 300                         clk_enable(mcbsp2_ick);
 301                         clk_enable(mcbsp2_fck);
 302                 }
 303         }
 304 #endif
 305
 306         spin_lock(&mcbsp[id].lock);
 307         if (!mcbsp[id].free) {
 308                 printk (KERN_ERR "OMAP-McBSP: McBSP%d is currently in use\n", id + 1);
 309                 spin_unlock(&mcbsp[id].lock);
 310                 return -1;
 311         }
 312
 313         mcbsp[id].free = 0;
 314         spin_unlock(&mcbsp[id].lock);
 315
 316         if (mcbsp[id].io_type == OMAP_MCBSP_IRQ_IO) {
 317                 /* We need to get IRQs here */
 318                 err = request_irq(mcbsp[id].tx_irq, omap_mcbsp_tx_irq_handler, 0,
 319                                   "McBSP",
 320                                   (void *) (&mcbsp[id]));
 321                 if (err != 0) {
 322                         printk(KERN_ERR "OMAP-McBSP: Unable to request TX IRQ %d for McBSP%d\n",
 323                                mcbsp[id].tx_irq, mcbsp[id].id);
 324                         return err;
 325                 }
 326
 327                 init_completion(&(mcbsp[id].tx_irq_completion));
 328
 329
 330                 err = request_irq(mcbsp[id].rx_irq, omap_mcbsp_rx_irq_handler, 0,
 331                                   "McBSP",
 332                                   (void *) (&mcbsp[id]));
 333                 if (err != 0) {
 334                         printk(KERN_ERR "OMAP-McBSP: Unable to request RX IRQ %d for McBSP%d\n",
 335                                mcbsp[id].rx_irq, mcbsp[id].id);
 336                         free_irq(mcbsp[id].tx_irq, (void *) (&mcbsp[id]));
 337                         return err;
 338                 }
 339
 340                 init_completion(&(mcbsp[id].rx_irq_completion));
 341         }
 342
 343         return 0;
 344
 345 }
 346
 347 void omap_mcbsp_free(unsigned int id)
 348 {
 349         if (omap_mcbsp_check(id) < 0)
 350                 return;
 351
 352 #ifdef CONFIG_ARCH_OMAP1
 353         if (cpu_class_is_omap1()) {
 354                 if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3)
 355                         omap_mcbsp_dsp_free();
 356         }
 357 #endif
 358
 359 #ifdef CONFIG_ARCH_OMAP2
 360         if (cpu_is_omap24xx()) {
 361                 if (id == OMAP_MCBSP1) {
 362                         clk_disable(mcbsp1_ick);
 363                         clk_disable(mcbsp1_fck);
 364                 } else {
 365                         clk_disable(mcbsp2_ick);
 366                         clk_disable(mcbsp2_fck);
 367                 }
 368         }
 369 #endif
 370
 371         spin_lock(&mcbsp[id].lock);
 372         if (mcbsp[id].free) {
 373                 printk (KERN_ERR "OMAP-McBSP: McBSP%d was not reserved\n", id + 1);
 374                 spin_unlock(&mcbsp[id].lock);
 375                 return;
 376         }
 377
 378         mcbsp[id].free = 1;
 379         spin_unlock(&mcbsp[id].lock);
 380
 381         if (mcbsp[id].io_type == OMAP_MCBSP_IRQ_IO) {
 382                 /* Free IRQs */
 383                 free_irq(mcbsp[id].rx_irq, (void *) (&mcbsp[id]));
 384                 free_irq(mcbsp[id].tx_irq, (void *) (&mcbsp[id]));
 385         }
 386 }
 387
 388 /*
 389  * Here we start the McBSP, by enabling the sample
 390  * generator, both transmitter and receivers,
 391  * and the frame sync.
 392  */
 393 void omap_mcbsp_start(unsigned int id)
 394 {
 395         u32 io_base;
 396         u16 w;
 397
 398         if (omap_mcbsp_check(id) < 0)
 399                 return;
 400
 401         io_base = mcbsp[id].io_base;
 402
 403         mcbsp[id].rx_word_length = ((OMAP_MCBSP_READ(io_base, RCR1) >> 5) & 0x7);
 404         mcbsp[id].tx_word_length = ((OMAP_MCBSP_READ(io_base, XCR1) >> 5) & 0x7);
 405
 406         /* Start the sample generator */
 407         w = OMAP_MCBSP_READ(io_base, SPCR2);
 408         OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 6));
 409
 410         /* Enable transmitter and receiver */
 411         w = OMAP_MCBSP_READ(io_base, SPCR2);
 412         OMAP_MCBSP_WRITE(io_base, SPCR2, w | 1);
 413
 414         w = OMAP_MCBSP_READ(io_base, SPCR1);
 415         OMAP_MCBSP_WRITE(io_base, SPCR1, w | 1);
 416
 417         udelay(100);
 418
 419         /* Start frame sync */
 420         w = OMAP_MCBSP_READ(io_base, SPCR2);
 421         OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 7));
 422
 423         /* Dump McBSP Regs */
 424         omap_mcbsp_dump_reg(id);
 425
 426 }
 427
 428 void omap_mcbsp_stop(unsigned int id)
 429 {
 430         u32 io_base;
 431         u16 w;
 432
 433         if (omap_mcbsp_check(id) < 0)
 434                 return;
 435
 436         io_base = mcbsp[id].io_base;
 437
 438         /* Reset transmitter */
 439         w = OMAP_MCBSP_READ(io_base, SPCR2);
 440         OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1));
 441
 442         /* Reset receiver */
 443         w = OMAP_MCBSP_READ(io_base, SPCR1);
 444         OMAP_MCBSP_WRITE(io_base, SPCR1, w & ~(1));
 445
 446         /* Reset the sample rate generator */
 447         w = OMAP_MCBSP_READ(io_base, SPCR2);
 448         OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1 << 6));
 449 }
 450
 451
 452 /* polled mcbsp i/o operations */
 453 int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
 454 {
 455         u32 base = mcbsp[id].io_base;
 456         writew(buf, base + OMAP_MCBSP_REG_DXR1);
 457         /* if frame sync error - clear the error */
 458         if (readw(base + OMAP_MCBSP_REG_SPCR2) & XSYNC_ERR) {
 459                 /* clear error */
 460                 writew(readw(base + OMAP_MCBSP_REG_SPCR2) & (~XSYNC_ERR),
 461                        base + OMAP_MCBSP_REG_SPCR2);
 462                 /* resend */
 463                 return -1;
 464         } else {
 465                 /* wait for transmit confirmation */
 466                 int attemps = 0;
 467                 while (!(readw(base + OMAP_MCBSP_REG_SPCR2) & XRDY)) {
 468                         if (attemps++ > 1000) {
 469                                 writew(readw(base + OMAP_MCBSP_REG_SPCR2) &
 470                                        (~XRST),
 471                                        base + OMAP_MCBSP_REG_SPCR2);
 472                                 udelay(10);
 473                                 writew(readw(base + OMAP_MCBSP_REG_SPCR2) |
 474                                        (XRST),
 475                                        base + OMAP_MCBSP_REG_SPCR2);
 476                                 udelay(10);
 477                                 printk(KERN_ERR
 478                                        " Could not write to McBSP Register\n");
 479                                 return -2;
 480                         }
 481                 }
 482         }
 483         return 0;
 484 }
 485
 486 int omap_mcbsp_pollread(unsigned int id, u16 * buf)
 487 {
 488         u32 base = mcbsp[id].io_base;
 489         /* if frame sync error - clear the error */
 490         if (readw(base + OMAP_MCBSP_REG_SPCR1) & RSYNC_ERR) {
 491                 /* clear error */
 492                 writew(readw(base + OMAP_MCBSP_REG_SPCR1) & (~RSYNC_ERR),
 493                        base + OMAP_MCBSP_REG_SPCR1);
 494                 /* resend */
 495                 return -1;
 496         } else {
 497                 /* wait for recieve confirmation */
 498                 int attemps = 0;
 499                 while (!(readw(base + OMAP_MCBSP_REG_SPCR1) & RRDY)) {
 500                         if (attemps++ > 1000) {
 501                                 writew(readw(base + OMAP_MCBSP_REG_SPCR1) &
 502                                        (~RRST),
 503                                        base + OMAP_MCBSP_REG_SPCR1);
 504                                 udelay(10);
 505                                 writew(readw(base + OMAP_MCBSP_REG_SPCR1) |
 506                                        (RRST),
 507                                        base + OMAP_MCBSP_REG_SPCR1);
 508                                 udelay(10);
 509                                 printk(KERN_ERR
 510                                        " Could not read from McBSP Register\n");
 511                                 return -2;
 512                         }
 513                 }
 514         }
 515         *buf = readw(base + OMAP_MCBSP_REG_DRR1);
 516         return 0;
 517 }
 518
 519 /*
 520  * IRQ based word transmission.
 521  */
 522 void omap_mcbsp_xmit_word(unsigned int id, u32 word)
 523 {
 524         u32 io_base;
 525         omap_mcbsp_word_length word_length = mcbsp[id].tx_word_length;
 526
 527         if (omap_mcbsp_check(id) < 0)
 528                 return;
 529
 530         io_base = mcbsp[id].io_base;
 531
 532         wait_for_completion(&(mcbsp[id].tx_irq_completion));
 533
 534         if (word_length > OMAP_MCBSP_WORD_16)
 535                 OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16);
 536         OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff);
 537 }
 538
 539 u32 omap_mcbsp_recv_word(unsigned int id)
 540 {
 541         u32 io_base;
 542         u16 word_lsb, word_msb = 0;
 543         omap_mcbsp_word_length word_length = mcbsp[id].rx_word_length;
 544
 545         if (omap_mcbsp_check(id) < 0)
 546                 return -EINVAL;
 547
 548         io_base = mcbsp[id].io_base;
 549
 550         wait_for_completion(&(mcbsp[id].rx_irq_completion));
 551
 552         if (word_length > OMAP_MCBSP_WORD_16)
 553                 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
 554         word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
 555
 556         return (word_lsb | (word_msb << 16));
 557 }
 558
 559
 560 int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
 561 {
 562         u32 io_base = mcbsp[id].io_base;
 563         omap_mcbsp_word_length tx_word_length = mcbsp[id].tx_word_length;
 564         omap_mcbsp_word_length rx_word_length = mcbsp[id].rx_word_length;
 565         u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
 566
 567         if (tx_word_length != rx_word_length)
 568                 return -EINVAL;
 569
 570         /* First we wait for the transmitter to be ready */
 571         spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
 572         while (!(spcr2 & XRDY)) {
 573                 spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
 574                 if (attempts++ > 1000) {
 575                         /* We must reset the transmitter */
 576                         OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 & (~XRST));
 577                         udelay(10);
 578                         OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
 579                         udelay(10);
 580                         printk("McBSP transmitter not ready\n");
 581                         return -EAGAIN;
 582                 }
 583         }
 584
 585         /* Now we can push the data */
 586         if (tx_word_length > OMAP_MCBSP_WORD_16)
 587                 OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16);
 588         OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff);
 589
 590         /* We wait for the receiver to be ready */
 591         spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
 592         while (!(spcr1 & RRDY)) {
 593                 spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
 594                 if (attempts++ > 1000) {
 595                         /* We must reset the receiver */
 596                         OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 & (~RRST));
 597                         udelay(10);
 598                         OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
 599                         udelay(10);
 600                         printk("McBSP receiver not ready\n");
 601                         return -EAGAIN;
 602                 }
 603         }
 604
 605         /* Receiver is ready, let's read the dummy data */
 606         if (rx_word_length > OMAP_MCBSP_WORD_16)
 607                 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
 608         word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
 609
 610         return 0;
 611 }
 612
 613 int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word)
 614 {
 615         u32 io_base = mcbsp[id].io_base, clock_word = 0;
 616         omap_mcbsp_word_length tx_word_length = mcbsp[id].tx_word_length;
 617         omap_mcbsp_word_length rx_word_length = mcbsp[id].rx_word_length;
 618         u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
 619
 620         if (tx_word_length != rx_word_length)
 621                 return -EINVAL;
 622
 623         /* First we wait for the transmitter to be ready */
 624         spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
 625         while (!(spcr2 & XRDY)) {
 626                 spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
 627                 if (attempts++ > 1000) {
 628                         /* We must reset the transmitter */
 629                         OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 & (~XRST));
 630                         udelay(10);
 631                         OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
 632                         udelay(10);
 633                         printk("McBSP transmitter not ready\n");
 634                         return -EAGAIN;
 635                 }
 636         }
 637
 638         /* We first need to enable the bus clock */
 639         if (tx_word_length > OMAP_MCBSP_WORD_16)
 640                 OMAP_MCBSP_WRITE(io_base, DXR2, clock_word >> 16);
 641         OMAP_MCBSP_WRITE(io_base, DXR1, clock_word & 0xffff);
 642
 643         /* We wait for the receiver to be ready */
 644         spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
 645         while (!(spcr1 & RRDY)) {
 646                 spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
 647                 if (attempts++ > 1000) {
 648                         /* We must reset the receiver */
 649                         OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 & (~RRST));
 650                         udelay(10);
 651                         OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
 652                         udelay(10);
 653                         printk("McBSP receiver not ready\n");
 654                         return -EAGAIN;
 655                 }
 656         }
 657
 658         /* Receiver is ready, there is something for us */
 659         if (rx_word_length > OMAP_MCBSP_WORD_16)
 660                 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
 661         word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
 662
 663         word[0] = (word_lsb | (word_msb << 16));
 664
 665         return 0;
 666 }
 667
 668
 669 /*
 670  * Simple DMA based buffer rx/tx routines.
 671  * Nothing fancy, just a single buffer tx/rx through DMA.
 672  * The DMA resources are released once the transfer is done.
 673  * For anything fancier, you should use your own customized DMA
 674  * routines and callbacks.
 675  */
 676 int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length)
 677 {
 678         int dma_tx_ch;
 679         int src_port = 0;
 680         int dest_port = 0;
 681         int sync_dev = 0;
 682
 683         if (omap_mcbsp_check(id) < 0)
 684                 return -EINVAL;
 685
 686         if (omap_request_dma(mcbsp[id].dma_tx_sync, "McBSP TX", omap_mcbsp_tx_dma_callback,
 687                              &mcbsp[id],
 688                              &dma_tx_ch)) {
 689                 printk("OMAP-McBSP: Unable to request DMA channel for McBSP%d TX. Trying IRQ based TX\n", id+1);
 690                 return -EAGAIN;
 691         }
 692         mcbsp[id].dma_tx_lch = dma_tx_ch;
 693
 694         DBG("TX DMA on channel %d\n", dma_tx_ch);
 695
 696         init_completion(&(mcbsp[id].tx_dma_completion));
 697
 698         if (cpu_class_is_omap1()) {
 699                 src_port = OMAP_DMA_PORT_TIPB;
 700                 dest_port = OMAP_DMA_PORT_EMIFF;
 701         }
 702         if (cpu_is_omap24xx())
 703                 sync_dev = mcbsp[id].dma_tx_sync;
 704
 705         omap_set_dma_transfer_params(mcbsp[id].dma_tx_lch,
 706                                      OMAP_DMA_DATA_TYPE_S16,
 707                                      length >> 1, 1,
 708                                      OMAP_DMA_SYNC_ELEMENT,
 709          sync_dev, 0);
 710
 711         omap_set_dma_dest_params(mcbsp[id].dma_tx_lch,
 712                                  src_port,
 713                                  OMAP_DMA_AMODE_CONSTANT,
 714                                  mcbsp[id].io_base + OMAP_MCBSP_REG_DXR1,
 715                                  0, 0);
 716
 717         omap_set_dma_src_params(mcbsp[id].dma_tx_lch,
 718                                 dest_port,
 719                                 OMAP_DMA_AMODE_POST_INC,
 720                                 buffer,
 721                                 0, 0);
 722
 723         omap_start_dma(mcbsp[id].dma_tx_lch);
 724         wait_for_completion(&(mcbsp[id].tx_dma_completion));
 725         return 0;
 726 }
 727
 728
 729 int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length)
 730 {
 731         int dma_rx_ch;
 732         int src_port = 0;
 733         int dest_port = 0;
 734         int sync_dev = 0;
 735
 736         if (omap_mcbsp_check(id) < 0)
 737                 return -EINVAL;
 738
 739         if (omap_request_dma(mcbsp[id].dma_rx_sync, "McBSP RX", omap_mcbsp_rx_dma_callback,
 740                              &mcbsp[id],
 741                              &dma_rx_ch)) {
 742                 printk("Unable to request DMA channel for McBSP%d RX. Trying IRQ based RX\n", id+1);
 743                 return -EAGAIN;
 744         }
 745         mcbsp[id].dma_rx_lch = dma_rx_ch;
 746
 747         DBG("RX DMA on channel %d\n", dma_rx_ch);
 748
 749         init_completion(&(mcbsp[id].rx_dma_completion));
 750
 751         if (cpu_class_is_omap1()) {
 752                 src_port = OMAP_DMA_PORT_TIPB;
 753                 dest_port = OMAP_DMA_PORT_EMIFF;
 754         }
 755         if (cpu_is_omap24xx())
 756                 sync_dev = mcbsp[id].dma_rx_sync;
 757
 758         omap_set_dma_transfer_params(mcbsp[id].dma_rx_lch,
 759                                      OMAP_DMA_DATA_TYPE_S16,
 760                                      length >> 1, 1,
 761                                      OMAP_DMA_SYNC_ELEMENT,
 762          sync_dev, 0);
 763
 764         omap_set_dma_src_params(mcbsp[id].dma_rx_lch,
 765                                 src_port,
 766                                 OMAP_DMA_AMODE_CONSTANT,
 767                                 mcbsp[id].io_base + OMAP_MCBSP_REG_DRR1,
 768                                 0, 0);
 769
 770         omap_set_dma_dest_params(mcbsp[id].dma_rx_lch,
 771                                  dest_port,
 772                                  OMAP_DMA_AMODE_POST_INC,
 773                                  buffer,
 774                                  0, 0);
 775
 776         omap_start_dma(mcbsp[id].dma_rx_lch);
 777         wait_for_completion(&(mcbsp[id].rx_dma_completion));
 778         return 0;
 779 }
 780
 781
 782 /*
 783  * SPI wrapper.
 784  * Since SPI setup is much simpler than the generic McBSP one,
 785  * this wrapper just need an omap_mcbsp_spi_cfg structure as an input.
 786  * Once this is done, you can call omap_mcbsp_start().
 787  */
 788 void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg)
 789 {
 790         struct omap_mcbsp_reg_cfg mcbsp_cfg;
 791
 792         if (omap_mcbsp_check(id) < 0)
 793                 return;
 794
 795         memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg));
 796
 797         /* SPI has only one frame */
 798         mcbsp_cfg.rcr1 |= (RWDLEN1(spi_cfg->word_length) | RFRLEN1(0));
 799         mcbsp_cfg.xcr1 |= (XWDLEN1(spi_cfg->word_length) | XFRLEN1(0));
 800
 801         /* Clock stop mode */
 802         if (spi_cfg->clk_stp_mode == OMAP_MCBSP_CLK_STP_MODE_NO_DELAY)
 803                 mcbsp_cfg.spcr1 |= (1 << 12);
 804         else
 805                 mcbsp_cfg.spcr1 |= (3 << 11);
 806
 807         /* Set clock parities */
 808         if (spi_cfg->rx_clock_polarity == OMAP_MCBSP_CLK_RISING)
 809                 mcbsp_cfg.pcr0 |= CLKRP;
 810         else
 811                 mcbsp_cfg.pcr0 &= ~CLKRP;
 812
 813         if (spi_cfg->tx_clock_polarity == OMAP_MCBSP_CLK_RISING)
 814                 mcbsp_cfg.pcr0 &= ~CLKXP;
 815         else
 816                 mcbsp_cfg.pcr0 |= CLKXP;
 817
 818         /* Set SCLKME to 0 and CLKSM to 1 */
 819         mcbsp_cfg.pcr0 &= ~SCLKME;
 820         mcbsp_cfg.srgr2 |= CLKSM;
 821
 822         /* Set FSXP */
 823         if (spi_cfg->fsx_polarity == OMAP_MCBSP_FS_ACTIVE_HIGH)
 824                 mcbsp_cfg.pcr0 &= ~FSXP;
 825         else
 826                 mcbsp_cfg.pcr0 |= FSXP;
 827
 828         if (spi_cfg->spi_mode == OMAP_MCBSP_SPI_MASTER) {
 829                 mcbsp_cfg.pcr0 |= CLKXM;
 830                 mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div -1);
 831                 mcbsp_cfg.pcr0 |= FSXM;
 832                 mcbsp_cfg.srgr2 &= ~FSGM;
 833                 mcbsp_cfg.xcr2 |= XDATDLY(1);
 834                 mcbsp_cfg.rcr2 |= RDATDLY(1);
 835         }
 836         else {
 837                 mcbsp_cfg.pcr0 &= ~CLKXM;
 838                 mcbsp_cfg.srgr1 |= CLKGDV(1);
 839                 mcbsp_cfg.pcr0 &= ~FSXM;
 840                 mcbsp_cfg.xcr2 &= ~XDATDLY(3);
 841                 mcbsp_cfg.rcr2 &= ~RDATDLY(3);
 842         }
 843
 844         mcbsp_cfg.xcr2 &= ~XPHASE;
 845         mcbsp_cfg.rcr2 &= ~RPHASE;
 846
 847         omap_mcbsp_config(id, &mcbsp_cfg);
 848 }
 849
 850
 851 /*
 852  * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
 853  * 730 has only 2 McBSP, and both of them are MPU peripherals.
 854  */
 855 struct omap_mcbsp_info {
 856         u32 virt_base;
 857         u8 dma_rx_sync, dma_tx_sync;
 858         u16 rx_irq, tx_irq;
 859 };
 860
 861 #ifdef CONFIG_ARCH_OMAP730
 862 static const struct omap_mcbsp_info mcbsp_730[] = {
 863         [0] = { .virt_base = io_p2v(OMAP730_MCBSP1_BASE),
 864                 .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
 865                 .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
 866                 .rx_irq = INT_730_McBSP1RX,
 867                 .tx_irq = INT_730_McBSP1TX },
 868         [1] = { .virt_base = io_p2v(OMAP730_MCBSP2_BASE),
 869                 .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
 870                 .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
 871                 .rx_irq = INT_730_McBSP2RX,
 872                 .tx_irq = INT_730_McBSP2TX },
 873 };
 874 #endif
 875
 876 #ifdef CONFIG_ARCH_OMAP15XX
 877 static const struct omap_mcbsp_info mcbsp_1510[] = {
 878         [0] = { .virt_base = OMAP1510_MCBSP1_BASE,
 879                 .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
 880                 .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
 881                 .rx_irq = INT_McBSP1RX,
 882                 .tx_irq = INT_McBSP1TX },
 883         [1] = { .virt_base = io_p2v(OMAP1510_MCBSP2_BASE),
 884                 .dma_rx_sync = OMAP_DMA_MCBSP2_RX,
 885                 .dma_tx_sync = OMAP_DMA_MCBSP2_TX,
 886                 .rx_irq = INT_1510_SPI_RX,
 887                 .tx_irq = INT_1510_SPI_TX },
 888         [2] = { .virt_base = OMAP1510_MCBSP3_BASE,
 889                 .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
 890                 .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
 891                 .rx_irq = INT_McBSP3RX,
 892                 .tx_irq = INT_McBSP3TX },
 893 };
 894 #endif
 895
 896 #if defined(CONFIG_ARCH_OMAP16XX)
 897 static const struct omap_mcbsp_info mcbsp_1610[] = {
 898         [0] = { .virt_base = OMAP1610_MCBSP1_BASE,
 899                 .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
 900                 .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
 901                 .rx_irq = INT_McBSP1RX,
 902                 .tx_irq = INT_McBSP1TX },
 903         [1] = { .virt_base = io_p2v(OMAP1610_MCBSP2_BASE),
 904                 .dma_rx_sync = OMAP_DMA_MCBSP2_RX,
 905                 .dma_tx_sync = OMAP_DMA_MCBSP2_TX,
 906                 .rx_irq = INT_1610_McBSP2_RX,
 907                 .tx_irq = INT_1610_McBSP2_TX },
 908         [2] = { .virt_base = OMAP1610_MCBSP3_BASE,
 909                 .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
 910                 .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
 911                 .rx_irq = INT_McBSP3RX,
 912                 .tx_irq = INT_McBSP3TX },
 913 };
 914 #endif
 915
 916 #if defined(CONFIG_ARCH_OMAP24XX)
 917 static const struct omap_mcbsp_info mcbsp_24xx[] = {
 918         [0] = { .virt_base = IO_ADDRESS(OMAP24XX_MCBSP1_BASE),
 919                 .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX,
 920                 .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
 921                 .rx_irq = INT_24XX_MCBSP1_IRQ_RX,
 922                 .tx_irq = INT_24XX_MCBSP1_IRQ_TX,
 923                 },
 924         [1] = { .virt_base = IO_ADDRESS(OMAP24XX_MCBSP2_BASE),
 925                 .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
 926                 .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
 927                 .rx_irq = INT_24XX_MCBSP2_IRQ_RX,
 928                 .tx_irq = INT_24XX_MCBSP2_IRQ_TX,
 929                 },
 930 };
 931 #endif
 932
 933 static int __init omap_mcbsp_init(void)
 934 {
 935         int mcbsp_count = 0, i;
 936         static const struct omap_mcbsp_info *mcbsp_info;
 937
 938         printk("Initializing OMAP McBSP system\n");
 939
 940 #ifdef CONFIG_ARCH_OMAP1
 941         mcbsp_dsp_ck = clk_get(0, "dsp_ck");
 942         if (IS_ERR(mcbsp_dsp_ck)) {
 943                 printk(KERN_ERR "mcbsp: could not acquire dsp_ck handle.\n");
 944                 return PTR_ERR(mcbsp_dsp_ck);
 945         }
 946         mcbsp_api_ck = clk_get(0, "api_ck");
 947         if (IS_ERR(mcbsp_api_ck)) {
 948                 printk(KERN_ERR "mcbsp: could not acquire api_ck handle.\n");
 949                 return PTR_ERR(mcbsp_api_ck);
 950         }
 951         mcbsp_dspxor_ck = clk_get(0, "dspxor_ck");
 952         if (IS_ERR(mcbsp_dspxor_ck)) {
 953                 printk(KERN_ERR "mcbsp: could not acquire dspxor_ck handle.\n");
 954                 return PTR_ERR(mcbsp_dspxor_ck);
 955         }
 956 #endif
 957 #ifdef CONFIG_ARCH_OMAP2
 958         mcbsp1_ick = clk_get(0, "mcbsp1_ick");
 959         if (IS_ERR(mcbsp1_ick)) {
 960                 printk(KERN_ERR "mcbsp: could not acquire mcbsp1_ick handle.\n");
 961                 return PTR_ERR(mcbsp1_ick);
 962         }
 963         mcbsp1_fck = clk_get(0, "mcbsp1_fck");
 964         if (IS_ERR(mcbsp1_fck)) {
 965                 printk(KERN_ERR "mcbsp: could not acquire mcbsp1_fck handle.\n");
 966                 return PTR_ERR(mcbsp1_fck);
 967         }
 968         mcbsp2_ick = clk_get(0, "mcbsp2_ick");
 969         if (IS_ERR(mcbsp2_ick)) {
 970                 printk(KERN_ERR "mcbsp: could not acquire mcbsp2_ick handle.\n");
 971                 return PTR_ERR(mcbsp2_ick);
 972         }
 973         mcbsp2_fck = clk_get(0, "mcbsp2_fck");
 974         if (IS_ERR(mcbsp2_fck)) {
 975                 printk(KERN_ERR "mcbsp: could not acquire mcbsp2_fck handle.\n");
 976                 return PTR_ERR(mcbsp2_fck);
 977         }
 978 #endif
 979
 980 #ifdef CONFIG_ARCH_OMAP730
 981         if (cpu_is_omap730()) {
 982                 mcbsp_info = mcbsp_730;
 983                 mcbsp_count = ARRAY_SIZE(mcbsp_730);
 984         }
 985 #endif
 986 #ifdef CONFIG_ARCH_OMAP15XX
 987         if (cpu_is_omap15xx()) {
 988                 mcbsp_info = mcbsp_1510;
 989                 mcbsp_count = ARRAY_SIZE(mcbsp_1510);
 990         }
 991 #endif
 992 #if defined(CONFIG_ARCH_OMAP16XX)
 993         if (cpu_is_omap16xx()) {
 994                 mcbsp_info = mcbsp_1610;
 995                 mcbsp_count = ARRAY_SIZE(mcbsp_1610);
 996         }
 997 #endif
 998 #if defined(CONFIG_ARCH_OMAP24XX)
 999         if (cpu_is_omap24xx()) {
1000                 mcbsp_info = mcbsp_24xx;
1001                 mcbsp_count = ARRAY_SIZE(mcbsp_24xx);
1002                 omap2_mcbsp2_mux_setup();
1003         }
1004 #endif
1005         for (i = 0; i < OMAP_MAX_MCBSP_COUNT ; i++) {
1006                 if (i >= mcbsp_count) {
1007                         mcbsp[i].io_base = 0;
1008                         mcbsp[i].free = 0;
1009                         continue;
1010                 }
1011                 mcbsp[i].id = i + 1;
1012                 mcbsp[i].free = 1;
1013                 mcbsp[i].dma_tx_lch = -1;
1014                 mcbsp[i].dma_rx_lch = -1;
1015
1016                 mcbsp[i].io_base = mcbsp_info[i].virt_base;
1017                 mcbsp[i].io_type = OMAP_MCBSP_IRQ_IO; /* Default I/O is IRQ based */
1018                 mcbsp[i].tx_irq = mcbsp_info[i].tx_irq;
1019                 mcbsp[i].rx_irq = mcbsp_info[i].rx_irq;
1020                 mcbsp[i].dma_rx_sync = mcbsp_info[i].dma_rx_sync;
1021                 mcbsp[i].dma_tx_sync = mcbsp_info[i].dma_tx_sync;
1022                 spin_lock_init(&mcbsp[i].lock);
1023         }
1024
1025         return 0;
1026 }
1027
1028 arch_initcall(omap_mcbsp_init);
1029
1030 EXPORT_SYMBOL(omap_mcbsp_config);
1031 EXPORT_SYMBOL(omap_mcbsp_request);
1032 EXPORT_SYMBOL(omap_mcbsp_set_io_type);
1033 EXPORT_SYMBOL(omap_mcbsp_free);
1034 EXPORT_SYMBOL(omap_mcbsp_start);
1035 EXPORT_SYMBOL(omap_mcbsp_stop);
1036 EXPORT_SYMBOL(omap_mcbsp_pollread);
1037 EXPORT_SYMBOL(omap_mcbsp_pollwrite);
1038 EXPORT_SYMBOL(omap_mcbsp_xmit_word);
1039 EXPORT_SYMBOL(omap_mcbsp_recv_word);
1040 EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
1041 EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
1042 EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll);
1043 EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll);
1044 EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);