arch/arm/plat-omap/mcbsp.c

   1 /*
   2  * linux/arch/arm/plat-omap/mcbsp.c
   3  *
   4  * Copyright (C) 2004 Nokia Corporation
   5  * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
   6  *
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * Multichannel mode not supported.
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/init.h>
  17 #include <linux/device.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/wait.h>
  20 #include <linux/completion.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/err.h>
  23 #include <linux/clk.h>
  24 #include <linux/delay.h>
  25 #include <linux/io.h>
  26
  27 #include <plat/dma.h>
  28 #include <plat/mcbsp.h>
  29
  30 struct omap_mcbsp **mcbsp_ptr;
  31 int omap_mcbsp_count;
  32
  33 void omap_mcbsp_write(void __iomem *io_base, u16 reg, u32 val)
  34 {
  35         if (cpu_class_is_omap1() || cpu_is_omap2420())
  36                 __raw_writew((u16)val, io_base + reg);
  37         else
  38                 __raw_writel(val, io_base + reg);
  39 }
  40
  41 int omap_mcbsp_read(void __iomem *io_base, u16 reg)
  42 {
  43         if (cpu_class_is_omap1() || cpu_is_omap2420())
  44                 return __raw_readw(io_base + reg);
  45         else
  46                 return __raw_readl(io_base + reg);
  47 }
  48
  49 #define OMAP_MCBSP_READ(base, reg) \
  50                         omap_mcbsp_read(base, OMAP_MCBSP_REG_##reg)
  51 #define OMAP_MCBSP_WRITE(base, reg, val) \
  52                         omap_mcbsp_write(base, OMAP_MCBSP_REG_##reg, val)
  53
  54 #define omap_mcbsp_check_valid_id(id)   (id < omap_mcbsp_count)
  55 #define id_to_mcbsp_ptr(id)             mcbsp_ptr[id];
  56
  57 static void omap_mcbsp_dump_reg(u8 id)
  58 {
  59         struct omap_mcbsp *mcbsp = id_to_mcbsp_ptr(id);
  60
  61         dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
  62         dev_dbg(mcbsp->dev, "DRR2:  0x%04x\n",
  63                         OMAP_MCBSP_READ(mcbsp->io_base, DRR2));
  64         dev_dbg(mcbsp->dev, "DRR1:  0x%04x\n",
  65                         OMAP_MCBSP_READ(mcbsp->io_base, DRR1));
  66         dev_dbg(mcbsp->dev, "DXR2:  0x%04x\n",
  67                         OMAP_MCBSP_READ(mcbsp->io_base, DXR2));
  68         dev_dbg(mcbsp->dev, "DXR1:  0x%04x\n",
  69                         OMAP_MCBSP_READ(mcbsp->io_base, DXR1));
  70         dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n",
  71                         OMAP_MCBSP_READ(mcbsp->io_base, SPCR2));
  72         dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n",
  73                         OMAP_MCBSP_READ(mcbsp->io_base, SPCR1));
  74         dev_dbg(mcbsp->dev, "RCR2:  0x%04x\n",
  75                         OMAP_MCBSP_READ(mcbsp->io_base, RCR2));
  76         dev_dbg(mcbsp->dev, "RCR1:  0x%04x\n",
  77                         OMAP_MCBSP_READ(mcbsp->io_base, RCR1));
  78         dev_dbg(mcbsp->dev, "XCR2:  0x%04x\n",
  79                         OMAP_MCBSP_READ(mcbsp->io_base, XCR2));
  80         dev_dbg(mcbsp->dev, "XCR1:  0x%04x\n",
  81                         OMAP_MCBSP_READ(mcbsp->io_base, XCR1));
  82         dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n",
  83                         OMAP_MCBSP_READ(mcbsp->io_base, SRGR2));
  84         dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n",
  85                         OMAP_MCBSP_READ(mcbsp->io_base, SRGR1));
  86         dev_dbg(mcbsp->dev, "PCR0:  0x%04x\n",
  87                         OMAP_MCBSP_READ(mcbsp->io_base, PCR0));
  88         dev_dbg(mcbsp->dev, "***********************\n");
  89 }
  90
  91 static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
  92 {
  93         struct omap_mcbsp *mcbsp_tx = dev_id;
  94         u16 irqst_spcr2;
  95
  96         irqst_spcr2 = OMAP_MCBSP_READ(mcbsp_tx->io_base, SPCR2);
  97         dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
  98
  99         if (irqst_spcr2 & XSYNC_ERR) {
 100                 dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n",
 101                         irqst_spcr2);
 102                 /* Writing zero to XSYNC_ERR clears the IRQ */
 103                 OMAP_MCBSP_WRITE(mcbsp_tx->io_base, SPCR2,
 104                         irqst_spcr2 & ~(XSYNC_ERR));
 105         } else {
 106                 complete(&mcbsp_tx->tx_irq_completion);
 107         }
 108
 109         return IRQ_HANDLED;
 110 }
 111
 112 static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
 113 {
 114         struct omap_mcbsp *mcbsp_rx = dev_id;
 115         u16 irqst_spcr1;
 116
 117         irqst_spcr1 = OMAP_MCBSP_READ(mcbsp_rx->io_base, SPCR1);
 118         dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
 119
 120         if (irqst_spcr1 & RSYNC_ERR) {
 121                 dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n",
 122                         irqst_spcr1);
 123                 /* Writing zero to RSYNC_ERR clears the IRQ */
 124                 OMAP_MCBSP_WRITE(mcbsp_rx->io_base, SPCR1,
 125                         irqst_spcr1 & ~(RSYNC_ERR));
 126         } else {
 127                 complete(&mcbsp_rx->tx_irq_completion);
 128         }
 129
 130         return IRQ_HANDLED;
 131 }
 132
 133 static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data)
 134 {
 135         struct omap_mcbsp *mcbsp_dma_tx = data;
 136
 137         dev_dbg(mcbsp_dma_tx->dev, "TX DMA callback : 0x%x\n",
 138                 OMAP_MCBSP_READ(mcbsp_dma_tx->io_base, SPCR2));
 139
 140         /* We can free the channels */
 141         omap_free_dma(mcbsp_dma_tx->dma_tx_lch);
 142         mcbsp_dma_tx->dma_tx_lch = -1;
 143
 144         complete(&mcbsp_dma_tx->tx_dma_completion);
 145 }
 146
 147 static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
 148 {
 149         struct omap_mcbsp *mcbsp_dma_rx = data;
 150
 151         dev_dbg(mcbsp_dma_rx->dev, "RX DMA callback : 0x%x\n",
 152                 OMAP_MCBSP_READ(mcbsp_dma_rx->io_base, SPCR2));
 153
 154         /* We can free the channels */
 155         omap_free_dma(mcbsp_dma_rx->dma_rx_lch);
 156         mcbsp_dma_rx->dma_rx_lch = -1;
 157
 158         complete(&mcbsp_dma_rx->rx_dma_completion);
 159 }
 160
 161 /*
 162  * omap_mcbsp_config simply write a config to the
 163  * appropriate McBSP.
 164  * You either call this function or set the McBSP registers
 165  * by yourself before calling omap_mcbsp_start().
 166  */
 167 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
 168 {
 169         struct omap_mcbsp *mcbsp;
 170         void __iomem *io_base;
 171
 172         if (!omap_mcbsp_check_valid_id(id)) {
 173                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 174                 return;
 175         }
 176         mcbsp = id_to_mcbsp_ptr(id);
 177
 178         io_base = mcbsp->io_base;
 179         dev_dbg(mcbsp->dev, "Configuring McBSP%d  phys_base: 0x%08lx\n",
 180                         mcbsp->id, mcbsp->phys_base);
 181
 182         /* We write the given config */
 183         OMAP_MCBSP_WRITE(io_base, SPCR2, config->spcr2);
 184         OMAP_MCBSP_WRITE(io_base, SPCR1, config->spcr1);
 185         OMAP_MCBSP_WRITE(io_base, RCR2, config->rcr2);
 186         OMAP_MCBSP_WRITE(io_base, RCR1, config->rcr1);
 187         OMAP_MCBSP_WRITE(io_base, XCR2, config->xcr2);
 188         OMAP_MCBSP_WRITE(io_base, XCR1, config->xcr1);
 189         OMAP_MCBSP_WRITE(io_base, SRGR2, config->srgr2);
 190         OMAP_MCBSP_WRITE(io_base, SRGR1, config->srgr1);
 191         OMAP_MCBSP_WRITE(io_base, MCR2, config->mcr2);
 192         OMAP_MCBSP_WRITE(io_base, MCR1, config->mcr1);
 193         OMAP_MCBSP_WRITE(io_base, PCR0, config->pcr0);
 194         if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
 195                 OMAP_MCBSP_WRITE(io_base, XCCR, config->xccr);
 196                 OMAP_MCBSP_WRITE(io_base, RCCR, config->rccr);
 197         }
 198 }
 199 EXPORT_SYMBOL(omap_mcbsp_config);
 200
 201 #ifdef CONFIG_ARCH_OMAP34XX
 202 /*
 203  * omap_mcbsp_set_tx_threshold configures how to deal
 204  * with transmit threshold. the threshold value and handler can be
 205  * configure in here.
 206  */
 207 void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
 208 {
 209         struct omap_mcbsp *mcbsp;
 210         void __iomem *io_base;
 211
 212         if (!cpu_is_omap34xx())
 213                 return;
 214
 215         if (!omap_mcbsp_check_valid_id(id)) {
 216                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 217                 return;
 218         }
 219         mcbsp = id_to_mcbsp_ptr(id);
 220         io_base = mcbsp->io_base;
 221
 222         OMAP_MCBSP_WRITE(io_base, THRSH2, threshold);
 223 }
 224 EXPORT_SYMBOL(omap_mcbsp_set_tx_threshold);
 225
 226 /*
 227  * omap_mcbsp_set_rx_threshold configures how to deal
 228  * with receive threshold. the threshold value and handler can be
 229  * configure in here.
 230  */
 231 void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
 232 {
 233         struct omap_mcbsp *mcbsp;
 234         void __iomem *io_base;
 235
 236         if (!cpu_is_omap34xx())
 237                 return;
 238
 239         if (!omap_mcbsp_check_valid_id(id)) {
 240                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 241                 return;
 242         }
 243         mcbsp = id_to_mcbsp_ptr(id);
 244         io_base = mcbsp->io_base;
 245
 246         OMAP_MCBSP_WRITE(io_base, THRSH1, threshold);
 247 }
 248 EXPORT_SYMBOL(omap_mcbsp_set_rx_threshold);
 249
 250 /*
 251  * omap_mcbsp_get_max_tx_thres just return the current configured
 252  * maximum threshold for transmission
 253  */
 254 u16 omap_mcbsp_get_max_tx_threshold(unsigned int id)
 255 {
 256         struct omap_mcbsp *mcbsp;
 257
 258         if (!omap_mcbsp_check_valid_id(id)) {
 259                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 260                 return -ENODEV;
 261         }
 262         mcbsp = id_to_mcbsp_ptr(id);
 263
 264         return mcbsp->max_tx_thres;
 265 }
 266 EXPORT_SYMBOL(omap_mcbsp_get_max_tx_threshold);
 267
 268 /*
 269  * omap_mcbsp_get_max_rx_thres just return the current configured
 270  * maximum threshold for reception
 271  */
 272 u16 omap_mcbsp_get_max_rx_threshold(unsigned int id)
 273 {
 274         struct omap_mcbsp *mcbsp;
 275
 276         if (!omap_mcbsp_check_valid_id(id)) {
 277                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 278                 return -ENODEV;
 279         }
 280         mcbsp = id_to_mcbsp_ptr(id);
 281
 282         return mcbsp->max_rx_thres;
 283 }
 284 EXPORT_SYMBOL(omap_mcbsp_get_max_rx_threshold);
 285
 286 /*
 287  * omap_mcbsp_get_dma_op_mode just return the current configured
 288  * operating mode for the mcbsp channel
 289  */
 290 int omap_mcbsp_get_dma_op_mode(unsigned int id)
 291 {
 292         struct omap_mcbsp *mcbsp;
 293         int dma_op_mode;
 294
 295         if (!omap_mcbsp_check_valid_id(id)) {
 296                 printk(KERN_ERR "%s: Invalid id (%u)\n", __func__, id + 1);
 297                 return -ENODEV;
 298         }
 299         mcbsp = id_to_mcbsp_ptr(id);
 300
 301         dma_op_mode = mcbsp->dma_op_mode;
 302
 303         return dma_op_mode;
 304 }
 305 EXPORT_SYMBOL(omap_mcbsp_get_dma_op_mode);
 306
 307 static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp)
 308 {
 309         /*
 310          * Enable wakup behavior, smart idle and all wakeups
 311          * REVISIT: some wakeups may be unnecessary
 312          */
 313         if (cpu_is_omap34xx()) {
 314                 u16 syscon;
 315
 316                 syscon = OMAP_MCBSP_READ(mcbsp->io_base, SYSCON);
 317                 syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
 318
 319                 if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) {
 320                         syscon |= (ENAWAKEUP | SIDLEMODE(0x02) |
 321                                         CLOCKACTIVITY(0x02));
 322                         OMAP_MCBSP_WRITE(mcbsp->io_base, WAKEUPEN,
 323                                         XRDYEN | RRDYEN);
 324                 } else {
 325                         syscon |= SIDLEMODE(0x01);
 326                 }
 327
 328                 OMAP_MCBSP_WRITE(mcbsp->io_base, SYSCON, syscon);
 329         }
 330 }
 331
 332 static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp)
 333 {
 334         /*
 335          * Disable wakup behavior, smart idle and all wakeups
 336          */
 337         if (cpu_is_omap34xx()) {
 338                 u16 syscon;
 339
 340                 syscon = OMAP_MCBSP_READ(mcbsp->io_base, SYSCON);
 341                 syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
 342                 /*
 343                  * HW bug workaround - If no_idle mode is taken, we need to
 344                  * go to smart_idle before going to always_idle, or the
 345                  * device will not hit retention anymore.
 346                  */
 347                 syscon |= SIDLEMODE(0x02);
 348                 OMAP_MCBSP_WRITE(mcbsp->io_base, SYSCON, syscon);
 349
 350                 syscon &= ~(SIDLEMODE(0x03));
 351                 OMAP_MCBSP_WRITE(mcbsp->io_base, SYSCON, syscon);
 352
 353                 OMAP_MCBSP_WRITE(mcbsp->io_base, WAKEUPEN, 0);
 354         }
 355 }
 356 #else
 357 static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp) {}
 358 static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp) {}
 359 #endif
 360
 361 /*
 362  * We can choose between IRQ based or polled IO.
 363  * This needs to be called before omap_mcbsp_request().
 364  */
 365 int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type)
 366 {
 367         struct omap_mcbsp *mcbsp;
 368
 369         if (!omap_mcbsp_check_valid_id(id)) {
 370                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 371                 return -ENODEV;
 372         }
 373         mcbsp = id_to_mcbsp_ptr(id);
 374
 375         spin_lock(&mcbsp->lock);
 376
 377         if (!mcbsp->free) {
 378                 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
 379                         mcbsp->id);
 380                 spin_unlock(&mcbsp->lock);
 381                 return -EINVAL;
 382         }
 383
 384         mcbsp->io_type = io_type;
 385
 386         spin_unlock(&mcbsp->lock);
 387
 388         return 0;
 389 }
 390 EXPORT_SYMBOL(omap_mcbsp_set_io_type);
 391
 392 int omap_mcbsp_request(unsigned int id)
 393 {
 394         struct omap_mcbsp *mcbsp;
 395         int err;
 396
 397         if (!omap_mcbsp_check_valid_id(id)) {
 398                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 399                 return -ENODEV;
 400         }
 401         mcbsp = id_to_mcbsp_ptr(id);
 402
 403         spin_lock(&mcbsp->lock);
 404         if (!mcbsp->free) {
 405                 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
 406                         mcbsp->id);
 407                 spin_unlock(&mcbsp->lock);
 408                 return -EBUSY;
 409         }
 410
 411         mcbsp->free = 0;
 412         spin_unlock(&mcbsp->lock);
 413
 414         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
 415                 mcbsp->pdata->ops->request(id);
 416
 417         clk_enable(mcbsp->iclk);
 418         clk_enable(mcbsp->fclk);
 419
 420         /* Do procedure specific to omap34xx arch, if applicable */
 421         omap34xx_mcbsp_request(mcbsp);
 422
 423         /*
 424          * Make sure that transmitter, receiver and sample-rate generator are
 425          * not running before activating IRQs.
 426          */
 427         OMAP_MCBSP_WRITE(mcbsp->io_base, SPCR1, 0);
 428         OMAP_MCBSP_WRITE(mcbsp->io_base, SPCR2, 0);
 429
 430         if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
 431                 /* We need to get IRQs here */
 432                 init_completion(&mcbsp->tx_irq_completion);
 433                 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler,
 434                                         0, "McBSP", (void *)mcbsp);
 435                 if (err != 0) {
 436                         dev_err(mcbsp->dev, "Unable to request TX IRQ %d "
 437                                         "for McBSP%d\n", mcbsp->tx_irq,
 438                                         mcbsp->id);
 439                         goto error;
 440                 }
 441
 442                 init_completion(&mcbsp->rx_irq_completion);
 443                 err = request_irq(mcbsp->rx_irq, omap_mcbsp_rx_irq_handler,
 444                                         0, "McBSP", (void *)mcbsp);
 445                 if (err != 0) {
 446                         dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
 447                                         "for McBSP%d\n", mcbsp->rx_irq,
 448                                         mcbsp->id);
 449                         goto tx_irq;
 450                 }
 451         }
 452
 453         return 0;
 454 tx_irq:
 455         free_irq(mcbsp->tx_irq, (void *)mcbsp);
 456 error:
 457         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
 458                         mcbsp->pdata->ops->free(id);
 459
 460         /* Do procedure specific to omap34xx arch, if applicable */
 461         omap34xx_mcbsp_free(mcbsp);
 462
 463         clk_disable(mcbsp->fclk);
 464         clk_disable(mcbsp->iclk);
 465
 466         mcbsp->free = 1;
 467
 468         return err;
 469 }
 470 EXPORT_SYMBOL(omap_mcbsp_request);
 471
 472 void omap_mcbsp_free(unsigned int id)
 473 {
 474         struct omap_mcbsp *mcbsp;
 475
 476         if (!omap_mcbsp_check_valid_id(id)) {
 477                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 478                 return;
 479         }
 480         mcbsp = id_to_mcbsp_ptr(id);
 481
 482         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
 483                 mcbsp->pdata->ops->free(id);
 484
 485         /* Do procedure specific to omap34xx arch, if applicable */
 486         omap34xx_mcbsp_free(mcbsp);
 487
 488         clk_disable(mcbsp->fclk);
 489         clk_disable(mcbsp->iclk);
 490
 491         if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
 492                 /* Free IRQs */
 493                 free_irq(mcbsp->rx_irq, (void *)mcbsp);
 494                 free_irq(mcbsp->tx_irq, (void *)mcbsp);
 495         }
 496
 497         spin_lock(&mcbsp->lock);
 498         if (mcbsp->free) {
 499                 dev_err(mcbsp->dev, "McBSP%d was not reserved\n",
 500                         mcbsp->id);
 501                 spin_unlock(&mcbsp->lock);
 502                 return;
 503         }
 504
 505         mcbsp->free = 1;
 506         spin_unlock(&mcbsp->lock);
 507 }
 508 EXPORT_SYMBOL(omap_mcbsp_free);
 509
 510 /*
 511  * Here we start the McBSP, by enabling transmitter, receiver or both.
 512  * If no transmitter or receiver is active prior calling, then sample-rate
 513  * generator and frame sync are started.
 514  */
 515 void omap_mcbsp_start(unsigned int id, int tx, int rx)
 516 {
 517         struct omap_mcbsp *mcbsp;
 518         void __iomem *io_base;
 519         int idle;
 520         u16 w;
 521
 522         if (!omap_mcbsp_check_valid_id(id)) {
 523                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 524                 return;
 525         }
 526         mcbsp = id_to_mcbsp_ptr(id);
 527         io_base = mcbsp->io_base;
 528
 529         mcbsp->rx_word_length = (OMAP_MCBSP_READ(io_base, RCR1) >> 5) & 0x7;
 530         mcbsp->tx_word_length = (OMAP_MCBSP_READ(io_base, XCR1) >> 5) & 0x7;
 531
 532         idle = !((OMAP_MCBSP_READ(io_base, SPCR2) |
 533                   OMAP_MCBSP_READ(io_base, SPCR1)) & 1);
 534
 535         if (idle) {
 536                 /* Start the sample generator */
 537                 w = OMAP_MCBSP_READ(io_base, SPCR2);
 538                 OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 6));
 539         }
 540
 541         /* Enable transmitter and receiver */
 542         tx &= 1;
 543         w = OMAP_MCBSP_READ(io_base, SPCR2);
 544         OMAP_MCBSP_WRITE(io_base, SPCR2, w | tx);
 545
 546         rx &= 1;
 547         w = OMAP_MCBSP_READ(io_base, SPCR1);
 548         OMAP_MCBSP_WRITE(io_base, SPCR1, w | rx);
 549
 550         /*
 551          * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
 552          * REVISIT: 100us may give enough time for two CLKSRG, however
 553          * due to some unknown PM related, clock gating etc. reason it
 554          * is now at 500us.
 555          */
 556         udelay(500);
 557
 558         if (idle) {
 559                 /* Start frame sync */
 560                 w = OMAP_MCBSP_READ(io_base, SPCR2);
 561                 OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 7));
 562         }
 563
 564         if (cpu_is_omap2430() || cpu_is_omap34xx()) {
 565                 /* Release the transmitter and receiver */
 566                 w = OMAP_MCBSP_READ(io_base, XCCR);
 567                 w &= ~(tx ? XDISABLE : 0);
 568                 OMAP_MCBSP_WRITE(io_base, XCCR, w);
 569                 w = OMAP_MCBSP_READ(io_base, RCCR);
 570                 w &= ~(rx ? RDISABLE : 0);
 571                 OMAP_MCBSP_WRITE(io_base, RCCR, w);
 572         }
 573
 574         /* Dump McBSP Regs */
 575         omap_mcbsp_dump_reg(id);
 576 }
 577 EXPORT_SYMBOL(omap_mcbsp_start);
 578
 579 void omap_mcbsp_stop(unsigned int id, int tx, int rx)
 580 {
 581         struct omap_mcbsp *mcbsp;
 582         void __iomem *io_base;
 583         int idle;
 584         u16 w;
 585
 586         if (!omap_mcbsp_check_valid_id(id)) {
 587                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 588                 return;
 589         }
 590
 591         mcbsp = id_to_mcbsp_ptr(id);
 592         io_base = mcbsp->io_base;
 593
 594         /* Reset transmitter */
 595         tx &= 1;
 596         if (cpu_is_omap2430() || cpu_is_omap34xx()) {
 597                 w = OMAP_MCBSP_READ(io_base, XCCR);
 598                 w |= (tx ? XDISABLE : 0);
 599                 OMAP_MCBSP_WRITE(io_base, XCCR, w);
 600         }
 601         w = OMAP_MCBSP_READ(io_base, SPCR2);
 602         OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~tx);
 603
 604         /* Reset receiver */
 605         rx &= 1;
 606         if (cpu_is_omap2430() || cpu_is_omap34xx()) {
 607                 w = OMAP_MCBSP_READ(io_base, RCCR);
 608                 w |= (rx ? RDISABLE : 0);
 609                 OMAP_MCBSP_WRITE(io_base, RCCR, w);
 610         }
 611         w = OMAP_MCBSP_READ(io_base, SPCR1);
 612         OMAP_MCBSP_WRITE(io_base, SPCR1, w & ~rx);
 613
 614         idle = !((OMAP_MCBSP_READ(io_base, SPCR2) |
 615                   OMAP_MCBSP_READ(io_base, SPCR1)) & 1);
 616
 617         if (idle) {
 618                 /* Reset the sample rate generator */
 619                 w = OMAP_MCBSP_READ(io_base, SPCR2);
 620                 OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1 << 6));
 621         }
 622 }
 623 EXPORT_SYMBOL(omap_mcbsp_stop);
 624
 625 /* polled mcbsp i/o operations */
 626 int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
 627 {
 628         struct omap_mcbsp *mcbsp;
 629         void __iomem *base;
 630
 631         if (!omap_mcbsp_check_valid_id(id)) {
 632                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 633                 return -ENODEV;
 634         }
 635
 636         mcbsp = id_to_mcbsp_ptr(id);
 637         base = mcbsp->io_base;
 638
 639         writew(buf, base + OMAP_MCBSP_REG_DXR1);
 640         /* if frame sync error - clear the error */
 641         if (readw(base + OMAP_MCBSP_REG_SPCR2) & XSYNC_ERR) {
 642                 /* clear error */
 643                 writew(readw(base + OMAP_MCBSP_REG_SPCR2) & (~XSYNC_ERR),
 644                        base + OMAP_MCBSP_REG_SPCR2);
 645                 /* resend */
 646                 return -1;
 647         } else {
 648                 /* wait for transmit confirmation */
 649                 int attemps = 0;
 650                 while (!(readw(base + OMAP_MCBSP_REG_SPCR2) & XRDY)) {
 651                         if (attemps++ > 1000) {
 652                                 writew(readw(base + OMAP_MCBSP_REG_SPCR2) &
 653                                        (~XRST),
 654                                        base + OMAP_MCBSP_REG_SPCR2);
 655                                 udelay(10);
 656                                 writew(readw(base + OMAP_MCBSP_REG_SPCR2) |
 657                                        (XRST),
 658                                        base + OMAP_MCBSP_REG_SPCR2);
 659                                 udelay(10);
 660                                 dev_err(mcbsp->dev, "Could not write to"
 661                                         " McBSP%d Register\n", mcbsp->id);
 662                                 return -2;
 663                         }
 664                 }
 665         }
 666
 667         return 0;
 668 }
 669 EXPORT_SYMBOL(omap_mcbsp_pollwrite);
 670
 671 int omap_mcbsp_pollread(unsigned int id, u16 *buf)
 672 {
 673         struct omap_mcbsp *mcbsp;
 674         void __iomem *base;
 675
 676         if (!omap_mcbsp_check_valid_id(id)) {
 677                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 678                 return -ENODEV;
 679         }
 680         mcbsp = id_to_mcbsp_ptr(id);
 681
 682         base = mcbsp->io_base;
 683         /* if frame sync error - clear the error */
 684         if (readw(base + OMAP_MCBSP_REG_SPCR1) & RSYNC_ERR) {
 685                 /* clear error */
 686                 writew(readw(base + OMAP_MCBSP_REG_SPCR1) & (~RSYNC_ERR),
 687                        base + OMAP_MCBSP_REG_SPCR1);
 688                 /* resend */
 689                 return -1;
 690         } else {
 691                 /* wait for recieve confirmation */
 692                 int attemps = 0;
 693                 while (!(readw(base + OMAP_MCBSP_REG_SPCR1) & RRDY)) {
 694                         if (attemps++ > 1000) {
 695                                 writew(readw(base + OMAP_MCBSP_REG_SPCR1) &
 696                                        (~RRST),
 697                                        base + OMAP_MCBSP_REG_SPCR1);
 698                                 udelay(10);
 699                                 writew(readw(base + OMAP_MCBSP_REG_SPCR1) |
 700                                        (RRST),
 701                                        base + OMAP_MCBSP_REG_SPCR1);
 702                                 udelay(10);
 703                                 dev_err(mcbsp->dev, "Could not read from"
 704                                         " McBSP%d Register\n", mcbsp->id);
 705                                 return -2;
 706                         }
 707                 }
 708         }
 709         *buf = readw(base + OMAP_MCBSP_REG_DRR1);
 710
 711         return 0;
 712 }
 713 EXPORT_SYMBOL(omap_mcbsp_pollread);
 714
 715 /*
 716  * IRQ based word transmission.
 717  */
 718 void omap_mcbsp_xmit_word(unsigned int id, u32 word)
 719 {
 720         struct omap_mcbsp *mcbsp;
 721         void __iomem *io_base;
 722         omap_mcbsp_word_length word_length;
 723
 724         if (!omap_mcbsp_check_valid_id(id)) {
 725                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 726                 return;
 727         }
 728
 729         mcbsp = id_to_mcbsp_ptr(id);
 730         io_base = mcbsp->io_base;
 731         word_length = mcbsp->tx_word_length;
 732
 733         wait_for_completion(&mcbsp->tx_irq_completion);
 734
 735         if (word_length > OMAP_MCBSP_WORD_16)
 736                 OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16);
 737         OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff);
 738 }
 739 EXPORT_SYMBOL(omap_mcbsp_xmit_word);
 740
 741 u32 omap_mcbsp_recv_word(unsigned int id)
 742 {
 743         struct omap_mcbsp *mcbsp;
 744         void __iomem *io_base;
 745         u16 word_lsb, word_msb = 0;
 746         omap_mcbsp_word_length word_length;
 747
 748         if (!omap_mcbsp_check_valid_id(id)) {
 749                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 750                 return -ENODEV;
 751         }
 752         mcbsp = id_to_mcbsp_ptr(id);
 753
 754         word_length = mcbsp->rx_word_length;
 755         io_base = mcbsp->io_base;
 756
 757         wait_for_completion(&mcbsp->rx_irq_completion);
 758
 759         if (word_length > OMAP_MCBSP_WORD_16)
 760                 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
 761         word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
 762
 763         return (word_lsb | (word_msb << 16));
 764 }
 765 EXPORT_SYMBOL(omap_mcbsp_recv_word);
 766
 767 int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
 768 {
 769         struct omap_mcbsp *mcbsp;
 770         void __iomem *io_base;
 771         omap_mcbsp_word_length tx_word_length;
 772         omap_mcbsp_word_length rx_word_length;
 773         u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
 774
 775         if (!omap_mcbsp_check_valid_id(id)) {
 776                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 777                 return -ENODEV;
 778         }
 779         mcbsp = id_to_mcbsp_ptr(id);
 780         io_base = mcbsp->io_base;
 781         tx_word_length = mcbsp->tx_word_length;
 782         rx_word_length = mcbsp->rx_word_length;
 783
 784         if (tx_word_length != rx_word_length)
 785                 return -EINVAL;
 786
 787         /* First we wait for the transmitter to be ready */
 788         spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
 789         while (!(spcr2 & XRDY)) {
 790                 spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
 791                 if (attempts++ > 1000) {
 792                         /* We must reset the transmitter */
 793                         OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 & (~XRST));
 794                         udelay(10);
 795                         OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
 796                         udelay(10);
 797                         dev_err(mcbsp->dev, "McBSP%d transmitter not "
 798                                 "ready\n", mcbsp->id);
 799                         return -EAGAIN;
 800                 }
 801         }
 802
 803         /* Now we can push the data */
 804         if (tx_word_length > OMAP_MCBSP_WORD_16)
 805                 OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16);
 806         OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff);
 807
 808         /* We wait for the receiver to be ready */
 809         spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
 810         while (!(spcr1 & RRDY)) {
 811                 spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
 812                 if (attempts++ > 1000) {
 813                         /* We must reset the receiver */
 814                         OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 & (~RRST));
 815                         udelay(10);
 816                         OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
 817                         udelay(10);
 818                         dev_err(mcbsp->dev, "McBSP%d receiver not "
 819                                 "ready\n", mcbsp->id);
 820                         return -EAGAIN;
 821                 }
 822         }
 823
 824         /* Receiver is ready, let's read the dummy data */
 825         if (rx_word_length > OMAP_MCBSP_WORD_16)
 826                 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
 827         word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
 828
 829         return 0;
 830 }
 831 EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll);
 832
 833 int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
 834 {
 835         struct omap_mcbsp *mcbsp;
 836         u32 clock_word = 0;
 837         void __iomem *io_base;
 838         omap_mcbsp_word_length tx_word_length;
 839         omap_mcbsp_word_length rx_word_length;
 840         u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
 841
 842         if (!omap_mcbsp_check_valid_id(id)) {
 843                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 844                 return -ENODEV;
 845         }
 846
 847         mcbsp = id_to_mcbsp_ptr(id);
 848         io_base = mcbsp->io_base;
 849
 850         tx_word_length = mcbsp->tx_word_length;
 851         rx_word_length = mcbsp->rx_word_length;
 852
 853         if (tx_word_length != rx_word_length)
 854                 return -EINVAL;
 855
 856         /* First we wait for the transmitter to be ready */
 857         spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
 858         while (!(spcr2 & XRDY)) {
 859                 spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
 860                 if (attempts++ > 1000) {
 861                         /* We must reset the transmitter */
 862                         OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 & (~XRST));
 863                         udelay(10);
 864                         OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
 865                         udelay(10);
 866                         dev_err(mcbsp->dev, "McBSP%d transmitter not "
 867                                 "ready\n", mcbsp->id);
 868                         return -EAGAIN;
 869                 }
 870         }
 871
 872         /* We first need to enable the bus clock */
 873         if (tx_word_length > OMAP_MCBSP_WORD_16)
 874                 OMAP_MCBSP_WRITE(io_base, DXR2, clock_word >> 16);
 875         OMAP_MCBSP_WRITE(io_base, DXR1, clock_word & 0xffff);
 876
 877         /* We wait for the receiver to be ready */
 878         spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
 879         while (!(spcr1 & RRDY)) {
 880                 spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
 881                 if (attempts++ > 1000) {
 882                         /* We must reset the receiver */
 883                         OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 & (~RRST));
 884                         udelay(10);
 885                         OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
 886                         udelay(10);
 887                         dev_err(mcbsp->dev, "McBSP%d receiver not "
 888                                 "ready\n", mcbsp->id);
 889                         return -EAGAIN;
 890                 }
 891         }
 892
 893         /* Receiver is ready, there is something for us */
 894         if (rx_word_length > OMAP_MCBSP_WORD_16)
 895                 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
 896         word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
 897
 898         word[0] = (word_lsb | (word_msb << 16));
 899
 900         return 0;
 901 }
 902 EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll);
 903
 904 /*
 905  * Simple DMA based buffer rx/tx routines.
 906  * Nothing fancy, just a single buffer tx/rx through DMA.
 907  * The DMA resources are released once the transfer is done.
 908  * For anything fancier, you should use your own customized DMA
 909  * routines and callbacks.
 910  */
 911 int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer,
 912                                 unsigned int length)
 913 {
 914         struct omap_mcbsp *mcbsp;
 915         int dma_tx_ch;
 916         int src_port = 0;
 917         int dest_port = 0;
 918         int sync_dev = 0;
 919
 920         if (!omap_mcbsp_check_valid_id(id)) {
 921                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 922                 return -ENODEV;
 923         }
 924         mcbsp = id_to_mcbsp_ptr(id);
 925
 926         if (omap_request_dma(mcbsp->dma_tx_sync, "McBSP TX",
 927                                 omap_mcbsp_tx_dma_callback,
 928                                 mcbsp,
 929                                 &dma_tx_ch)) {
 930                 dev_err(mcbsp->dev, " Unable to request DMA channel for "
 931                                 "McBSP%d TX. Trying IRQ based TX\n",
 932                                 mcbsp->id);
 933                 return -EAGAIN;
 934         }
 935         mcbsp->dma_tx_lch = dma_tx_ch;
 936
 937         dev_err(mcbsp->dev, "McBSP%d TX DMA on channel %d\n", mcbsp->id,
 938                 dma_tx_ch);
 939
 940         init_completion(&mcbsp->tx_dma_completion);
 941
 942         if (cpu_class_is_omap1()) {
 943                 src_port = OMAP_DMA_PORT_TIPB;
 944                 dest_port = OMAP_DMA_PORT_EMIFF;
 945         }
 946         if (cpu_class_is_omap2())
 947                 sync_dev = mcbsp->dma_tx_sync;
 948
 949         omap_set_dma_transfer_params(mcbsp->dma_tx_lch,
 950                                      OMAP_DMA_DATA_TYPE_S16,
 951                                      length >> 1, 1,
 952                                      OMAP_DMA_SYNC_ELEMENT,
 953          sync_dev, 0);
 954
 955         omap_set_dma_dest_params(mcbsp->dma_tx_lch,
 956                                  src_port,
 957                                  OMAP_DMA_AMODE_CONSTANT,
 958                                  mcbsp->phys_base + OMAP_MCBSP_REG_DXR1,
 959                                  0, 0);
 960
 961         omap_set_dma_src_params(mcbsp->dma_tx_lch,
 962                                 dest_port,
 963                                 OMAP_DMA_AMODE_POST_INC,
 964                                 buffer,
 965                                 0, 0);
 966
 967         omap_start_dma(mcbsp->dma_tx_lch);
 968         wait_for_completion(&mcbsp->tx_dma_completion);
 969
 970         return 0;
 971 }
 972 EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
 973
 974 int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer,
 975                                 unsigned int length)
 976 {
 977         struct omap_mcbsp *mcbsp;
 978         int dma_rx_ch;
 979         int src_port = 0;
 980         int dest_port = 0;
 981         int sync_dev = 0;
 982
 983         if (!omap_mcbsp_check_valid_id(id)) {
 984                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 985                 return -ENODEV;
 986         }
 987         mcbsp = id_to_mcbsp_ptr(id);
 988
 989         if (omap_request_dma(mcbsp->dma_rx_sync, "McBSP RX",
 990                                 omap_mcbsp_rx_dma_callback,
 991                                 mcbsp,
 992                                 &dma_rx_ch)) {
 993                 dev_err(mcbsp->dev, "Unable to request DMA channel for "
 994                                 "McBSP%d RX. Trying IRQ based RX\n",
 995                                 mcbsp->id);
 996                 return -EAGAIN;
 997         }
 998         mcbsp->dma_rx_lch = dma_rx_ch;
 999
1000         dev_err(mcbsp->dev, "McBSP%d RX DMA on channel %d\n", mcbsp->id,
1001                 dma_rx_ch);
1002
1003         init_completion(&mcbsp->rx_dma_completion);
1004
1005         if (cpu_class_is_omap1()) {
1006                 src_port = OMAP_DMA_PORT_TIPB;
1007                 dest_port = OMAP_DMA_PORT_EMIFF;
1008         }
1009         if (cpu_class_is_omap2())
1010                 sync_dev = mcbsp->dma_rx_sync;
1011
1012         omap_set_dma_transfer_params(mcbsp->dma_rx_lch,
1013                                         OMAP_DMA_DATA_TYPE_S16,
1014                                         length >> 1, 1,
1015                                         OMAP_DMA_SYNC_ELEMENT,
1016                                         sync_dev, 0);
1017
1018         omap_set_dma_src_params(mcbsp->dma_rx_lch,
1019                                 src_port,
1020                                 OMAP_DMA_AMODE_CONSTANT,
1021                                 mcbsp->phys_base + OMAP_MCBSP_REG_DRR1,
1022                                 0, 0);
1023
1024         omap_set_dma_dest_params(mcbsp->dma_rx_lch,
1025                                         dest_port,
1026                                         OMAP_DMA_AMODE_POST_INC,
1027                                         buffer,
1028                                         0, 0);
1029
1030         omap_start_dma(mcbsp->dma_rx_lch);
1031         wait_for_completion(&mcbsp->rx_dma_completion);
1032
1033         return 0;
1034 }
1035 EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
1036
1037 /*
1038  * SPI wrapper.
1039  * Since SPI setup is much simpler than the generic McBSP one,
1040  * this wrapper just need an omap_mcbsp_spi_cfg structure as an input.
1041  * Once this is done, you can call omap_mcbsp_start().
1042  */
1043 void omap_mcbsp_set_spi_mode(unsigned int id,
1044                                 const struct omap_mcbsp_spi_cfg *spi_cfg)
1045 {
1046         struct omap_mcbsp *mcbsp;
1047         struct omap_mcbsp_reg_cfg mcbsp_cfg;
1048
1049         if (!omap_mcbsp_check_valid_id(id)) {
1050                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1051                 return;
1052         }
1053         mcbsp = id_to_mcbsp_ptr(id);
1054
1055         memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg));
1056
1057         /* SPI has only one frame */
1058         mcbsp_cfg.rcr1 |= (RWDLEN1(spi_cfg->word_length) | RFRLEN1(0));
1059         mcbsp_cfg.xcr1 |= (XWDLEN1(spi_cfg->word_length) | XFRLEN1(0));
1060
1061         /* Clock stop mode */
1062         if (spi_cfg->clk_stp_mode == OMAP_MCBSP_CLK_STP_MODE_NO_DELAY)
1063                 mcbsp_cfg.spcr1 |= (1 << 12);
1064         else
1065                 mcbsp_cfg.spcr1 |= (3 << 11);
1066
1067         /* Set clock parities */
1068         if (spi_cfg->rx_clock_polarity == OMAP_MCBSP_CLK_RISING)
1069                 mcbsp_cfg.pcr0 |= CLKRP;
1070         else
1071                 mcbsp_cfg.pcr0 &= ~CLKRP;
1072
1073         if (spi_cfg->tx_clock_polarity == OMAP_MCBSP_CLK_RISING)
1074                 mcbsp_cfg.pcr0 &= ~CLKXP;
1075         else
1076                 mcbsp_cfg.pcr0 |= CLKXP;
1077
1078         /* Set SCLKME to 0 and CLKSM to 1 */
1079         mcbsp_cfg.pcr0 &= ~SCLKME;
1080         mcbsp_cfg.srgr2 |= CLKSM;
1081
1082         /* Set FSXP */
1083         if (spi_cfg->fsx_polarity == OMAP_MCBSP_FS_ACTIVE_HIGH)
1084                 mcbsp_cfg.pcr0 &= ~FSXP;
1085         else
1086                 mcbsp_cfg.pcr0 |= FSXP;
1087
1088         if (spi_cfg->spi_mode == OMAP_MCBSP_SPI_MASTER) {
1089                 mcbsp_cfg.pcr0 |= CLKXM;
1090                 mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div - 1);
1091                 mcbsp_cfg.pcr0 |= FSXM;
1092                 mcbsp_cfg.srgr2 &= ~FSGM;
1093                 mcbsp_cfg.xcr2 |= XDATDLY(1);
1094                 mcbsp_cfg.rcr2 |= RDATDLY(1);
1095         } else {
1096                 mcbsp_cfg.pcr0 &= ~CLKXM;
1097                 mcbsp_cfg.srgr1 |= CLKGDV(1);
1098                 mcbsp_cfg.pcr0 &= ~FSXM;
1099                 mcbsp_cfg.xcr2 &= ~XDATDLY(3);
1100                 mcbsp_cfg.rcr2 &= ~RDATDLY(3);
1101         }
1102
1103         mcbsp_cfg.xcr2 &= ~XPHASE;
1104         mcbsp_cfg.rcr2 &= ~RPHASE;
1105
1106         omap_mcbsp_config(id, &mcbsp_cfg);
1107 }
1108 EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);
1109
1110 #ifdef CONFIG_ARCH_OMAP34XX
1111 #define max_thres(m)                    (mcbsp->pdata->buffer_size)
1112 #define valid_threshold(m, val)         ((val) <= max_thres(m))
1113 #define THRESHOLD_PROP_BUILDER(prop)                                    \
1114 static ssize_t prop##_show(struct device *dev,                          \
1115                         struct device_attribute *attr, char *buf)       \
1116 {                                                                       \
1117         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);                \
1118                                                                         \
1119         return sprintf(buf, "%u\n", mcbsp->prop);                       \
1120 }                                                                       \
1121                                                                         \
1122 static ssize_t prop##_store(struct device *dev,                         \
1123                                 struct device_attribute *attr,          \
1124                                 const char *buf, size_t size)           \
1125 {                                                                       \
1126         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);                \
1127         unsigned long val;                                              \
1128         int status;                                                     \
1129                                                                         \
1130         status = strict_strtoul(buf, 0, &val);                          \
1131         if (status)                                                     \
1132                 return status;                                          \
1133                                                                         \
1134         if (!valid_threshold(mcbsp, val))                               \
1135                 return -EDOM;                                           \
1136                                                                         \
1137         mcbsp->prop = val;                                              \
1138         return size;                                                    \
1139 }                                                                       \
1140                                                                         \
1141 static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store);
1142
1143 THRESHOLD_PROP_BUILDER(max_tx_thres);
1144 THRESHOLD_PROP_BUILDER(max_rx_thres);
1145
1146 static const char *dma_op_modes[] = {
1147         "element", "threshold", "frame",
1148 };
1149
1150 static ssize_t dma_op_mode_show(struct device *dev,
1151                         struct device_attribute *attr, char *buf)
1152 {
1153         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1154         int dma_op_mode, i = 0;
1155         ssize_t len = 0;
1156         const char * const *s;
1157
1158         dma_op_mode = mcbsp->dma_op_mode;
1159
1160         for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) {
1161                 if (dma_op_mode == i)
1162                         len += sprintf(buf + len, "[%s] ", *s);
1163                 else
1164                         len += sprintf(buf + len, "%s ", *s);
1165         }
1166         len += sprintf(buf + len, "\n");
1167
1168         return len;
1169 }
1170
1171 static ssize_t dma_op_mode_store(struct device *dev,
1172                                 struct device_attribute *attr,
1173                                 const char *buf, size_t size)
1174 {
1175         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1176         const char * const *s;
1177         int i = 0;
1178
1179         for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++)
1180                 if (sysfs_streq(buf, *s))
1181                         break;
1182
1183         if (i == ARRAY_SIZE(dma_op_modes))
1184                 return -EINVAL;
1185
1186         spin_lock_irq(&mcbsp->lock);
1187         if (!mcbsp->free) {
1188                 size = -EBUSY;
1189                 goto unlock;
1190         }
1191         mcbsp->dma_op_mode = i;
1192
1193 unlock:
1194         spin_unlock_irq(&mcbsp->lock);
1195
1196         return size;
1197 }
1198
1199 static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store);
1200
1201 static const struct attribute *additional_attrs[] = {
1202         &dev_attr_max_tx_thres.attr,
1203         &dev_attr_max_rx_thres.attr,
1204         &dev_attr_dma_op_mode.attr,
1205         NULL,
1206 };
1207
1208 static const struct attribute_group additional_attr_group = {
1209         .attrs = (struct attribute **)additional_attrs,
1210 };
1211
1212 static inline int __devinit omap_additional_add(struct device *dev)
1213 {
1214         return sysfs_create_group(&dev->kobj, &additional_attr_group);
1215 }
1216
1217 static inline void __devexit omap_additional_remove(struct device *dev)
1218 {
1219         sysfs_remove_group(&dev->kobj, &additional_attr_group);
1220 }
1221
1222 static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp)
1223 {
1224         mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
1225         if (cpu_is_omap34xx()) {
1226                 mcbsp->max_tx_thres = max_thres(mcbsp);
1227                 mcbsp->max_rx_thres = max_thres(mcbsp);
1228                 /*
1229                  * REVISIT: Set dmap_op_mode to THRESHOLD as default
1230                  * for mcbsp2 instances.
1231                  */
1232                 if (omap_additional_add(mcbsp->dev))
1233                         dev_warn(mcbsp->dev,
1234                                 "Unable to create additional controls\n");
1235         } else {
1236                 mcbsp->max_tx_thres = -EINVAL;
1237                 mcbsp->max_rx_thres = -EINVAL;
1238         }
1239 }
1240
1241 static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp)
1242 {
1243         if (cpu_is_omap34xx())
1244                 omap_additional_remove(mcbsp->dev);
1245 }
1246 #else
1247 static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp) {}
1248 static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp) {}
1249 #endif /* CONFIG_ARCH_OMAP34XX */
1250
1251 /*
1252  * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
1253  * 730 has only 2 McBSP, and both of them are MPU peripherals.
1254  */
1255 static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
1256 {
1257         struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data;
1258         struct omap_mcbsp *mcbsp;
1259         int id = pdev->id - 1;
1260         int ret = 0;
1261
1262         if (!pdata) {
1263                 dev_err(&pdev->dev, "McBSP device initialized without"
1264                                 "platform data\n");
1265                 ret = -EINVAL;
1266                 goto exit;
1267         }
1268
1269         dev_dbg(&pdev->dev, "Initializing OMAP McBSP (%d).\n", pdev->id);
1270
1271         if (id >= omap_mcbsp_count) {
1272                 dev_err(&pdev->dev, "Invalid McBSP device id (%d)\n", id);
1273                 ret = -EINVAL;
1274                 goto exit;
1275         }
1276
1277         mcbsp = kzalloc(sizeof(struct omap_mcbsp), GFP_KERNEL);
1278         if (!mcbsp) {
1279                 ret = -ENOMEM;
1280                 goto exit;
1281         }
1282
1283         spin_lock_init(&mcbsp->lock);
1284         mcbsp->id = id + 1;
1285         mcbsp->free = 1;
1286         mcbsp->dma_tx_lch = -1;
1287         mcbsp->dma_rx_lch = -1;
1288
1289         mcbsp->phys_base = pdata->phys_base;
1290         mcbsp->io_base = ioremap(pdata->phys_base, SZ_4K);
1291         if (!mcbsp->io_base) {
1292                 ret = -ENOMEM;
1293                 goto err_ioremap;
1294         }
1295
1296         /* Default I/O is IRQ based */
1297         mcbsp->io_type = OMAP_MCBSP_IRQ_IO;
1298         mcbsp->tx_irq = pdata->tx_irq;
1299         mcbsp->rx_irq = pdata->rx_irq;
1300         mcbsp->dma_rx_sync = pdata->dma_rx_sync;
1301         mcbsp->dma_tx_sync = pdata->dma_tx_sync;
1302
1303         mcbsp->iclk = clk_get(&pdev->dev, "ick");
1304         if (IS_ERR(mcbsp->iclk)) {
1305                 ret = PTR_ERR(mcbsp->iclk);
1306                 dev_err(&pdev->dev, "unable to get ick: %d\n", ret);
1307                 goto err_iclk;
1308         }
1309
1310         mcbsp->fclk = clk_get(&pdev->dev, "fck");
1311         if (IS_ERR(mcbsp->fclk)) {
1312                 ret = PTR_ERR(mcbsp->fclk);
1313                 dev_err(&pdev->dev, "unable to get fck: %d\n", ret);
1314                 goto err_fclk;
1315         }
1316
1317         mcbsp->pdata = pdata;
1318         mcbsp->dev = &pdev->dev;
1319         mcbsp_ptr[id] = mcbsp;
1320         platform_set_drvdata(pdev, mcbsp);
1321
1322         /* Initialize mcbsp properties for OMAP34XX if needed / applicable */
1323         omap34xx_device_init(mcbsp);
1324
1325         return 0;
1326
1327 err_fclk:
1328         clk_put(mcbsp->iclk);
1329 err_iclk:
1330         iounmap(mcbsp->io_base);
1331 err_ioremap:
1332         kfree(mcbsp);
1333 exit:
1334         return ret;
1335 }
1336
1337 static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
1338 {
1339         struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
1340
1341         platform_set_drvdata(pdev, NULL);
1342         if (mcbsp) {
1343
1344                 if (mcbsp->pdata && mcbsp->pdata->ops &&
1345                                 mcbsp->pdata->ops->free)
1346                         mcbsp->pdata->ops->free(mcbsp->id);
1347
1348                 omap34xx_device_exit(mcbsp);
1349
1350                 clk_disable(mcbsp->fclk);
1351                 clk_disable(mcbsp->iclk);
1352                 clk_put(mcbsp->fclk);
1353                 clk_put(mcbsp->iclk);
1354
1355                 iounmap(mcbsp->io_base);
1356
1357                 mcbsp->fclk = NULL;
1358                 mcbsp->iclk = NULL;
1359                 mcbsp->free = 0;
1360                 mcbsp->dev = NULL;
1361         }
1362
1363         return 0;
1364 }
1365
1366 static struct platform_driver omap_mcbsp_driver = {
1367         .probe          = omap_mcbsp_probe,
1368         .remove         = __devexit_p(omap_mcbsp_remove),
1369         .driver         = {
1370                 .name   = "omap-mcbsp",
1371         },
1372 };
1373
1374 int __init omap_mcbsp_init(void)
1375 {
1376         /* Register the McBSP driver */
1377         return platform_driver_register(&omap_mcbsp_driver);
1378 }