arch/arm/plat-omap/mcbsp.c

   1 /*
   2  * linux/arch/arm/plat-omap/mcbsp.c
   3  *
   4  * Copyright (C) 2004 Nokia Corporation
   5  * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
   6  *
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * Multichannel mode not supported.
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/init.h>
  17 #include <linux/device.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/wait.h>
  20 #include <linux/completion.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/err.h>
  23 #include <linux/clk.h>
  24 #include <linux/delay.h>
  25 #include <linux/io.h>
  26
  27 #include <mach/dma.h>
  28 #include <mach/mcbsp.h>
  29
  30 struct omap_mcbsp **mcbsp_ptr;
  31 int omap_mcbsp_count;
  32
  33 void omap_mcbsp_write(void __iomem *io_base, u16 reg, u32 val)
  34 {
  35         if (cpu_class_is_omap1() || cpu_is_omap2420())
  36                 __raw_writew((u16)val, io_base + reg);
  37         else
  38                 __raw_writel(val, io_base + reg);
  39 }
  40
  41 int omap_mcbsp_read(void __iomem *io_base, u16 reg)
  42 {
  43         if (cpu_class_is_omap1() || cpu_is_omap2420())
  44                 return __raw_readw(io_base + reg);
  45         else
  46                 return __raw_readl(io_base + reg);
  47 }
  48
  49 #define OMAP_MCBSP_READ(base, reg) \
  50                         omap_mcbsp_read(base, OMAP_MCBSP_REG_##reg)
  51 #define OMAP_MCBSP_WRITE(base, reg, val) \
  52                         omap_mcbsp_write(base, OMAP_MCBSP_REG_##reg, val)
  53
  54 #define omap_mcbsp_check_valid_id(id)   (id < omap_mcbsp_count)
  55 #define id_to_mcbsp_ptr(id)             mcbsp_ptr[id];
  56
  57 static void omap_mcbsp_dump_reg(u8 id)
  58 {
  59         struct omap_mcbsp *mcbsp = id_to_mcbsp_ptr(id);
  60
  61         dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
  62         dev_dbg(mcbsp->dev, "DRR2:  0x%04x\n",
  63                         OMAP_MCBSP_READ(mcbsp->io_base, DRR2));
  64         dev_dbg(mcbsp->dev, "DRR1:  0x%04x\n",
  65                         OMAP_MCBSP_READ(mcbsp->io_base, DRR1));
  66         dev_dbg(mcbsp->dev, "DXR2:  0x%04x\n",
  67                         OMAP_MCBSP_READ(mcbsp->io_base, DXR2));
  68         dev_dbg(mcbsp->dev, "DXR1:  0x%04x\n",
  69                         OMAP_MCBSP_READ(mcbsp->io_base, DXR1));
  70         dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n",
  71                         OMAP_MCBSP_READ(mcbsp->io_base, SPCR2));
  72         dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n",
  73                         OMAP_MCBSP_READ(mcbsp->io_base, SPCR1));
  74         dev_dbg(mcbsp->dev, "RCR2:  0x%04x\n",
  75                         OMAP_MCBSP_READ(mcbsp->io_base, RCR2));
  76         dev_dbg(mcbsp->dev, "RCR1:  0x%04x\n",
  77                         OMAP_MCBSP_READ(mcbsp->io_base, RCR1));
  78         dev_dbg(mcbsp->dev, "XCR2:  0x%04x\n",
  79                         OMAP_MCBSP_READ(mcbsp->io_base, XCR2));
  80         dev_dbg(mcbsp->dev, "XCR1:  0x%04x\n",
  81                         OMAP_MCBSP_READ(mcbsp->io_base, XCR1));
  82         dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n",
  83                         OMAP_MCBSP_READ(mcbsp->io_base, SRGR2));
  84         dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n",
  85                         OMAP_MCBSP_READ(mcbsp->io_base, SRGR1));
  86         dev_dbg(mcbsp->dev, "PCR0:  0x%04x\n",
  87                         OMAP_MCBSP_READ(mcbsp->io_base, PCR0));
  88         dev_dbg(mcbsp->dev, "***********************\n");
  89 }
  90
  91 static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
  92 {
  93         struct omap_mcbsp *mcbsp_tx = dev_id;
  94         u16 irqst_spcr2;
  95
  96         irqst_spcr2 = OMAP_MCBSP_READ(mcbsp_tx->io_base, SPCR2);
  97         dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
  98
  99         if (irqst_spcr2 & XSYNC_ERR) {
 100                 dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n",
 101                         irqst_spcr2);
 102                 /* Writing zero to XSYNC_ERR clears the IRQ */
 103                 OMAP_MCBSP_WRITE(mcbsp_tx->io_base, SPCR2,
 104                         irqst_spcr2 & ~(XSYNC_ERR));
 105         } else {
 106                 complete(&mcbsp_tx->tx_irq_completion);
 107         }
 108
 109         return IRQ_HANDLED;
 110 }
 111
 112 static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
 113 {
 114         struct omap_mcbsp *mcbsp_rx = dev_id;
 115         u16 irqst_spcr1;
 116
 117         irqst_spcr1 = OMAP_MCBSP_READ(mcbsp_rx->io_base, SPCR1);
 118         dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
 119
 120         if (irqst_spcr1 & RSYNC_ERR) {
 121                 dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n",
 122                         irqst_spcr1);
 123                 /* Writing zero to RSYNC_ERR clears the IRQ */
 124                 OMAP_MCBSP_WRITE(mcbsp_rx->io_base, SPCR1,
 125                         irqst_spcr1 & ~(RSYNC_ERR));
 126         } else {
 127                 complete(&mcbsp_rx->tx_irq_completion);
 128         }
 129
 130         return IRQ_HANDLED;
 131 }
 132
 133 static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data)
 134 {
 135         struct omap_mcbsp *mcbsp_dma_tx = data;
 136
 137         dev_dbg(mcbsp_dma_tx->dev, "TX DMA callback : 0x%x\n",
 138                 OMAP_MCBSP_READ(mcbsp_dma_tx->io_base, SPCR2));
 139
 140         /* We can free the channels */
 141         omap_free_dma(mcbsp_dma_tx->dma_tx_lch);
 142         mcbsp_dma_tx->dma_tx_lch = -1;
 143
 144         complete(&mcbsp_dma_tx->tx_dma_completion);
 145 }
 146
 147 static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
 148 {
 149         struct omap_mcbsp *mcbsp_dma_rx = data;
 150
 151         dev_dbg(mcbsp_dma_rx->dev, "RX DMA callback : 0x%x\n",
 152                 OMAP_MCBSP_READ(mcbsp_dma_rx->io_base, SPCR2));
 153
 154         /* We can free the channels */
 155         omap_free_dma(mcbsp_dma_rx->dma_rx_lch);
 156         mcbsp_dma_rx->dma_rx_lch = -1;
 157
 158         complete(&mcbsp_dma_rx->rx_dma_completion);
 159 }
 160
 161 /*
 162  * omap_mcbsp_config simply write a config to the
 163  * appropriate McBSP.
 164  * You either call this function or set the McBSP registers
 165  * by yourself before calling omap_mcbsp_start().
 166  */
 167 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
 168 {
 169         struct omap_mcbsp *mcbsp;
 170         void __iomem *io_base;
 171
 172         if (!omap_mcbsp_check_valid_id(id)) {
 173                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 174                 return;
 175         }
 176         mcbsp = id_to_mcbsp_ptr(id);
 177
 178         io_base = mcbsp->io_base;
 179         dev_dbg(mcbsp->dev, "Configuring McBSP%d  phys_base: 0x%08lx\n",
 180                         mcbsp->id, mcbsp->phys_base);
 181
 182         /* We write the given config */
 183         OMAP_MCBSP_WRITE(io_base, SPCR2, config->spcr2);
 184         OMAP_MCBSP_WRITE(io_base, SPCR1, config->spcr1);
 185         OMAP_MCBSP_WRITE(io_base, RCR2, config->rcr2);
 186         OMAP_MCBSP_WRITE(io_base, RCR1, config->rcr1);
 187         OMAP_MCBSP_WRITE(io_base, XCR2, config->xcr2);
 188         OMAP_MCBSP_WRITE(io_base, XCR1, config->xcr1);
 189         OMAP_MCBSP_WRITE(io_base, SRGR2, config->srgr2);
 190         OMAP_MCBSP_WRITE(io_base, SRGR1, config->srgr1);
 191         OMAP_MCBSP_WRITE(io_base, MCR2, config->mcr2);
 192         OMAP_MCBSP_WRITE(io_base, MCR1, config->mcr1);
 193         OMAP_MCBSP_WRITE(io_base, PCR0, config->pcr0);
 194         if (cpu_is_omap2430() || cpu_is_omap34xx()) {
 195                 OMAP_MCBSP_WRITE(io_base, XCCR, config->xccr);
 196                 OMAP_MCBSP_WRITE(io_base, RCCR, config->rccr);
 197         }
 198 }
 199 EXPORT_SYMBOL(omap_mcbsp_config);
 200
 201 #ifdef CONFIG_ARCH_OMAP34XX
 202 /*
 203  * omap_mcbsp_set_tx_threshold configures how to deal
 204  * with transmit threshold. the threshold value and handler can be
 205  * configure in here.
 206  */
 207 void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
 208 {
 209         struct omap_mcbsp *mcbsp;
 210         void __iomem *io_base;
 211
 212         if (!cpu_is_omap34xx())
 213                 return;
 214
 215         if (!omap_mcbsp_check_valid_id(id)) {
 216                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 217                 return;
 218         }
 219         mcbsp = id_to_mcbsp_ptr(id);
 220         io_base = mcbsp->io_base;
 221
 222         OMAP_MCBSP_WRITE(io_base, THRSH2, threshold);
 223 }
 224 EXPORT_SYMBOL(omap_mcbsp_set_tx_threshold);
 225
 226 /*
 227  * omap_mcbsp_set_rx_threshold configures how to deal
 228  * with receive threshold. the threshold value and handler can be
 229  * configure in here.
 230  */
 231 void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
 232 {
 233         struct omap_mcbsp *mcbsp;
 234         void __iomem *io_base;
 235
 236         if (!cpu_is_omap34xx())
 237                 return;
 238
 239         if (!omap_mcbsp_check_valid_id(id)) {
 240                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 241                 return;
 242         }
 243         mcbsp = id_to_mcbsp_ptr(id);
 244         io_base = mcbsp->io_base;
 245
 246         OMAP_MCBSP_WRITE(io_base, THRSH1, threshold);
 247 }
 248 EXPORT_SYMBOL(omap_mcbsp_set_rx_threshold);
 249
 250 /*
 251  * omap_mcbsp_get_max_tx_thres just return the current configured
 252  * maximum threshold for transmission
 253  */
 254 u16 omap_mcbsp_get_max_tx_threshold(unsigned int id)
 255 {
 256         struct omap_mcbsp *mcbsp;
 257
 258         if (!omap_mcbsp_check_valid_id(id)) {
 259                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 260                 return -ENODEV;
 261         }
 262         mcbsp = id_to_mcbsp_ptr(id);
 263
 264         return mcbsp->max_tx_thres;
 265 }
 266 EXPORT_SYMBOL(omap_mcbsp_get_max_tx_threshold);
 267
 268 /*
 269  * omap_mcbsp_get_max_rx_thres just return the current configured
 270  * maximum threshold for reception
 271  */
 272 u16 omap_mcbsp_get_max_rx_threshold(unsigned int id)
 273 {
 274         struct omap_mcbsp *mcbsp;
 275
 276         if (!omap_mcbsp_check_valid_id(id)) {
 277                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 278                 return -ENODEV;
 279         }
 280         mcbsp = id_to_mcbsp_ptr(id);
 281
 282         return mcbsp->max_rx_thres;
 283 }
 284 EXPORT_SYMBOL(omap_mcbsp_get_max_rx_threshold);
 285
 286 /*
 287  * omap_mcbsp_get_dma_op_mode just return the current configured
 288  * operating mode for the mcbsp channel
 289  */
 290 int omap_mcbsp_get_dma_op_mode(unsigned int id)
 291 {
 292         struct omap_mcbsp *mcbsp;
 293         int dma_op_mode;
 294
 295         if (!omap_mcbsp_check_valid_id(id)) {
 296                 printk(KERN_ERR "%s: Invalid id (%u)\n", __func__, id + 1);
 297                 return -ENODEV;
 298         }
 299         mcbsp = id_to_mcbsp_ptr(id);
 300
 301         spin_lock_irq(&mcbsp->lock);
 302         dma_op_mode = mcbsp->dma_op_mode;
 303         spin_unlock_irq(&mcbsp->lock);
 304
 305         return dma_op_mode;
 306 }
 307 EXPORT_SYMBOL(omap_mcbsp_get_dma_op_mode);
 308
 309 static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp)
 310 {
 311         /*
 312          * Enable wakup behavior, smart idle and all wakeups
 313          * REVISIT: some wakeups may be unnecessary
 314          */
 315         if (cpu_is_omap34xx()) {
 316                 u16 syscon;
 317
 318                 syscon = OMAP_MCBSP_READ(mcbsp->io_base, SYSCON);
 319                 syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
 320
 321                 spin_lock_irq(&mcbsp->lock);
 322                 if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD)
 323                         syscon |= SIDLEMODE(0x02);
 324                 else
 325                         syscon |= SIDLEMODE(0x01);
 326                 spin_unlock_irq(&mcbsp->lock);
 327
 328                 syscon |= (ENAWAKEUP | CLOCKACTIVITY(0x02));
 329                 OMAP_MCBSP_WRITE(mcbsp->io_base, SYSCON, syscon);
 330
 331                 OMAP_MCBSP_WRITE(mcbsp->io_base, WAKEUPEN, XRDYEN | RRDYEN);
 332         }
 333 }
 334
 335 static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp)
 336 {
 337         /*
 338          * Disable wakup behavior, smart idle and all wakeups
 339          */
 340         if (cpu_is_omap34xx()) {
 341                 u16 syscon;
 342
 343                 syscon = OMAP_MCBSP_READ(mcbsp->io_base, SYSCON);
 344                 syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
 345                 OMAP_MCBSP_WRITE(mcbsp->io_base, SYSCON, syscon);
 346
 347                 OMAP_MCBSP_WRITE(mcbsp->io_base, WAKEUPEN, 0);
 348         }
 349 }
 350 #else
 351 static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp) {}
 352 static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp) {}
 353 #endif
 354
 355 /*
 356  * We can choose between IRQ based or polled IO.
 357  * This needs to be called before omap_mcbsp_request().
 358  */
 359 int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type)
 360 {
 361         struct omap_mcbsp *mcbsp;
 362
 363         if (!omap_mcbsp_check_valid_id(id)) {
 364                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 365                 return -ENODEV;
 366         }
 367         mcbsp = id_to_mcbsp_ptr(id);
 368
 369         spin_lock(&mcbsp->lock);
 370
 371         if (!mcbsp->free) {
 372                 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
 373                         mcbsp->id);
 374                 spin_unlock(&mcbsp->lock);
 375                 return -EINVAL;
 376         }
 377
 378         mcbsp->io_type = io_type;
 379
 380         spin_unlock(&mcbsp->lock);
 381
 382         return 0;
 383 }
 384 EXPORT_SYMBOL(omap_mcbsp_set_io_type);
 385
 386 int omap_mcbsp_request(unsigned int id)
 387 {
 388         struct omap_mcbsp *mcbsp;
 389         int err;
 390
 391         if (!omap_mcbsp_check_valid_id(id)) {
 392                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 393                 return -ENODEV;
 394         }
 395         mcbsp = id_to_mcbsp_ptr(id);
 396
 397         spin_lock(&mcbsp->lock);
 398         if (!mcbsp->free) {
 399                 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
 400                         mcbsp->id);
 401                 spin_unlock(&mcbsp->lock);
 402                 return -EBUSY;
 403         }
 404
 405         mcbsp->free = 0;
 406         spin_unlock(&mcbsp->lock);
 407
 408         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
 409                 mcbsp->pdata->ops->request(id);
 410
 411         clk_enable(mcbsp->iclk);
 412         clk_enable(mcbsp->fclk);
 413
 414         /* Do procedure specific to omap34xx arch, if applicable */
 415         omap34xx_mcbsp_request(mcbsp);
 416
 417         /*
 418          * Make sure that transmitter, receiver and sample-rate generator are
 419          * not running before activating IRQs.
 420          */
 421         OMAP_MCBSP_WRITE(mcbsp->io_base, SPCR1, 0);
 422         OMAP_MCBSP_WRITE(mcbsp->io_base, SPCR2, 0);
 423
 424         if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
 425                 /* We need to get IRQs here */
 426                 init_completion(&mcbsp->tx_irq_completion);
 427                 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler,
 428                                         0, "McBSP", (void *)mcbsp);
 429                 if (err != 0) {
 430                         dev_err(mcbsp->dev, "Unable to request TX IRQ %d "
 431                                         "for McBSP%d\n", mcbsp->tx_irq,
 432                                         mcbsp->id);
 433                         return err;
 434                 }
 435
 436                 init_completion(&mcbsp->rx_irq_completion);
 437                 err = request_irq(mcbsp->rx_irq, omap_mcbsp_rx_irq_handler,
 438                                         0, "McBSP", (void *)mcbsp);
 439                 if (err != 0) {
 440                         dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
 441                                         "for McBSP%d\n", mcbsp->rx_irq,
 442                                         mcbsp->id);
 443                         free_irq(mcbsp->tx_irq, (void *)mcbsp);
 444                         return err;
 445                 }
 446         }
 447
 448         return 0;
 449 }
 450 EXPORT_SYMBOL(omap_mcbsp_request);
 451
 452 void omap_mcbsp_free(unsigned int id)
 453 {
 454         struct omap_mcbsp *mcbsp;
 455
 456         if (!omap_mcbsp_check_valid_id(id)) {
 457                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 458                 return;
 459         }
 460         mcbsp = id_to_mcbsp_ptr(id);
 461
 462         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
 463                 mcbsp->pdata->ops->free(id);
 464
 465         /* Do procedure specific to omap34xx arch, if applicable */
 466         omap34xx_mcbsp_free(mcbsp);
 467
 468         clk_disable(mcbsp->fclk);
 469         clk_disable(mcbsp->iclk);
 470
 471         if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
 472                 /* Free IRQs */
 473                 free_irq(mcbsp->rx_irq, (void *)mcbsp);
 474                 free_irq(mcbsp->tx_irq, (void *)mcbsp);
 475         }
 476
 477         spin_lock(&mcbsp->lock);
 478         if (mcbsp->free) {
 479                 dev_err(mcbsp->dev, "McBSP%d was not reserved\n",
 480                         mcbsp->id);
 481                 spin_unlock(&mcbsp->lock);
 482                 return;
 483         }
 484
 485         mcbsp->free = 1;
 486         spin_unlock(&mcbsp->lock);
 487 }
 488 EXPORT_SYMBOL(omap_mcbsp_free);
 489
 490 /*
 491  * Here we start the McBSP, by enabling transmitter, receiver or both.
 492  * If no transmitter or receiver is active prior calling, then sample-rate
 493  * generator and frame sync are started.
 494  */
 495 void omap_mcbsp_start(unsigned int id, int tx, int rx)
 496 {
 497         struct omap_mcbsp *mcbsp;
 498         void __iomem *io_base;
 499         int idle;
 500         u16 w;
 501
 502         if (!omap_mcbsp_check_valid_id(id)) {
 503                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 504                 return;
 505         }
 506         mcbsp = id_to_mcbsp_ptr(id);
 507         io_base = mcbsp->io_base;
 508
 509         mcbsp->rx_word_length = (OMAP_MCBSP_READ(io_base, RCR1) >> 5) & 0x7;
 510         mcbsp->tx_word_length = (OMAP_MCBSP_READ(io_base, XCR1) >> 5) & 0x7;
 511
 512         idle = !((OMAP_MCBSP_READ(io_base, SPCR2) |
 513                   OMAP_MCBSP_READ(io_base, SPCR1)) & 1);
 514
 515         if (idle) {
 516                 /* Start the sample generator */
 517                 w = OMAP_MCBSP_READ(io_base, SPCR2);
 518                 OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 6));
 519         }
 520
 521         /* Enable transmitter and receiver */
 522         w = OMAP_MCBSP_READ(io_base, SPCR2);
 523         OMAP_MCBSP_WRITE(io_base, SPCR2, w | (tx & 1));
 524
 525         w = OMAP_MCBSP_READ(io_base, SPCR1);
 526         OMAP_MCBSP_WRITE(io_base, SPCR1, w | (rx & 1));
 527
 528         /*
 529          * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
 530          * REVISIT: 100us may give enough time for two CLKSRG, however
 531          * due to some unknown PM related, clock gating etc. reason it
 532          * is now at 500us.
 533          */
 534         udelay(500);
 535
 536         if (idle) {
 537                 /* Start frame sync */
 538                 w = OMAP_MCBSP_READ(io_base, SPCR2);
 539                 OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 7));
 540         }
 541
 542         /* Dump McBSP Regs */
 543         omap_mcbsp_dump_reg(id);
 544 }
 545 EXPORT_SYMBOL(omap_mcbsp_start);
 546
 547 void omap_mcbsp_stop(unsigned int id, int tx, int rx)
 548 {
 549         struct omap_mcbsp *mcbsp;
 550         void __iomem *io_base;
 551         int idle;
 552         u16 w;
 553
 554         if (!omap_mcbsp_check_valid_id(id)) {
 555                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 556                 return;
 557         }
 558
 559         mcbsp = id_to_mcbsp_ptr(id);
 560         io_base = mcbsp->io_base;
 561
 562         /* Reset transmitter */
 563         w = OMAP_MCBSP_READ(io_base, SPCR2);
 564         OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(tx & 1));
 565
 566         /* Reset receiver */
 567         w = OMAP_MCBSP_READ(io_base, SPCR1);
 568         OMAP_MCBSP_WRITE(io_base, SPCR1, w & ~(rx & 1));
 569
 570         idle = !((OMAP_MCBSP_READ(io_base, SPCR2) |
 571                   OMAP_MCBSP_READ(io_base, SPCR1)) & 1);
 572
 573         if (idle) {
 574                 /* Reset the sample rate generator */
 575                 w = OMAP_MCBSP_READ(io_base, SPCR2);
 576                 OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1 << 6));
 577         }
 578 }
 579 EXPORT_SYMBOL(omap_mcbsp_stop);
 580
 581 void omap_mcbsp_xmit_enable(unsigned int id, u8 enable)
 582 {
 583         struct omap_mcbsp *mcbsp;
 584         void __iomem *io_base;
 585         u16 w;
 586
 587         if (!(cpu_is_omap2430() || cpu_is_omap34xx()))
 588                 return;
 589
 590         if (!omap_mcbsp_check_valid_id(id)) {
 591                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 592                 return;
 593         }
 594
 595         mcbsp = id_to_mcbsp_ptr(id);
 596         io_base = mcbsp->io_base;
 597
 598         w = OMAP_MCBSP_READ(io_base, XCCR);
 599
 600         if (enable)
 601                 OMAP_MCBSP_WRITE(io_base, XCCR, w & ~(XDISABLE));
 602         else
 603                 OMAP_MCBSP_WRITE(io_base, XCCR, w | XDISABLE);
 604 }
 605 EXPORT_SYMBOL(omap_mcbsp_xmit_enable);
 606
 607 void omap_mcbsp_recv_enable(unsigned int id, u8 enable)
 608 {
 609         struct omap_mcbsp *mcbsp;
 610         void __iomem *io_base;
 611         u16 w;
 612
 613         if (!(cpu_is_omap2430() || cpu_is_omap34xx()))
 614                 return;
 615
 616         if (!omap_mcbsp_check_valid_id(id)) {
 617                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 618                 return;
 619         }
 620
 621         mcbsp = id_to_mcbsp_ptr(id);
 622         io_base = mcbsp->io_base;
 623
 624         w = OMAP_MCBSP_READ(io_base, RCCR);
 625
 626         if (enable)
 627                 OMAP_MCBSP_WRITE(io_base, RCCR, w & ~(RDISABLE));
 628         else
 629                 OMAP_MCBSP_WRITE(io_base, RCCR, w | RDISABLE);
 630 }
 631 EXPORT_SYMBOL(omap_mcbsp_recv_enable);
 632
 633 /* polled mcbsp i/o operations */
 634 int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
 635 {
 636         struct omap_mcbsp *mcbsp;
 637         void __iomem *base;
 638
 639         if (!omap_mcbsp_check_valid_id(id)) {
 640                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 641                 return -ENODEV;
 642         }
 643
 644         mcbsp = id_to_mcbsp_ptr(id);
 645         base = mcbsp->io_base;
 646
 647         writew(buf, base + OMAP_MCBSP_REG_DXR1);
 648         /* if frame sync error - clear the error */
 649         if (readw(base + OMAP_MCBSP_REG_SPCR2) & XSYNC_ERR) {
 650                 /* clear error */
 651                 writew(readw(base + OMAP_MCBSP_REG_SPCR2) & (~XSYNC_ERR),
 652                        base + OMAP_MCBSP_REG_SPCR2);
 653                 /* resend */
 654                 return -1;
 655         } else {
 656                 /* wait for transmit confirmation */
 657                 int attemps = 0;
 658                 while (!(readw(base + OMAP_MCBSP_REG_SPCR2) & XRDY)) {
 659                         if (attemps++ > 1000) {
 660                                 writew(readw(base + OMAP_MCBSP_REG_SPCR2) &
 661                                        (~XRST),
 662                                        base + OMAP_MCBSP_REG_SPCR2);
 663                                 udelay(10);
 664                                 writew(readw(base + OMAP_MCBSP_REG_SPCR2) |
 665                                        (XRST),
 666                                        base + OMAP_MCBSP_REG_SPCR2);
 667                                 udelay(10);
 668                                 dev_err(mcbsp->dev, "Could not write to"
 669                                         " McBSP%d Register\n", mcbsp->id);
 670                                 return -2;
 671                         }
 672                 }
 673         }
 674
 675         return 0;
 676 }
 677 EXPORT_SYMBOL(omap_mcbsp_pollwrite);
 678
 679 int omap_mcbsp_pollread(unsigned int id, u16 *buf)
 680 {
 681         struct omap_mcbsp *mcbsp;
 682         void __iomem *base;
 683
 684         if (!omap_mcbsp_check_valid_id(id)) {
 685                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 686                 return -ENODEV;
 687         }
 688         mcbsp = id_to_mcbsp_ptr(id);
 689
 690         base = mcbsp->io_base;
 691         /* if frame sync error - clear the error */
 692         if (readw(base + OMAP_MCBSP_REG_SPCR1) & RSYNC_ERR) {
 693                 /* clear error */
 694                 writew(readw(base + OMAP_MCBSP_REG_SPCR1) & (~RSYNC_ERR),
 695                        base + OMAP_MCBSP_REG_SPCR1);
 696                 /* resend */
 697                 return -1;
 698         } else {
 699                 /* wait for recieve confirmation */
 700                 int attemps = 0;
 701                 while (!(readw(base + OMAP_MCBSP_REG_SPCR1) & RRDY)) {
 702                         if (attemps++ > 1000) {
 703                                 writew(readw(base + OMAP_MCBSP_REG_SPCR1) &
 704                                        (~RRST),
 705                                        base + OMAP_MCBSP_REG_SPCR1);
 706                                 udelay(10);
 707                                 writew(readw(base + OMAP_MCBSP_REG_SPCR1) |
 708                                        (RRST),
 709                                        base + OMAP_MCBSP_REG_SPCR1);
 710                                 udelay(10);
 711                                 dev_err(mcbsp->dev, "Could not read from"
 712                                         " McBSP%d Register\n", mcbsp->id);
 713                                 return -2;
 714                         }
 715                 }
 716         }
 717         *buf = readw(base + OMAP_MCBSP_REG_DRR1);
 718
 719         return 0;
 720 }
 721 EXPORT_SYMBOL(omap_mcbsp_pollread);
 722
 723 /*
 724  * IRQ based word transmission.
 725  */
 726 void omap_mcbsp_xmit_word(unsigned int id, u32 word)
 727 {
 728         struct omap_mcbsp *mcbsp;
 729         void __iomem *io_base;
 730         omap_mcbsp_word_length word_length;
 731
 732         if (!omap_mcbsp_check_valid_id(id)) {
 733                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 734                 return;
 735         }
 736
 737         mcbsp = id_to_mcbsp_ptr(id);
 738         io_base = mcbsp->io_base;
 739         word_length = mcbsp->tx_word_length;
 740
 741         wait_for_completion(&mcbsp->tx_irq_completion);
 742
 743         if (word_length > OMAP_MCBSP_WORD_16)
 744                 OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16);
 745         OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff);
 746 }
 747 EXPORT_SYMBOL(omap_mcbsp_xmit_word);
 748
 749 u32 omap_mcbsp_recv_word(unsigned int id)
 750 {
 751         struct omap_mcbsp *mcbsp;
 752         void __iomem *io_base;
 753         u16 word_lsb, word_msb = 0;
 754         omap_mcbsp_word_length word_length;
 755
 756         if (!omap_mcbsp_check_valid_id(id)) {
 757                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 758                 return -ENODEV;
 759         }
 760         mcbsp = id_to_mcbsp_ptr(id);
 761
 762         word_length = mcbsp->rx_word_length;
 763         io_base = mcbsp->io_base;
 764
 765         wait_for_completion(&mcbsp->rx_irq_completion);
 766
 767         if (word_length > OMAP_MCBSP_WORD_16)
 768                 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
 769         word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
 770
 771         return (word_lsb | (word_msb << 16));
 772 }
 773 EXPORT_SYMBOL(omap_mcbsp_recv_word);
 774
 775 int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
 776 {
 777         struct omap_mcbsp *mcbsp;
 778         void __iomem *io_base;
 779         omap_mcbsp_word_length tx_word_length;
 780         omap_mcbsp_word_length rx_word_length;
 781         u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
 782
 783         if (!omap_mcbsp_check_valid_id(id)) {
 784                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 785                 return -ENODEV;
 786         }
 787         mcbsp = id_to_mcbsp_ptr(id);
 788         io_base = mcbsp->io_base;
 789         tx_word_length = mcbsp->tx_word_length;
 790         rx_word_length = mcbsp->rx_word_length;
 791
 792         if (tx_word_length != rx_word_length)
 793                 return -EINVAL;
 794
 795         /* First we wait for the transmitter to be ready */
 796         spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
 797         while (!(spcr2 & XRDY)) {
 798                 spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
 799                 if (attempts++ > 1000) {
 800                         /* We must reset the transmitter */
 801                         OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 & (~XRST));
 802                         udelay(10);
 803                         OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
 804                         udelay(10);
 805                         dev_err(mcbsp->dev, "McBSP%d transmitter not "
 806                                 "ready\n", mcbsp->id);
 807                         return -EAGAIN;
 808                 }
 809         }
 810
 811         /* Now we can push the data */
 812         if (tx_word_length > OMAP_MCBSP_WORD_16)
 813                 OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16);
 814         OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff);
 815
 816         /* We wait for the receiver to be ready */
 817         spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
 818         while (!(spcr1 & RRDY)) {
 819                 spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
 820                 if (attempts++ > 1000) {
 821                         /* We must reset the receiver */
 822                         OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 & (~RRST));
 823                         udelay(10);
 824                         OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
 825                         udelay(10);
 826                         dev_err(mcbsp->dev, "McBSP%d receiver not "
 827                                 "ready\n", mcbsp->id);
 828                         return -EAGAIN;
 829                 }
 830         }
 831
 832         /* Receiver is ready, let's read the dummy data */
 833         if (rx_word_length > OMAP_MCBSP_WORD_16)
 834                 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
 835         word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
 836
 837         return 0;
 838 }
 839 EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll);
 840
 841 int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
 842 {
 843         struct omap_mcbsp *mcbsp;
 844         u32 clock_word = 0;
 845         void __iomem *io_base;
 846         omap_mcbsp_word_length tx_word_length;
 847         omap_mcbsp_word_length rx_word_length;
 848         u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
 849
 850         if (!omap_mcbsp_check_valid_id(id)) {
 851                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 852                 return -ENODEV;
 853         }
 854
 855         mcbsp = id_to_mcbsp_ptr(id);
 856         io_base = mcbsp->io_base;
 857
 858         tx_word_length = mcbsp->tx_word_length;
 859         rx_word_length = mcbsp->rx_word_length;
 860
 861         if (tx_word_length != rx_word_length)
 862                 return -EINVAL;
 863
 864         /* First we wait for the transmitter to be ready */
 865         spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
 866         while (!(spcr2 & XRDY)) {
 867                 spcr2 = OMAP_MCBSP_READ(io_base, SPCR2);
 868                 if (attempts++ > 1000) {
 869                         /* We must reset the transmitter */
 870                         OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 & (~XRST));
 871                         udelay(10);
 872                         OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
 873                         udelay(10);
 874                         dev_err(mcbsp->dev, "McBSP%d transmitter not "
 875                                 "ready\n", mcbsp->id);
 876                         return -EAGAIN;
 877                 }
 878         }
 879
 880         /* We first need to enable the bus clock */
 881         if (tx_word_length > OMAP_MCBSP_WORD_16)
 882                 OMAP_MCBSP_WRITE(io_base, DXR2, clock_word >> 16);
 883         OMAP_MCBSP_WRITE(io_base, DXR1, clock_word & 0xffff);
 884
 885         /* We wait for the receiver to be ready */
 886         spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
 887         while (!(spcr1 & RRDY)) {
 888                 spcr1 = OMAP_MCBSP_READ(io_base, SPCR1);
 889                 if (attempts++ > 1000) {
 890                         /* We must reset the receiver */
 891                         OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 & (~RRST));
 892                         udelay(10);
 893                         OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
 894                         udelay(10);
 895                         dev_err(mcbsp->dev, "McBSP%d receiver not "
 896                                 "ready\n", mcbsp->id);
 897                         return -EAGAIN;
 898                 }
 899         }
 900
 901         /* Receiver is ready, there is something for us */
 902         if (rx_word_length > OMAP_MCBSP_WORD_16)
 903                 word_msb = OMAP_MCBSP_READ(io_base, DRR2);
 904         word_lsb = OMAP_MCBSP_READ(io_base, DRR1);
 905
 906         word[0] = (word_lsb | (word_msb << 16));
 907
 908         return 0;
 909 }
 910 EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll);
 911
 912 /*
 913  * Simple DMA based buffer rx/tx routines.
 914  * Nothing fancy, just a single buffer tx/rx through DMA.
 915  * The DMA resources are released once the transfer is done.
 916  * For anything fancier, you should use your own customized DMA
 917  * routines and callbacks.
 918  */
 919 int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer,
 920                                 unsigned int length)
 921 {
 922         struct omap_mcbsp *mcbsp;
 923         int dma_tx_ch;
 924         int src_port = 0;
 925         int dest_port = 0;
 926         int sync_dev = 0;
 927
 928         if (!omap_mcbsp_check_valid_id(id)) {
 929                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 930                 return -ENODEV;
 931         }
 932         mcbsp = id_to_mcbsp_ptr(id);
 933
 934         if (omap_request_dma(mcbsp->dma_tx_sync, "McBSP TX",
 935                                 omap_mcbsp_tx_dma_callback,
 936                                 mcbsp,
 937                                 &dma_tx_ch)) {
 938                 dev_err(mcbsp->dev, " Unable to request DMA channel for "
 939                                 "McBSP%d TX. Trying IRQ based TX\n",
 940                                 mcbsp->id);
 941                 return -EAGAIN;
 942         }
 943         mcbsp->dma_tx_lch = dma_tx_ch;
 944
 945         dev_err(mcbsp->dev, "McBSP%d TX DMA on channel %d\n", mcbsp->id,
 946                 dma_tx_ch);
 947
 948         init_completion(&mcbsp->tx_dma_completion);
 949
 950         if (cpu_class_is_omap1()) {
 951                 src_port = OMAP_DMA_PORT_TIPB;
 952                 dest_port = OMAP_DMA_PORT_EMIFF;
 953         }
 954         if (cpu_class_is_omap2())
 955                 sync_dev = mcbsp->dma_tx_sync;
 956
 957         omap_set_dma_transfer_params(mcbsp->dma_tx_lch,
 958                                      OMAP_DMA_DATA_TYPE_S16,
 959                                      length >> 1, 1,
 960                                      OMAP_DMA_SYNC_ELEMENT,
 961          sync_dev, 0);
 962
 963         omap_set_dma_dest_params(mcbsp->dma_tx_lch,
 964                                  src_port,
 965                                  OMAP_DMA_AMODE_CONSTANT,
 966                                  mcbsp->phys_base + OMAP_MCBSP_REG_DXR1,
 967                                  0, 0);
 968
 969         omap_set_dma_src_params(mcbsp->dma_tx_lch,
 970                                 dest_port,
 971                                 OMAP_DMA_AMODE_POST_INC,
 972                                 buffer,
 973                                 0, 0);
 974
 975         omap_start_dma(mcbsp->dma_tx_lch);
 976         wait_for_completion(&mcbsp->tx_dma_completion);
 977
 978         return 0;
 979 }
 980 EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
 981
 982 int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer,
 983                                 unsigned int length)
 984 {
 985         struct omap_mcbsp *mcbsp;
 986         int dma_rx_ch;
 987         int src_port = 0;
 988         int dest_port = 0;
 989         int sync_dev = 0;
 990
 991         if (!omap_mcbsp_check_valid_id(id)) {
 992                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 993                 return -ENODEV;
 994         }
 995         mcbsp = id_to_mcbsp_ptr(id);
 996
 997         if (omap_request_dma(mcbsp->dma_rx_sync, "McBSP RX",
 998                                 omap_mcbsp_rx_dma_callback,
 999                                 mcbsp,
1000                                 &dma_rx_ch)) {
1001                 dev_err(mcbsp->dev, "Unable to request DMA channel for "
1002                                 "McBSP%d RX. Trying IRQ based RX\n",
1003                                 mcbsp->id);
1004                 return -EAGAIN;
1005         }
1006         mcbsp->dma_rx_lch = dma_rx_ch;
1007
1008         dev_err(mcbsp->dev, "McBSP%d RX DMA on channel %d\n", mcbsp->id,
1009                 dma_rx_ch);
1010
1011         init_completion(&mcbsp->rx_dma_completion);
1012
1013         if (cpu_class_is_omap1()) {
1014                 src_port = OMAP_DMA_PORT_TIPB;
1015                 dest_port = OMAP_DMA_PORT_EMIFF;
1016         }
1017         if (cpu_class_is_omap2())
1018                 sync_dev = mcbsp->dma_rx_sync;
1019
1020         omap_set_dma_transfer_params(mcbsp->dma_rx_lch,
1021                                         OMAP_DMA_DATA_TYPE_S16,
1022                                         length >> 1, 1,
1023                                         OMAP_DMA_SYNC_ELEMENT,
1024                                         sync_dev, 0);
1025
1026         omap_set_dma_src_params(mcbsp->dma_rx_lch,
1027                                 src_port,
1028                                 OMAP_DMA_AMODE_CONSTANT,
1029                                 mcbsp->phys_base + OMAP_MCBSP_REG_DRR1,
1030                                 0, 0);
1031
1032         omap_set_dma_dest_params(mcbsp->dma_rx_lch,
1033                                         dest_port,
1034                                         OMAP_DMA_AMODE_POST_INC,
1035                                         buffer,
1036                                         0, 0);
1037
1038         omap_start_dma(mcbsp->dma_rx_lch);
1039         wait_for_completion(&mcbsp->rx_dma_completion);
1040
1041         return 0;
1042 }
1043 EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
1044
1045 /*
1046  * SPI wrapper.
1047  * Since SPI setup is much simpler than the generic McBSP one,
1048  * this wrapper just need an omap_mcbsp_spi_cfg structure as an input.
1049  * Once this is done, you can call omap_mcbsp_start().
1050  */
1051 void omap_mcbsp_set_spi_mode(unsigned int id,
1052                                 const struct omap_mcbsp_spi_cfg *spi_cfg)
1053 {
1054         struct omap_mcbsp *mcbsp;
1055         struct omap_mcbsp_reg_cfg mcbsp_cfg;
1056
1057         if (!omap_mcbsp_check_valid_id(id)) {
1058                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1059                 return;
1060         }
1061         mcbsp = id_to_mcbsp_ptr(id);
1062
1063         memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg));
1064
1065         /* SPI has only one frame */
1066         mcbsp_cfg.rcr1 |= (RWDLEN1(spi_cfg->word_length) | RFRLEN1(0));
1067         mcbsp_cfg.xcr1 |= (XWDLEN1(spi_cfg->word_length) | XFRLEN1(0));
1068
1069         /* Clock stop mode */
1070         if (spi_cfg->clk_stp_mode == OMAP_MCBSP_CLK_STP_MODE_NO_DELAY)
1071                 mcbsp_cfg.spcr1 |= (1 << 12);
1072         else
1073                 mcbsp_cfg.spcr1 |= (3 << 11);
1074
1075         /* Set clock parities */
1076         if (spi_cfg->rx_clock_polarity == OMAP_MCBSP_CLK_RISING)
1077                 mcbsp_cfg.pcr0 |= CLKRP;
1078         else
1079                 mcbsp_cfg.pcr0 &= ~CLKRP;
1080
1081         if (spi_cfg->tx_clock_polarity == OMAP_MCBSP_CLK_RISING)
1082                 mcbsp_cfg.pcr0 &= ~CLKXP;
1083         else
1084                 mcbsp_cfg.pcr0 |= CLKXP;
1085
1086         /* Set SCLKME to 0 and CLKSM to 1 */
1087         mcbsp_cfg.pcr0 &= ~SCLKME;
1088         mcbsp_cfg.srgr2 |= CLKSM;
1089
1090         /* Set FSXP */
1091         if (spi_cfg->fsx_polarity == OMAP_MCBSP_FS_ACTIVE_HIGH)
1092                 mcbsp_cfg.pcr0 &= ~FSXP;
1093         else
1094                 mcbsp_cfg.pcr0 |= FSXP;
1095
1096         if (spi_cfg->spi_mode == OMAP_MCBSP_SPI_MASTER) {
1097                 mcbsp_cfg.pcr0 |= CLKXM;
1098                 mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div - 1);
1099                 mcbsp_cfg.pcr0 |= FSXM;
1100                 mcbsp_cfg.srgr2 &= ~FSGM;
1101                 mcbsp_cfg.xcr2 |= XDATDLY(1);
1102                 mcbsp_cfg.rcr2 |= RDATDLY(1);
1103         } else {
1104                 mcbsp_cfg.pcr0 &= ~CLKXM;
1105                 mcbsp_cfg.srgr1 |= CLKGDV(1);
1106                 mcbsp_cfg.pcr0 &= ~FSXM;
1107                 mcbsp_cfg.xcr2 &= ~XDATDLY(3);
1108                 mcbsp_cfg.rcr2 &= ~RDATDLY(3);
1109         }
1110
1111         mcbsp_cfg.xcr2 &= ~XPHASE;
1112         mcbsp_cfg.rcr2 &= ~RPHASE;
1113
1114         omap_mcbsp_config(id, &mcbsp_cfg);
1115 }
1116 EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);
1117
1118 #ifdef CONFIG_ARCH_OMAP34XX
1119 #define max_thres(m)                    (mcbsp->pdata->buffer_size)
1120 #define valid_threshold(m, val)         ((val) <= max_thres(m))
1121 #define THRESHOLD_PROP_BUILDER(prop)                                    \
1122 static ssize_t prop##_show(struct device *dev,                          \
1123                         struct device_attribute *attr, char *buf)       \
1124 {                                                                       \
1125         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);                \
1126                                                                         \
1127         return sprintf(buf, "%u\n", mcbsp->prop);                       \
1128 }                                                                       \
1129                                                                         \
1130 static ssize_t prop##_store(struct device *dev,                         \
1131                                 struct device_attribute *attr,          \
1132                                 const char *buf, size_t size)           \
1133 {                                                                       \
1134         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);                \
1135         unsigned long val;                                              \
1136         int status;                                                     \
1137                                                                         \
1138         status = strict_strtoul(buf, 0, &val);                          \
1139         if (status)                                                     \
1140                 return status;                                          \
1141                                                                         \
1142         if (!valid_threshold(mcbsp, val))                               \
1143                 return -EDOM;                                           \
1144                                                                         \
1145         mcbsp->prop = val;                                              \
1146         return size;                                                    \
1147 }                                                                       \
1148                                                                         \
1149 static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store);
1150
1151 THRESHOLD_PROP_BUILDER(max_tx_thres);
1152 THRESHOLD_PROP_BUILDER(max_rx_thres);
1153
1154 static ssize_t dma_op_mode_show(struct device *dev,
1155                         struct device_attribute *attr, char *buf)
1156 {
1157         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1158         int dma_op_mode;
1159
1160         spin_lock_irq(&mcbsp->lock);
1161         dma_op_mode = mcbsp->dma_op_mode;
1162         spin_unlock_irq(&mcbsp->lock);
1163
1164         return sprintf(buf, "current mode: %d\n"
1165                         "possible mode values are:\n"
1166                         "%d - %s\n"
1167                         "%d - %s\n"
1168                         "%d - %s\n",
1169                         dma_op_mode,
1170                         MCBSP_DMA_MODE_ELEMENT, "element mode",
1171                         MCBSP_DMA_MODE_THRESHOLD, "threshold mode",
1172                         MCBSP_DMA_MODE_FRAME, "frame mode");
1173 }
1174
1175 static ssize_t dma_op_mode_store(struct device *dev,
1176                                 struct device_attribute *attr,
1177                                 const char *buf, size_t size)
1178 {
1179         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1180         unsigned long val;
1181         int status;
1182
1183         status = strict_strtoul(buf, 0, &val);
1184         if (status)
1185                 return status;
1186
1187         spin_lock_irq(&mcbsp->lock);
1188
1189         if (!mcbsp->free) {
1190                 size = -EBUSY;
1191                 goto unlock;
1192         }
1193
1194         if (val > MCBSP_DMA_MODE_FRAME || val < MCBSP_DMA_MODE_ELEMENT) {
1195                 size = -EINVAL;
1196                 goto unlock;
1197         }
1198
1199         mcbsp->dma_op_mode = val;
1200
1201 unlock:
1202         spin_unlock_irq(&mcbsp->lock);
1203
1204         return size;
1205 }
1206
1207 static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store);
1208
1209 static const struct attribute *additional_attrs[] = {
1210         &dev_attr_max_tx_thres.attr,
1211         &dev_attr_max_rx_thres.attr,
1212         &dev_attr_dma_op_mode.attr,
1213         NULL,
1214 };
1215
1216 static const struct attribute_group additional_attr_group = {
1217         .attrs = (struct attribute **)additional_attrs,
1218 };
1219
1220 static inline int __devinit omap_additional_add(struct device *dev)
1221 {
1222         return sysfs_create_group(&dev->kobj, &additional_attr_group);
1223 }
1224
1225 static inline void __devexit omap_additional_remove(struct device *dev)
1226 {
1227         sysfs_remove_group(&dev->kobj, &additional_attr_group);
1228 }
1229
1230 static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp)
1231 {
1232         mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
1233         if (cpu_is_omap34xx()) {
1234                 mcbsp->max_tx_thres = max_thres(mcbsp);
1235                 mcbsp->max_rx_thres = max_thres(mcbsp);
1236                 /*
1237                  * REVISIT: Set dmap_op_mode to THRESHOLD as default
1238                  * for mcbsp2 instances.
1239                  */
1240                 if (omap_additional_add(mcbsp->dev))
1241                         dev_warn(mcbsp->dev,
1242                                 "Unable to create additional controls\n");
1243         } else {
1244                 mcbsp->max_tx_thres = -EINVAL;
1245                 mcbsp->max_rx_thres = -EINVAL;
1246         }
1247 }
1248
1249 static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp)
1250 {
1251         if (cpu_is_omap34xx())
1252                 omap_additional_remove(mcbsp->dev);
1253 }
1254 #else
1255 static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp) {}
1256 static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp) {}
1257 #endif /* CONFIG_ARCH_OMAP34XX */
1258
1259 /*
1260  * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
1261  * 730 has only 2 McBSP, and both of them are MPU peripherals.
1262  */
1263 static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
1264 {
1265         struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data;
1266         struct omap_mcbsp *mcbsp;
1267         int id = pdev->id - 1;
1268         int ret = 0;
1269
1270         if (!pdata) {
1271                 dev_err(&pdev->dev, "McBSP device initialized without"
1272                                 "platform data\n");
1273                 ret = -EINVAL;
1274                 goto exit;
1275         }
1276
1277         dev_dbg(&pdev->dev, "Initializing OMAP McBSP (%d).\n", pdev->id);
1278
1279         if (id >= omap_mcbsp_count) {
1280                 dev_err(&pdev->dev, "Invalid McBSP device id (%d)\n", id);
1281                 ret = -EINVAL;
1282                 goto exit;
1283         }
1284
1285         mcbsp = kzalloc(sizeof(struct omap_mcbsp), GFP_KERNEL);
1286         if (!mcbsp) {
1287                 ret = -ENOMEM;
1288                 goto exit;
1289         }
1290
1291         spin_lock_init(&mcbsp->lock);
1292         mcbsp->id = id + 1;
1293         mcbsp->free = 1;
1294         mcbsp->dma_tx_lch = -1;
1295         mcbsp->dma_rx_lch = -1;
1296
1297         mcbsp->phys_base = pdata->phys_base;
1298         mcbsp->io_base = ioremap(pdata->phys_base, SZ_4K);
1299         if (!mcbsp->io_base) {
1300                 ret = -ENOMEM;
1301                 goto err_ioremap;
1302         }
1303
1304         /* Default I/O is IRQ based */
1305         mcbsp->io_type = OMAP_MCBSP_IRQ_IO;
1306         mcbsp->tx_irq = pdata->tx_irq;
1307         mcbsp->rx_irq = pdata->rx_irq;
1308         mcbsp->dma_rx_sync = pdata->dma_rx_sync;
1309         mcbsp->dma_tx_sync = pdata->dma_tx_sync;
1310
1311         mcbsp->iclk = clk_get(&pdev->dev, "ick");
1312         if (IS_ERR(mcbsp->iclk)) {
1313                 ret = PTR_ERR(mcbsp->iclk);
1314                 dev_err(&pdev->dev, "unable to get ick: %d\n", ret);
1315                 goto err_iclk;
1316         }
1317
1318         mcbsp->fclk = clk_get(&pdev->dev, "fck");
1319         if (IS_ERR(mcbsp->fclk)) {
1320                 ret = PTR_ERR(mcbsp->fclk);
1321                 dev_err(&pdev->dev, "unable to get fck: %d\n", ret);
1322                 goto err_fclk;
1323         }
1324
1325         mcbsp->pdata = pdata;
1326         mcbsp->dev = &pdev->dev;
1327         mcbsp_ptr[id] = mcbsp;
1328         platform_set_drvdata(pdev, mcbsp);
1329
1330         /* Initialize mcbsp properties for OMAP34XX if needed / applicable */
1331         omap34xx_device_init(mcbsp);
1332
1333         return 0;
1334
1335 err_fclk:
1336         clk_put(mcbsp->iclk);
1337 err_iclk:
1338         iounmap(mcbsp->io_base);
1339 err_ioremap:
1340         kfree(mcbsp);
1341 exit:
1342         return ret;
1343 }
1344
1345 static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
1346 {
1347         struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
1348
1349         platform_set_drvdata(pdev, NULL);
1350         if (mcbsp) {
1351
1352                 if (mcbsp->pdata && mcbsp->pdata->ops &&
1353                                 mcbsp->pdata->ops->free)
1354                         mcbsp->pdata->ops->free(mcbsp->id);
1355
1356                 omap34xx_device_exit(mcbsp);
1357
1358                 clk_disable(mcbsp->fclk);
1359                 clk_disable(mcbsp->iclk);
1360                 clk_put(mcbsp->fclk);
1361                 clk_put(mcbsp->iclk);
1362
1363                 iounmap(mcbsp->io_base);
1364
1365                 mcbsp->fclk = NULL;
1366                 mcbsp->iclk = NULL;
1367                 mcbsp->free = 0;
1368                 mcbsp->dev = NULL;
1369         }
1370
1371         return 0;
1372 }
1373
1374 static struct platform_driver omap_mcbsp_driver = {
1375         .probe          = omap_mcbsp_probe,
1376         .remove         = __devexit_p(omap_mcbsp_remove),
1377         .driver         = {
1378                 .name   = "omap-mcbsp",
1379         },
1380 };
1381
1382 int __init omap_mcbsp_init(void)
1383 {
1384         /* Register the McBSP driver */
1385         return platform_driver_register(&omap_mcbsp_driver);
1386 }