arch/arm/plat-omap/mcbsp.c

   1 /*
   2  * linux/arch/arm/plat-omap/mcbsp.c
   3  *
   4  * Copyright (C) 2004 Nokia Corporation
   5  * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
   6  *
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * Multichannel mode not supported.
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/init.h>
  17 #include <linux/device.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/wait.h>
  20 #include <linux/completion.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/err.h>
  23 #include <linux/clk.h>
  24 #include <linux/delay.h>
  25 #include <linux/io.h>
  26 #include <linux/slab.h>
  27
  28 #include <plat/dma.h>
  29 #include <plat/mcbsp.h>
  30 #include <plat/omap_device.h>
  31
  32 /* XXX These "sideways" includes are a sign that something is wrong */
  33 #include "../mach-omap2/cm2xxx_3xxx.h"
  34 #include "../mach-omap2/cm-regbits-34xx.h"
  35
  36 struct omap_mcbsp **mcbsp_ptr;
  37 int omap_mcbsp_count, omap_mcbsp_cache_size;
  38
  39 static void omap_mcbsp_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
  40 {
  41         if (cpu_class_is_omap1()) {
  42                 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)] = (u16)val;
  43                 __raw_writew((u16)val, mcbsp->io_base + reg);
  44         } else if (cpu_is_omap2420()) {
  45                 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)] = (u16)val;
  46                 __raw_writew((u16)val, mcbsp->io_base + reg);
  47         } else {
  48                 ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)] = val;
  49                 __raw_writel(val, mcbsp->io_base + reg);
  50         }
  51 }
  52
  53 static int omap_mcbsp_read(struct omap_mcbsp *mcbsp, u16 reg, bool from_cache)
  54 {
  55         if (cpu_class_is_omap1()) {
  56                 return !from_cache ? __raw_readw(mcbsp->io_base + reg) :
  57                                 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u16)];
  58         } else if (cpu_is_omap2420()) {
  59                 return !from_cache ? __raw_readw(mcbsp->io_base + reg) :
  60                                 ((u16 *)mcbsp->reg_cache)[reg / sizeof(u32)];
  61         } else {
  62                 return !from_cache ? __raw_readl(mcbsp->io_base + reg) :
  63                                 ((u32 *)mcbsp->reg_cache)[reg / sizeof(u32)];
  64         }
  65 }
  66
  67 #ifdef CONFIG_ARCH_OMAP3
  68 static void omap_mcbsp_st_write(struct omap_mcbsp *mcbsp, u16 reg, u32 val)
  69 {
  70         __raw_writel(val, mcbsp->st_data->io_base_st + reg);
  71 }
  72
  73 static int omap_mcbsp_st_read(struct omap_mcbsp *mcbsp, u16 reg)
  74 {
  75         return __raw_readl(mcbsp->st_data->io_base_st + reg);
  76 }
  77 #endif
  78
  79 #define MCBSP_READ(mcbsp, reg) \
  80                 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 0)
  81 #define MCBSP_WRITE(mcbsp, reg, val) \
  82                 omap_mcbsp_write(mcbsp, OMAP_MCBSP_REG_##reg, val)
  83 #define MCBSP_READ_CACHE(mcbsp, reg) \
  84                 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1)
  85
  86 #define MCBSP_ST_READ(mcbsp, reg) \
  87                         omap_mcbsp_st_read(mcbsp, OMAP_ST_REG_##reg)
  88 #define MCBSP_ST_WRITE(mcbsp, reg, val) \
  89                         omap_mcbsp_st_write(mcbsp, OMAP_ST_REG_##reg, val)
  90
  91 static void omap_mcbsp_dump_reg(u8 id)
  92 {
  93         struct omap_mcbsp *mcbsp = id_to_mcbsp_ptr(id);
  94
  95         dev_dbg(mcbsp->dev, "**** McBSP%d regs ****\n", mcbsp->id);
  96         dev_dbg(mcbsp->dev, "DRR2:  0x%04x\n",
  97                         MCBSP_READ(mcbsp, DRR2));
  98         dev_dbg(mcbsp->dev, "DRR1:  0x%04x\n",
  99                         MCBSP_READ(mcbsp, DRR1));
 100         dev_dbg(mcbsp->dev, "DXR2:  0x%04x\n",
 101                         MCBSP_READ(mcbsp, DXR2));
 102         dev_dbg(mcbsp->dev, "DXR1:  0x%04x\n",
 103                         MCBSP_READ(mcbsp, DXR1));
 104         dev_dbg(mcbsp->dev, "SPCR2: 0x%04x\n",
 105                         MCBSP_READ(mcbsp, SPCR2));
 106         dev_dbg(mcbsp->dev, "SPCR1: 0x%04x\n",
 107                         MCBSP_READ(mcbsp, SPCR1));
 108         dev_dbg(mcbsp->dev, "RCR2:  0x%04x\n",
 109                         MCBSP_READ(mcbsp, RCR2));
 110         dev_dbg(mcbsp->dev, "RCR1:  0x%04x\n",
 111                         MCBSP_READ(mcbsp, RCR1));
 112         dev_dbg(mcbsp->dev, "XCR2:  0x%04x\n",
 113                         MCBSP_READ(mcbsp, XCR2));
 114         dev_dbg(mcbsp->dev, "XCR1:  0x%04x\n",
 115                         MCBSP_READ(mcbsp, XCR1));
 116         dev_dbg(mcbsp->dev, "SRGR2: 0x%04x\n",
 117                         MCBSP_READ(mcbsp, SRGR2));
 118         dev_dbg(mcbsp->dev, "SRGR1: 0x%04x\n",
 119                         MCBSP_READ(mcbsp, SRGR1));
 120         dev_dbg(mcbsp->dev, "PCR0:  0x%04x\n",
 121                         MCBSP_READ(mcbsp, PCR0));
 122         dev_dbg(mcbsp->dev, "***********************\n");
 123 }
 124
 125 static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
 126 {
 127         struct omap_mcbsp *mcbsp_tx = dev_id;
 128         u16 irqst_spcr2;
 129
 130         irqst_spcr2 = MCBSP_READ(mcbsp_tx, SPCR2);
 131         dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n", irqst_spcr2);
 132
 133         if (irqst_spcr2 & XSYNC_ERR) {
 134                 dev_err(mcbsp_tx->dev, "TX Frame Sync Error! : 0x%x\n",
 135                         irqst_spcr2);
 136                 /* Writing zero to XSYNC_ERR clears the IRQ */
 137                 MCBSP_WRITE(mcbsp_tx, SPCR2, MCBSP_READ_CACHE(mcbsp_tx, SPCR2));
 138         } else {
 139                 complete(&mcbsp_tx->tx_irq_completion);
 140         }
 141
 142         return IRQ_HANDLED;
 143 }
 144
 145 static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
 146 {
 147         struct omap_mcbsp *mcbsp_rx = dev_id;
 148         u16 irqst_spcr1;
 149
 150         irqst_spcr1 = MCBSP_READ(mcbsp_rx, SPCR1);
 151         dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n", irqst_spcr1);
 152
 153         if (irqst_spcr1 & RSYNC_ERR) {
 154                 dev_err(mcbsp_rx->dev, "RX Frame Sync Error! : 0x%x\n",
 155                         irqst_spcr1);
 156                 /* Writing zero to RSYNC_ERR clears the IRQ */
 157                 MCBSP_WRITE(mcbsp_rx, SPCR1, MCBSP_READ_CACHE(mcbsp_rx, SPCR1));
 158         } else {
 159                 complete(&mcbsp_rx->rx_irq_completion);
 160         }
 161
 162         return IRQ_HANDLED;
 163 }
 164
 165 static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data)
 166 {
 167         struct omap_mcbsp *mcbsp_dma_tx = data;
 168
 169         dev_dbg(mcbsp_dma_tx->dev, "TX DMA callback : 0x%x\n",
 170                 MCBSP_READ(mcbsp_dma_tx, SPCR2));
 171
 172         /* We can free the channels */
 173         omap_free_dma(mcbsp_dma_tx->dma_tx_lch);
 174         mcbsp_dma_tx->dma_tx_lch = -1;
 175
 176         complete(&mcbsp_dma_tx->tx_dma_completion);
 177 }
 178
 179 static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
 180 {
 181         struct omap_mcbsp *mcbsp_dma_rx = data;
 182
 183         dev_dbg(mcbsp_dma_rx->dev, "RX DMA callback : 0x%x\n",
 184                 MCBSP_READ(mcbsp_dma_rx, SPCR2));
 185
 186         /* We can free the channels */
 187         omap_free_dma(mcbsp_dma_rx->dma_rx_lch);
 188         mcbsp_dma_rx->dma_rx_lch = -1;
 189
 190         complete(&mcbsp_dma_rx->rx_dma_completion);
 191 }
 192
 193 /*
 194  * omap_mcbsp_config simply write a config to the
 195  * appropriate McBSP.
 196  * You either call this function or set the McBSP registers
 197  * by yourself before calling omap_mcbsp_start().
 198  */
 199 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
 200 {
 201         struct omap_mcbsp *mcbsp;
 202
 203         if (!omap_mcbsp_check_valid_id(id)) {
 204                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 205                 return;
 206         }
 207         mcbsp = id_to_mcbsp_ptr(id);
 208
 209         dev_dbg(mcbsp->dev, "Configuring McBSP%d  phys_base: 0x%08lx\n",
 210                         mcbsp->id, mcbsp->phys_base);
 211
 212         /* We write the given config */
 213         MCBSP_WRITE(mcbsp, SPCR2, config->spcr2);
 214         MCBSP_WRITE(mcbsp, SPCR1, config->spcr1);
 215         MCBSP_WRITE(mcbsp, RCR2, config->rcr2);
 216         MCBSP_WRITE(mcbsp, RCR1, config->rcr1);
 217         MCBSP_WRITE(mcbsp, XCR2, config->xcr2);
 218         MCBSP_WRITE(mcbsp, XCR1, config->xcr1);
 219         MCBSP_WRITE(mcbsp, SRGR2, config->srgr2);
 220         MCBSP_WRITE(mcbsp, SRGR1, config->srgr1);
 221         MCBSP_WRITE(mcbsp, MCR2, config->mcr2);
 222         MCBSP_WRITE(mcbsp, MCR1, config->mcr1);
 223         MCBSP_WRITE(mcbsp, PCR0, config->pcr0);
 224         if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
 225                 MCBSP_WRITE(mcbsp, XCCR, config->xccr);
 226                 MCBSP_WRITE(mcbsp, RCCR, config->rccr);
 227         }
 228 }
 229 EXPORT_SYMBOL(omap_mcbsp_config);
 230
 231 #ifdef CONFIG_ARCH_OMAP3
 232 static struct omap_device *find_omap_device_by_dev(struct device *dev)
 233 {
 234         struct platform_device *pdev = container_of(dev,
 235                                         struct platform_device, dev);
 236         return container_of(pdev, struct omap_device, pdev);
 237 }
 238
 239 static void omap_st_on(struct omap_mcbsp *mcbsp)
 240 {
 241         unsigned int w;
 242         struct omap_device *od;
 243
 244         od = find_omap_device_by_dev(mcbsp->dev);
 245
 246         /*
 247          * Sidetone uses McBSP ICLK - which must not idle when sidetones
 248          * are enabled or sidetones start sounding ugly.
 249          */
 250         w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
 251         w &= ~(1 << (mcbsp->id - 2));
 252         omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
 253
 254         /* Enable McBSP Sidetone */
 255         w = MCBSP_READ(mcbsp, SSELCR);
 256         MCBSP_WRITE(mcbsp, SSELCR, w | SIDETONEEN);
 257
 258         /* Enable Sidetone from Sidetone Core */
 259         w = MCBSP_ST_READ(mcbsp, SSELCR);
 260         MCBSP_ST_WRITE(mcbsp, SSELCR, w | ST_SIDETONEEN);
 261 }
 262
 263 static void omap_st_off(struct omap_mcbsp *mcbsp)
 264 {
 265         unsigned int w;
 266         struct omap_device *od;
 267
 268         od = find_omap_device_by_dev(mcbsp->dev);
 269
 270         w = MCBSP_ST_READ(mcbsp, SSELCR);
 271         MCBSP_ST_WRITE(mcbsp, SSELCR, w & ~(ST_SIDETONEEN));
 272
 273         w = MCBSP_READ(mcbsp, SSELCR);
 274         MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN));
 275
 276         w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
 277         w |= 1 << (mcbsp->id - 2);
 278         omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
 279 }
 280
 281 static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir)
 282 {
 283         u16 val, i;
 284         struct omap_device *od;
 285
 286         od = find_omap_device_by_dev(mcbsp->dev);
 287
 288         val = MCBSP_ST_READ(mcbsp, SSELCR);
 289
 290         if (val & ST_COEFFWREN)
 291                 MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
 292
 293         MCBSP_ST_WRITE(mcbsp, SSELCR, val | ST_COEFFWREN);
 294
 295         for (i = 0; i < 128; i++)
 296                 MCBSP_ST_WRITE(mcbsp, SFIRCR, fir[i]);
 297
 298         i = 0;
 299
 300         val = MCBSP_ST_READ(mcbsp, SSELCR);
 301         while (!(val & ST_COEFFWRDONE) && (++i < 1000))
 302                 val = MCBSP_ST_READ(mcbsp, SSELCR);
 303
 304         MCBSP_ST_WRITE(mcbsp, SSELCR, val & ~(ST_COEFFWREN));
 305
 306         if (i == 1000)
 307                 dev_err(mcbsp->dev, "McBSP FIR load error!\n");
 308 }
 309
 310 static void omap_st_chgain(struct omap_mcbsp *mcbsp)
 311 {
 312         u16 w;
 313         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 314         struct omap_device *od;
 315
 316         od = find_omap_device_by_dev(mcbsp->dev);
 317
 318         w = MCBSP_ST_READ(mcbsp, SSELCR);
 319
 320         MCBSP_ST_WRITE(mcbsp, SGAINCR, ST_CH0GAIN(st_data->ch0gain) | \
 321                       ST_CH1GAIN(st_data->ch1gain));
 322 }
 323
 324 int omap_st_set_chgain(unsigned int id, int channel, s16 chgain)
 325 {
 326         struct omap_mcbsp *mcbsp;
 327         struct omap_mcbsp_st_data *st_data;
 328         int ret = 0;
 329
 330         if (!omap_mcbsp_check_valid_id(id)) {
 331                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 332                 return -ENODEV;
 333         }
 334
 335         mcbsp = id_to_mcbsp_ptr(id);
 336         st_data = mcbsp->st_data;
 337
 338         if (!st_data)
 339                 return -ENOENT;
 340
 341         spin_lock_irq(&mcbsp->lock);
 342         if (channel == 0)
 343                 st_data->ch0gain = chgain;
 344         else if (channel == 1)
 345                 st_data->ch1gain = chgain;
 346         else
 347                 ret = -EINVAL;
 348
 349         if (st_data->enabled)
 350                 omap_st_chgain(mcbsp);
 351         spin_unlock_irq(&mcbsp->lock);
 352
 353         return ret;
 354 }
 355 EXPORT_SYMBOL(omap_st_set_chgain);
 356
 357 int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain)
 358 {
 359         struct omap_mcbsp *mcbsp;
 360         struct omap_mcbsp_st_data *st_data;
 361         int ret = 0;
 362
 363         if (!omap_mcbsp_check_valid_id(id)) {
 364                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 365                 return -ENODEV;
 366         }
 367
 368         mcbsp = id_to_mcbsp_ptr(id);
 369         st_data = mcbsp->st_data;
 370
 371         if (!st_data)
 372                 return -ENOENT;
 373
 374         spin_lock_irq(&mcbsp->lock);
 375         if (channel == 0)
 376                 *chgain = st_data->ch0gain;
 377         else if (channel == 1)
 378                 *chgain = st_data->ch1gain;
 379         else
 380                 ret = -EINVAL;
 381         spin_unlock_irq(&mcbsp->lock);
 382
 383         return ret;
 384 }
 385 EXPORT_SYMBOL(omap_st_get_chgain);
 386
 387 static int omap_st_start(struct omap_mcbsp *mcbsp)
 388 {
 389         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 390
 391         if (st_data && st_data->enabled && !st_data->running) {
 392                 omap_st_fir_write(mcbsp, st_data->taps);
 393                 omap_st_chgain(mcbsp);
 394
 395                 if (!mcbsp->free) {
 396                         omap_st_on(mcbsp);
 397                         st_data->running = 1;
 398                 }
 399         }
 400
 401         return 0;
 402 }
 403
 404 int omap_st_enable(unsigned int id)
 405 {
 406         struct omap_mcbsp *mcbsp;
 407         struct omap_mcbsp_st_data *st_data;
 408
 409         if (!omap_mcbsp_check_valid_id(id)) {
 410                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 411                 return -ENODEV;
 412         }
 413
 414         mcbsp = id_to_mcbsp_ptr(id);
 415         st_data = mcbsp->st_data;
 416
 417         if (!st_data)
 418                 return -ENODEV;
 419
 420         spin_lock_irq(&mcbsp->lock);
 421         st_data->enabled = 1;
 422         omap_st_start(mcbsp);
 423         spin_unlock_irq(&mcbsp->lock);
 424
 425         return 0;
 426 }
 427 EXPORT_SYMBOL(omap_st_enable);
 428
 429 static int omap_st_stop(struct omap_mcbsp *mcbsp)
 430 {
 431         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
 432
 433         if (st_data && st_data->running) {
 434                 if (!mcbsp->free) {
 435                         omap_st_off(mcbsp);
 436                         st_data->running = 0;
 437                 }
 438         }
 439
 440         return 0;
 441 }
 442
 443 int omap_st_disable(unsigned int id)
 444 {
 445         struct omap_mcbsp *mcbsp;
 446         struct omap_mcbsp_st_data *st_data;
 447         int ret = 0;
 448
 449         if (!omap_mcbsp_check_valid_id(id)) {
 450                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 451                 return -ENODEV;
 452         }
 453
 454         mcbsp = id_to_mcbsp_ptr(id);
 455         st_data = mcbsp->st_data;
 456
 457         if (!st_data)
 458                 return -ENODEV;
 459
 460         spin_lock_irq(&mcbsp->lock);
 461         omap_st_stop(mcbsp);
 462         st_data->enabled = 0;
 463         spin_unlock_irq(&mcbsp->lock);
 464
 465         return ret;
 466 }
 467 EXPORT_SYMBOL(omap_st_disable);
 468
 469 int omap_st_is_enabled(unsigned int id)
 470 {
 471         struct omap_mcbsp *mcbsp;
 472         struct omap_mcbsp_st_data *st_data;
 473
 474         if (!omap_mcbsp_check_valid_id(id)) {
 475                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 476                 return -ENODEV;
 477         }
 478
 479         mcbsp = id_to_mcbsp_ptr(id);
 480         st_data = mcbsp->st_data;
 481
 482         if (!st_data)
 483                 return -ENODEV;
 484
 485
 486         return st_data->enabled;
 487 }
 488 EXPORT_SYMBOL(omap_st_is_enabled);
 489
 490 /*
 491  * omap_mcbsp_set_rx_threshold configures the transmit threshold in words.
 492  * The threshold parameter is 1 based, and it is converted (threshold - 1)
 493  * for the THRSH2 register.
 494  */
 495 void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
 496 {
 497         struct omap_mcbsp *mcbsp;
 498
 499         if (!cpu_is_omap34xx() && !cpu_is_omap44xx())
 500                 return;
 501
 502         if (!omap_mcbsp_check_valid_id(id)) {
 503                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 504                 return;
 505         }
 506         mcbsp = id_to_mcbsp_ptr(id);
 507
 508         if (threshold && threshold <= mcbsp->max_tx_thres)
 509                 MCBSP_WRITE(mcbsp, THRSH2, threshold - 1);
 510 }
 511 EXPORT_SYMBOL(omap_mcbsp_set_tx_threshold);
 512
 513 /*
 514  * omap_mcbsp_set_rx_threshold configures the receive threshold in words.
 515  * The threshold parameter is 1 based, and it is converted (threshold - 1)
 516  * for the THRSH1 register.
 517  */
 518 void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
 519 {
 520         struct omap_mcbsp *mcbsp;
 521
 522         if (!cpu_is_omap34xx() && !cpu_is_omap44xx())
 523                 return;
 524
 525         if (!omap_mcbsp_check_valid_id(id)) {
 526                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 527                 return;
 528         }
 529         mcbsp = id_to_mcbsp_ptr(id);
 530
 531         if (threshold && threshold <= mcbsp->max_rx_thres)
 532                 MCBSP_WRITE(mcbsp, THRSH1, threshold - 1);
 533 }
 534 EXPORT_SYMBOL(omap_mcbsp_set_rx_threshold);
 535
 536 /*
 537  * omap_mcbsp_get_max_tx_thres just return the current configured
 538  * maximum threshold for transmission
 539  */
 540 u16 omap_mcbsp_get_max_tx_threshold(unsigned int id)
 541 {
 542         struct omap_mcbsp *mcbsp;
 543
 544         if (!omap_mcbsp_check_valid_id(id)) {
 545                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 546                 return -ENODEV;
 547         }
 548         mcbsp = id_to_mcbsp_ptr(id);
 549
 550         return mcbsp->max_tx_thres;
 551 }
 552 EXPORT_SYMBOL(omap_mcbsp_get_max_tx_threshold);
 553
 554 /*
 555  * omap_mcbsp_get_max_rx_thres just return the current configured
 556  * maximum threshold for reception
 557  */
 558 u16 omap_mcbsp_get_max_rx_threshold(unsigned int id)
 559 {
 560         struct omap_mcbsp *mcbsp;
 561
 562         if (!omap_mcbsp_check_valid_id(id)) {
 563                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 564                 return -ENODEV;
 565         }
 566         mcbsp = id_to_mcbsp_ptr(id);
 567
 568         return mcbsp->max_rx_thres;
 569 }
 570 EXPORT_SYMBOL(omap_mcbsp_get_max_rx_threshold);
 571
 572 u16 omap_mcbsp_get_fifo_size(unsigned int id)
 573 {
 574         struct omap_mcbsp *mcbsp;
 575
 576         if (!omap_mcbsp_check_valid_id(id)) {
 577                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 578                 return -ENODEV;
 579         }
 580         mcbsp = id_to_mcbsp_ptr(id);
 581
 582         return mcbsp->pdata->buffer_size;
 583 }
 584 EXPORT_SYMBOL(omap_mcbsp_get_fifo_size);
 585
 586 /*
 587  * omap_mcbsp_get_tx_delay returns the number of used slots in the McBSP FIFO
 588  */
 589 u16 omap_mcbsp_get_tx_delay(unsigned int id)
 590 {
 591         struct omap_mcbsp *mcbsp;
 592         u16 buffstat;
 593
 594         if (!omap_mcbsp_check_valid_id(id)) {
 595                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 596                 return -ENODEV;
 597         }
 598         mcbsp = id_to_mcbsp_ptr(id);
 599
 600         /* Returns the number of free locations in the buffer */
 601         buffstat = MCBSP_READ(mcbsp, XBUFFSTAT);
 602
 603         /* Number of slots are different in McBSP ports */
 604         return mcbsp->pdata->buffer_size - buffstat;
 605 }
 606 EXPORT_SYMBOL(omap_mcbsp_get_tx_delay);
 607
 608 /*
 609  * omap_mcbsp_get_rx_delay returns the number of free slots in the McBSP FIFO
 610  * to reach the threshold value (when the DMA will be triggered to read it)
 611  */
 612 u16 omap_mcbsp_get_rx_delay(unsigned int id)
 613 {
 614         struct omap_mcbsp *mcbsp;
 615         u16 buffstat, threshold;
 616
 617         if (!omap_mcbsp_check_valid_id(id)) {
 618                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 619                 return -ENODEV;
 620         }
 621         mcbsp = id_to_mcbsp_ptr(id);
 622
 623         /* Returns the number of used locations in the buffer */
 624         buffstat = MCBSP_READ(mcbsp, RBUFFSTAT);
 625         /* RX threshold */
 626         threshold = MCBSP_READ(mcbsp, THRSH1);
 627
 628         /* Return the number of location till we reach the threshold limit */
 629         if (threshold <= buffstat)
 630                 return 0;
 631         else
 632                 return threshold - buffstat;
 633 }
 634 EXPORT_SYMBOL(omap_mcbsp_get_rx_delay);
 635
 636 /*
 637  * omap_mcbsp_get_dma_op_mode just return the current configured
 638  * operating mode for the mcbsp channel
 639  */
 640 int omap_mcbsp_get_dma_op_mode(unsigned int id)
 641 {
 642         struct omap_mcbsp *mcbsp;
 643         int dma_op_mode;
 644
 645         if (!omap_mcbsp_check_valid_id(id)) {
 646                 printk(KERN_ERR "%s: Invalid id (%u)\n", __func__, id + 1);
 647                 return -ENODEV;
 648         }
 649         mcbsp = id_to_mcbsp_ptr(id);
 650
 651         dma_op_mode = mcbsp->dma_op_mode;
 652
 653         return dma_op_mode;
 654 }
 655 EXPORT_SYMBOL(omap_mcbsp_get_dma_op_mode);
 656
 657 static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp)
 658 {
 659         struct omap_device *od;
 660
 661         od = find_omap_device_by_dev(mcbsp->dev);
 662         /*
 663          * Enable wakup behavior, smart idle and all wakeups
 664          * REVISIT: some wakeups may be unnecessary
 665          */
 666         if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
 667                 MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
 668         }
 669 }
 670
 671 static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp)
 672 {
 673         struct omap_device *od;
 674
 675         od = find_omap_device_by_dev(mcbsp->dev);
 676
 677         /*
 678          * Disable wakup behavior, smart idle and all wakeups
 679          */
 680         if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
 681                 /*
 682                  * HW bug workaround - If no_idle mode is taken, we need to
 683                  * go to smart_idle before going to always_idle, or the
 684                  * device will not hit retention anymore.
 685                  */
 686
 687                 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
 688         }
 689 }
 690 #else
 691 static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp) {}
 692 static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp) {}
 693 static inline void omap_st_start(struct omap_mcbsp *mcbsp) {}
 694 static inline void omap_st_stop(struct omap_mcbsp *mcbsp) {}
 695 #endif
 696
 697 /*
 698  * We can choose between IRQ based or polled IO.
 699  * This needs to be called before omap_mcbsp_request().
 700  */
 701 int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type)
 702 {
 703         struct omap_mcbsp *mcbsp;
 704
 705         if (!omap_mcbsp_check_valid_id(id)) {
 706                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 707                 return -ENODEV;
 708         }
 709         mcbsp = id_to_mcbsp_ptr(id);
 710
 711         spin_lock(&mcbsp->lock);
 712
 713         if (!mcbsp->free) {
 714                 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
 715                         mcbsp->id);
 716                 spin_unlock(&mcbsp->lock);
 717                 return -EINVAL;
 718         }
 719
 720         mcbsp->io_type = io_type;
 721
 722         spin_unlock(&mcbsp->lock);
 723
 724         return 0;
 725 }
 726 EXPORT_SYMBOL(omap_mcbsp_set_io_type);
 727
 728 int omap_mcbsp_request(unsigned int id)
 729 {
 730         struct omap_mcbsp *mcbsp;
 731         void *reg_cache;
 732         int err;
 733
 734         if (!omap_mcbsp_check_valid_id(id)) {
 735                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 736                 return -ENODEV;
 737         }
 738         mcbsp = id_to_mcbsp_ptr(id);
 739
 740         reg_cache = kzalloc(omap_mcbsp_cache_size, GFP_KERNEL);
 741         if (!reg_cache) {
 742                 return -ENOMEM;
 743         }
 744
 745         spin_lock(&mcbsp->lock);
 746         if (!mcbsp->free) {
 747                 dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
 748                         mcbsp->id);
 749                 err = -EBUSY;
 750                 goto err_kfree;
 751         }
 752
 753         mcbsp->free = false;
 754         mcbsp->reg_cache = reg_cache;
 755         spin_unlock(&mcbsp->lock);
 756
 757         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
 758                 mcbsp->pdata->ops->request(id);
 759
 760         clk_enable(mcbsp->iclk);
 761         clk_enable(mcbsp->fclk);
 762
 763         /* Do procedure specific to omap34xx arch, if applicable */
 764         omap34xx_mcbsp_request(mcbsp);
 765
 766         /*
 767          * Make sure that transmitter, receiver and sample-rate generator are
 768          * not running before activating IRQs.
 769          */
 770         MCBSP_WRITE(mcbsp, SPCR1, 0);
 771         MCBSP_WRITE(mcbsp, SPCR2, 0);
 772
 773         if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
 774                 /* We need to get IRQs here */
 775                 init_completion(&mcbsp->tx_irq_completion);
 776                 err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler,
 777                                         0, "McBSP", (void *)mcbsp);
 778                 if (err != 0) {
 779                         dev_err(mcbsp->dev, "Unable to request TX IRQ %d "
 780                                         "for McBSP%d\n", mcbsp->tx_irq,
 781                                         mcbsp->id);
 782                         goto err_clk_disable;
 783                 }
 784
 785                 if (mcbsp->rx_irq) {
 786                         init_completion(&mcbsp->rx_irq_completion);
 787                         err = request_irq(mcbsp->rx_irq,
 788                                         omap_mcbsp_rx_irq_handler,
 789                                         0, "McBSP", (void *)mcbsp);
 790                         if (err != 0) {
 791                                 dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
 792                                                 "for McBSP%d\n", mcbsp->rx_irq,
 793                                                 mcbsp->id);
 794                                 goto err_free_irq;
 795                         }
 796                 }
 797         }
 798
 799         return 0;
 800 err_free_irq:
 801         free_irq(mcbsp->tx_irq, (void *)mcbsp);
 802 err_clk_disable:
 803         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
 804                 mcbsp->pdata->ops->free(id);
 805
 806         /* Do procedure specific to omap34xx arch, if applicable */
 807         omap34xx_mcbsp_free(mcbsp);
 808
 809         clk_disable(mcbsp->fclk);
 810         clk_disable(mcbsp->iclk);
 811
 812         spin_lock(&mcbsp->lock);
 813         mcbsp->free = true;
 814         mcbsp->reg_cache = NULL;
 815 err_kfree:
 816         spin_unlock(&mcbsp->lock);
 817         kfree(reg_cache);
 818
 819         return err;
 820 }
 821 EXPORT_SYMBOL(omap_mcbsp_request);
 822
 823 void omap_mcbsp_free(unsigned int id)
 824 {
 825         struct omap_mcbsp *mcbsp;
 826         void *reg_cache;
 827
 828         if (!omap_mcbsp_check_valid_id(id)) {
 829                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 830                 return;
 831         }
 832         mcbsp = id_to_mcbsp_ptr(id);
 833
 834         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
 835                 mcbsp->pdata->ops->free(id);
 836
 837         /* Do procedure specific to omap34xx arch, if applicable */
 838         omap34xx_mcbsp_free(mcbsp);
 839
 840         clk_disable(mcbsp->fclk);
 841         clk_disable(mcbsp->iclk);
 842
 843         if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
 844                 /* Free IRQs */
 845                 if (mcbsp->rx_irq)
 846                         free_irq(mcbsp->rx_irq, (void *)mcbsp);
 847                 free_irq(mcbsp->tx_irq, (void *)mcbsp);
 848         }
 849
 850         reg_cache = mcbsp->reg_cache;
 851
 852         spin_lock(&mcbsp->lock);
 853         if (mcbsp->free)
 854                 dev_err(mcbsp->dev, "McBSP%d was not reserved\n", mcbsp->id);
 855         else
 856                 mcbsp->free = true;
 857         mcbsp->reg_cache = NULL;
 858         spin_unlock(&mcbsp->lock);
 859
 860         if (reg_cache)
 861                 kfree(reg_cache);
 862 }
 863 EXPORT_SYMBOL(omap_mcbsp_free);
 864
 865 /*
 866  * Here we start the McBSP, by enabling transmitter, receiver or both.
 867  * If no transmitter or receiver is active prior calling, then sample-rate
 868  * generator and frame sync are started.
 869  */
 870 void omap_mcbsp_start(unsigned int id, int tx, int rx)
 871 {
 872         struct omap_mcbsp *mcbsp;
 873         int enable_srg = 0;
 874         u16 w;
 875
 876         if (!omap_mcbsp_check_valid_id(id)) {
 877                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 878                 return;
 879         }
 880         mcbsp = id_to_mcbsp_ptr(id);
 881
 882         if (cpu_is_omap34xx())
 883                 omap_st_start(mcbsp);
 884
 885         mcbsp->rx_word_length = (MCBSP_READ_CACHE(mcbsp, RCR1) >> 5) & 0x7;
 886         mcbsp->tx_word_length = (MCBSP_READ_CACHE(mcbsp, XCR1) >> 5) & 0x7;
 887
 888         /* Only enable SRG, if McBSP is master */
 889         w = MCBSP_READ_CACHE(mcbsp, PCR0);
 890         if (w & (FSXM | FSRM | CLKXM | CLKRM))
 891                 enable_srg = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
 892                                 MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
 893
 894         if (enable_srg) {
 895                 /* Start the sample generator */
 896                 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 897                 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 6));
 898         }
 899
 900         /* Enable transmitter and receiver */
 901         tx &= 1;
 902         w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 903         MCBSP_WRITE(mcbsp, SPCR2, w | tx);
 904
 905         rx &= 1;
 906         w = MCBSP_READ_CACHE(mcbsp, SPCR1);
 907         MCBSP_WRITE(mcbsp, SPCR1, w | rx);
 908
 909         /*
 910          * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
 911          * REVISIT: 100us may give enough time for two CLKSRG, however
 912          * due to some unknown PM related, clock gating etc. reason it
 913          * is now at 500us.
 914          */
 915         udelay(500);
 916
 917         if (enable_srg) {
 918                 /* Start frame sync */
 919                 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 920                 MCBSP_WRITE(mcbsp, SPCR2, w | (1 << 7));
 921         }
 922
 923         if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
 924                 /* Release the transmitter and receiver */
 925                 w = MCBSP_READ_CACHE(mcbsp, XCCR);
 926                 w &= ~(tx ? XDISABLE : 0);
 927                 MCBSP_WRITE(mcbsp, XCCR, w);
 928                 w = MCBSP_READ_CACHE(mcbsp, RCCR);
 929                 w &= ~(rx ? RDISABLE : 0);
 930                 MCBSP_WRITE(mcbsp, RCCR, w);
 931         }
 932
 933         /* Dump McBSP Regs */
 934         omap_mcbsp_dump_reg(id);
 935 }
 936 EXPORT_SYMBOL(omap_mcbsp_start);
 937
 938 void omap_mcbsp_stop(unsigned int id, int tx, int rx)
 939 {
 940         struct omap_mcbsp *mcbsp;
 941         int idle;
 942         u16 w;
 943
 944         if (!omap_mcbsp_check_valid_id(id)) {
 945                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 946                 return;
 947         }
 948
 949         mcbsp = id_to_mcbsp_ptr(id);
 950
 951         /* Reset transmitter */
 952         tx &= 1;
 953         if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
 954                 w = MCBSP_READ_CACHE(mcbsp, XCCR);
 955                 w |= (tx ? XDISABLE : 0);
 956                 MCBSP_WRITE(mcbsp, XCCR, w);
 957         }
 958         w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 959         MCBSP_WRITE(mcbsp, SPCR2, w & ~tx);
 960
 961         /* Reset receiver */
 962         rx &= 1;
 963         if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
 964                 w = MCBSP_READ_CACHE(mcbsp, RCCR);
 965                 w |= (rx ? RDISABLE : 0);
 966                 MCBSP_WRITE(mcbsp, RCCR, w);
 967         }
 968         w = MCBSP_READ_CACHE(mcbsp, SPCR1);
 969         MCBSP_WRITE(mcbsp, SPCR1, w & ~rx);
 970
 971         idle = !((MCBSP_READ_CACHE(mcbsp, SPCR2) |
 972                         MCBSP_READ_CACHE(mcbsp, SPCR1)) & 1);
 973
 974         if (idle) {
 975                 /* Reset the sample rate generator */
 976                 w = MCBSP_READ_CACHE(mcbsp, SPCR2);
 977                 MCBSP_WRITE(mcbsp, SPCR2, w & ~(1 << 6));
 978         }
 979
 980         if (cpu_is_omap34xx())
 981                 omap_st_stop(mcbsp);
 982 }
 983 EXPORT_SYMBOL(omap_mcbsp_stop);
 984
 985 /* polled mcbsp i/o operations */
 986 int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
 987 {
 988         struct omap_mcbsp *mcbsp;
 989
 990         if (!omap_mcbsp_check_valid_id(id)) {
 991                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
 992                 return -ENODEV;
 993         }
 994
 995         mcbsp = id_to_mcbsp_ptr(id);
 996
 997         MCBSP_WRITE(mcbsp, DXR1, buf);
 998         /* if frame sync error - clear the error */
 999         if (MCBSP_READ(mcbsp, SPCR2) & XSYNC_ERR) {
1000                 /* clear error */
1001                 MCBSP_WRITE(mcbsp, SPCR2, MCBSP_READ_CACHE(mcbsp, SPCR2));
1002                 /* resend */
1003                 return -1;
1004         } else {
1005                 /* wait for transmit confirmation */
1006                 int attemps = 0;
1007                 while (!(MCBSP_READ(mcbsp, SPCR2) & XRDY)) {
1008                         if (attemps++ > 1000) {
1009                                 MCBSP_WRITE(mcbsp, SPCR2,
1010                                                 MCBSP_READ_CACHE(mcbsp, SPCR2) &
1011                                                 (~XRST));
1012                                 udelay(10);
1013                                 MCBSP_WRITE(mcbsp, SPCR2,
1014                                                 MCBSP_READ_CACHE(mcbsp, SPCR2) |
1015                                                 (XRST));
1016                                 udelay(10);
1017                                 dev_err(mcbsp->dev, "Could not write to"
1018                                         " McBSP%d Register\n", mcbsp->id);
1019                                 return -2;
1020                         }
1021                 }
1022         }
1023
1024         return 0;
1025 }
1026 EXPORT_SYMBOL(omap_mcbsp_pollwrite);
1027
1028 int omap_mcbsp_pollread(unsigned int id, u16 *buf)
1029 {
1030         struct omap_mcbsp *mcbsp;
1031
1032         if (!omap_mcbsp_check_valid_id(id)) {
1033                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1034                 return -ENODEV;
1035         }
1036         mcbsp = id_to_mcbsp_ptr(id);
1037
1038         /* if frame sync error - clear the error */
1039         if (MCBSP_READ(mcbsp, SPCR1) & RSYNC_ERR) {
1040                 /* clear error */
1041                 MCBSP_WRITE(mcbsp, SPCR1, MCBSP_READ_CACHE(mcbsp, SPCR1));
1042                 /* resend */
1043                 return -1;
1044         } else {
1045                 /* wait for recieve confirmation */
1046                 int attemps = 0;
1047                 while (!(MCBSP_READ(mcbsp, SPCR1) & RRDY)) {
1048                         if (attemps++ > 1000) {
1049                                 MCBSP_WRITE(mcbsp, SPCR1,
1050                                                 MCBSP_READ_CACHE(mcbsp, SPCR1) &
1051                                                 (~RRST));
1052                                 udelay(10);
1053                                 MCBSP_WRITE(mcbsp, SPCR1,
1054                                                 MCBSP_READ_CACHE(mcbsp, SPCR1) |
1055                                                 (RRST));
1056                                 udelay(10);
1057                                 dev_err(mcbsp->dev, "Could not read from"
1058                                         " McBSP%d Register\n", mcbsp->id);
1059                                 return -2;
1060                         }
1061                 }
1062         }
1063         *buf = MCBSP_READ(mcbsp, DRR1);
1064
1065         return 0;
1066 }
1067 EXPORT_SYMBOL(omap_mcbsp_pollread);
1068
1069 /*
1070  * IRQ based word transmission.
1071  */
1072 void omap_mcbsp_xmit_word(unsigned int id, u32 word)
1073 {
1074         struct omap_mcbsp *mcbsp;
1075         omap_mcbsp_word_length word_length;
1076
1077         if (!omap_mcbsp_check_valid_id(id)) {
1078                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1079                 return;
1080         }
1081
1082         mcbsp = id_to_mcbsp_ptr(id);
1083         word_length = mcbsp->tx_word_length;
1084
1085         wait_for_completion(&mcbsp->tx_irq_completion);
1086
1087         if (word_length > OMAP_MCBSP_WORD_16)
1088                 MCBSP_WRITE(mcbsp, DXR2, word >> 16);
1089         MCBSP_WRITE(mcbsp, DXR1, word & 0xffff);
1090 }
1091 EXPORT_SYMBOL(omap_mcbsp_xmit_word);
1092
1093 u32 omap_mcbsp_recv_word(unsigned int id)
1094 {
1095         struct omap_mcbsp *mcbsp;
1096         u16 word_lsb, word_msb = 0;
1097         omap_mcbsp_word_length word_length;
1098
1099         if (!omap_mcbsp_check_valid_id(id)) {
1100                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1101                 return -ENODEV;
1102         }
1103         mcbsp = id_to_mcbsp_ptr(id);
1104
1105         word_length = mcbsp->rx_word_length;
1106
1107         wait_for_completion(&mcbsp->rx_irq_completion);
1108
1109         if (word_length > OMAP_MCBSP_WORD_16)
1110                 word_msb = MCBSP_READ(mcbsp, DRR2);
1111         word_lsb = MCBSP_READ(mcbsp, DRR1);
1112
1113         return (word_lsb | (word_msb << 16));
1114 }
1115 EXPORT_SYMBOL(omap_mcbsp_recv_word);
1116
1117 int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
1118 {
1119         struct omap_mcbsp *mcbsp;
1120         omap_mcbsp_word_length tx_word_length;
1121         omap_mcbsp_word_length rx_word_length;
1122         u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
1123
1124         if (!omap_mcbsp_check_valid_id(id)) {
1125                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1126                 return -ENODEV;
1127         }
1128         mcbsp = id_to_mcbsp_ptr(id);
1129         tx_word_length = mcbsp->tx_word_length;
1130         rx_word_length = mcbsp->rx_word_length;
1131
1132         if (tx_word_length != rx_word_length)
1133                 return -EINVAL;
1134
1135         /* First we wait for the transmitter to be ready */
1136         spcr2 = MCBSP_READ(mcbsp, SPCR2);
1137         while (!(spcr2 & XRDY)) {
1138                 spcr2 = MCBSP_READ(mcbsp, SPCR2);
1139                 if (attempts++ > 1000) {
1140                         /* We must reset the transmitter */
1141                         MCBSP_WRITE(mcbsp, SPCR2,
1142                                     MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XRST));
1143                         udelay(10);
1144                         MCBSP_WRITE(mcbsp, SPCR2,
1145                                     MCBSP_READ_CACHE(mcbsp, SPCR2) | XRST);
1146                         udelay(10);
1147                         dev_err(mcbsp->dev, "McBSP%d transmitter not "
1148                                 "ready\n", mcbsp->id);
1149                         return -EAGAIN;
1150                 }
1151         }
1152
1153         /* Now we can push the data */
1154         if (tx_word_length > OMAP_MCBSP_WORD_16)
1155                 MCBSP_WRITE(mcbsp, DXR2, word >> 16);
1156         MCBSP_WRITE(mcbsp, DXR1, word & 0xffff);
1157
1158         /* We wait for the receiver to be ready */
1159         spcr1 = MCBSP_READ(mcbsp, SPCR1);
1160         while (!(spcr1 & RRDY)) {
1161                 spcr1 = MCBSP_READ(mcbsp, SPCR1);
1162                 if (attempts++ > 1000) {
1163                         /* We must reset the receiver */
1164                         MCBSP_WRITE(mcbsp, SPCR1,
1165                                     MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RRST));
1166                         udelay(10);
1167                         MCBSP_WRITE(mcbsp, SPCR1,
1168                                     MCBSP_READ_CACHE(mcbsp, SPCR1) | RRST);
1169                         udelay(10);
1170                         dev_err(mcbsp->dev, "McBSP%d receiver not "
1171                                 "ready\n", mcbsp->id);
1172                         return -EAGAIN;
1173                 }
1174         }
1175
1176         /* Receiver is ready, let's read the dummy data */
1177         if (rx_word_length > OMAP_MCBSP_WORD_16)
1178                 word_msb = MCBSP_READ(mcbsp, DRR2);
1179         word_lsb = MCBSP_READ(mcbsp, DRR1);
1180
1181         return 0;
1182 }
1183 EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll);
1184
1185 int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
1186 {
1187         struct omap_mcbsp *mcbsp;
1188         u32 clock_word = 0;
1189         omap_mcbsp_word_length tx_word_length;
1190         omap_mcbsp_word_length rx_word_length;
1191         u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
1192
1193         if (!omap_mcbsp_check_valid_id(id)) {
1194                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1195                 return -ENODEV;
1196         }
1197
1198         mcbsp = id_to_mcbsp_ptr(id);
1199
1200         tx_word_length = mcbsp->tx_word_length;
1201         rx_word_length = mcbsp->rx_word_length;
1202
1203         if (tx_word_length != rx_word_length)
1204                 return -EINVAL;
1205
1206         /* First we wait for the transmitter to be ready */
1207         spcr2 = MCBSP_READ(mcbsp, SPCR2);
1208         while (!(spcr2 & XRDY)) {
1209                 spcr2 = MCBSP_READ(mcbsp, SPCR2);
1210                 if (attempts++ > 1000) {
1211                         /* We must reset the transmitter */
1212                         MCBSP_WRITE(mcbsp, SPCR2,
1213                                     MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XRST));
1214                         udelay(10);
1215                         MCBSP_WRITE(mcbsp, SPCR2,
1216                                     MCBSP_READ_CACHE(mcbsp, SPCR2) | XRST);
1217                         udelay(10);
1218                         dev_err(mcbsp->dev, "McBSP%d transmitter not "
1219                                 "ready\n", mcbsp->id);
1220                         return -EAGAIN;
1221                 }
1222         }
1223
1224         /* We first need to enable the bus clock */
1225         if (tx_word_length > OMAP_MCBSP_WORD_16)
1226                 MCBSP_WRITE(mcbsp, DXR2, clock_word >> 16);
1227         MCBSP_WRITE(mcbsp, DXR1, clock_word & 0xffff);
1228
1229         /* We wait for the receiver to be ready */
1230         spcr1 = MCBSP_READ(mcbsp, SPCR1);
1231         while (!(spcr1 & RRDY)) {
1232                 spcr1 = MCBSP_READ(mcbsp, SPCR1);
1233                 if (attempts++ > 1000) {
1234                         /* We must reset the receiver */
1235                         MCBSP_WRITE(mcbsp, SPCR1,
1236                                     MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RRST));
1237                         udelay(10);
1238                         MCBSP_WRITE(mcbsp, SPCR1,
1239                                     MCBSP_READ_CACHE(mcbsp, SPCR1) | RRST);
1240                         udelay(10);
1241                         dev_err(mcbsp->dev, "McBSP%d receiver not "
1242                                 "ready\n", mcbsp->id);
1243                         return -EAGAIN;
1244                 }
1245         }
1246
1247         /* Receiver is ready, there is something for us */
1248         if (rx_word_length > OMAP_MCBSP_WORD_16)
1249                 word_msb = MCBSP_READ(mcbsp, DRR2);
1250         word_lsb = MCBSP_READ(mcbsp, DRR1);
1251
1252         word[0] = (word_lsb | (word_msb << 16));
1253
1254         return 0;
1255 }
1256 EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll);
1257
1258 /*
1259  * Simple DMA based buffer rx/tx routines.
1260  * Nothing fancy, just a single buffer tx/rx through DMA.
1261  * The DMA resources are released once the transfer is done.
1262  * For anything fancier, you should use your own customized DMA
1263  * routines and callbacks.
1264  */
1265 int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer,
1266                                 unsigned int length)
1267 {
1268         struct omap_mcbsp *mcbsp;
1269         int dma_tx_ch;
1270         int src_port = 0;
1271         int dest_port = 0;
1272         int sync_dev = 0;
1273
1274         if (!omap_mcbsp_check_valid_id(id)) {
1275                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1276                 return -ENODEV;
1277         }
1278         mcbsp = id_to_mcbsp_ptr(id);
1279
1280         if (omap_request_dma(mcbsp->dma_tx_sync, "McBSP TX",
1281                                 omap_mcbsp_tx_dma_callback,
1282                                 mcbsp,
1283                                 &dma_tx_ch)) {
1284                 dev_err(mcbsp->dev, " Unable to request DMA channel for "
1285                                 "McBSP%d TX. Trying IRQ based TX\n",
1286                                 mcbsp->id);
1287                 return -EAGAIN;
1288         }
1289         mcbsp->dma_tx_lch = dma_tx_ch;
1290
1291         dev_err(mcbsp->dev, "McBSP%d TX DMA on channel %d\n", mcbsp->id,
1292                 dma_tx_ch);
1293
1294         init_completion(&mcbsp->tx_dma_completion);
1295
1296         if (cpu_class_is_omap1()) {
1297                 src_port = OMAP_DMA_PORT_TIPB;
1298                 dest_port = OMAP_DMA_PORT_EMIFF;
1299         }
1300         if (cpu_class_is_omap2())
1301                 sync_dev = mcbsp->dma_tx_sync;
1302
1303         omap_set_dma_transfer_params(mcbsp->dma_tx_lch,
1304                                      OMAP_DMA_DATA_TYPE_S16,
1305                                      length >> 1, 1,
1306                                      OMAP_DMA_SYNC_ELEMENT,
1307          sync_dev, 0);
1308
1309         omap_set_dma_dest_params(mcbsp->dma_tx_lch,
1310                                  src_port,
1311                                  OMAP_DMA_AMODE_CONSTANT,
1312                                  mcbsp->phys_base + OMAP_MCBSP_REG_DXR1,
1313                                  0, 0);
1314
1315         omap_set_dma_src_params(mcbsp->dma_tx_lch,
1316                                 dest_port,
1317                                 OMAP_DMA_AMODE_POST_INC,
1318                                 buffer,
1319                                 0, 0);
1320
1321         omap_start_dma(mcbsp->dma_tx_lch);
1322         wait_for_completion(&mcbsp->tx_dma_completion);
1323
1324         return 0;
1325 }
1326 EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
1327
1328 int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer,
1329                                 unsigned int length)
1330 {
1331         struct omap_mcbsp *mcbsp;
1332         int dma_rx_ch;
1333         int src_port = 0;
1334         int dest_port = 0;
1335         int sync_dev = 0;
1336
1337         if (!omap_mcbsp_check_valid_id(id)) {
1338                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1339                 return -ENODEV;
1340         }
1341         mcbsp = id_to_mcbsp_ptr(id);
1342
1343         if (omap_request_dma(mcbsp->dma_rx_sync, "McBSP RX",
1344                                 omap_mcbsp_rx_dma_callback,
1345                                 mcbsp,
1346                                 &dma_rx_ch)) {
1347                 dev_err(mcbsp->dev, "Unable to request DMA channel for "
1348                                 "McBSP%d RX. Trying IRQ based RX\n",
1349                                 mcbsp->id);
1350                 return -EAGAIN;
1351         }
1352         mcbsp->dma_rx_lch = dma_rx_ch;
1353
1354         dev_err(mcbsp->dev, "McBSP%d RX DMA on channel %d\n", mcbsp->id,
1355                 dma_rx_ch);
1356
1357         init_completion(&mcbsp->rx_dma_completion);
1358
1359         if (cpu_class_is_omap1()) {
1360                 src_port = OMAP_DMA_PORT_TIPB;
1361                 dest_port = OMAP_DMA_PORT_EMIFF;
1362         }
1363         if (cpu_class_is_omap2())
1364                 sync_dev = mcbsp->dma_rx_sync;
1365
1366         omap_set_dma_transfer_params(mcbsp->dma_rx_lch,
1367                                         OMAP_DMA_DATA_TYPE_S16,
1368                                         length >> 1, 1,
1369                                         OMAP_DMA_SYNC_ELEMENT,
1370                                         sync_dev, 0);
1371
1372         omap_set_dma_src_params(mcbsp->dma_rx_lch,
1373                                 src_port,
1374                                 OMAP_DMA_AMODE_CONSTANT,
1375                                 mcbsp->phys_base + OMAP_MCBSP_REG_DRR1,
1376                                 0, 0);
1377
1378         omap_set_dma_dest_params(mcbsp->dma_rx_lch,
1379                                         dest_port,
1380                                         OMAP_DMA_AMODE_POST_INC,
1381                                         buffer,
1382                                         0, 0);
1383
1384         omap_start_dma(mcbsp->dma_rx_lch);
1385         wait_for_completion(&mcbsp->rx_dma_completion);
1386
1387         return 0;
1388 }
1389 EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
1390
1391 /*
1392  * SPI wrapper.
1393  * Since SPI setup is much simpler than the generic McBSP one,
1394  * this wrapper just need an omap_mcbsp_spi_cfg structure as an input.
1395  * Once this is done, you can call omap_mcbsp_start().
1396  */
1397 void omap_mcbsp_set_spi_mode(unsigned int id,
1398                                 const struct omap_mcbsp_spi_cfg *spi_cfg)
1399 {
1400         struct omap_mcbsp *mcbsp;
1401         struct omap_mcbsp_reg_cfg mcbsp_cfg;
1402
1403         if (!omap_mcbsp_check_valid_id(id)) {
1404                 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
1405                 return;
1406         }
1407         mcbsp = id_to_mcbsp_ptr(id);
1408
1409         memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg));
1410
1411         /* SPI has only one frame */
1412         mcbsp_cfg.rcr1 |= (RWDLEN1(spi_cfg->word_length) | RFRLEN1(0));
1413         mcbsp_cfg.xcr1 |= (XWDLEN1(spi_cfg->word_length) | XFRLEN1(0));
1414
1415         /* Clock stop mode */
1416         if (spi_cfg->clk_stp_mode == OMAP_MCBSP_CLK_STP_MODE_NO_DELAY)
1417                 mcbsp_cfg.spcr1 |= (1 << 12);
1418         else
1419                 mcbsp_cfg.spcr1 |= (3 << 11);
1420
1421         /* Set clock parities */
1422         if (spi_cfg->rx_clock_polarity == OMAP_MCBSP_CLK_RISING)
1423                 mcbsp_cfg.pcr0 |= CLKRP;
1424         else
1425                 mcbsp_cfg.pcr0 &= ~CLKRP;
1426
1427         if (spi_cfg->tx_clock_polarity == OMAP_MCBSP_CLK_RISING)
1428                 mcbsp_cfg.pcr0 &= ~CLKXP;
1429         else
1430                 mcbsp_cfg.pcr0 |= CLKXP;
1431
1432         /* Set SCLKME to 0 and CLKSM to 1 */
1433         mcbsp_cfg.pcr0 &= ~SCLKME;
1434         mcbsp_cfg.srgr2 |= CLKSM;
1435
1436         /* Set FSXP */
1437         if (spi_cfg->fsx_polarity == OMAP_MCBSP_FS_ACTIVE_HIGH)
1438                 mcbsp_cfg.pcr0 &= ~FSXP;
1439         else
1440                 mcbsp_cfg.pcr0 |= FSXP;
1441
1442         if (spi_cfg->spi_mode == OMAP_MCBSP_SPI_MASTER) {
1443                 mcbsp_cfg.pcr0 |= CLKXM;
1444                 mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div - 1);
1445                 mcbsp_cfg.pcr0 |= FSXM;
1446                 mcbsp_cfg.srgr2 &= ~FSGM;
1447                 mcbsp_cfg.xcr2 |= XDATDLY(1);
1448                 mcbsp_cfg.rcr2 |= RDATDLY(1);
1449         } else {
1450                 mcbsp_cfg.pcr0 &= ~CLKXM;
1451                 mcbsp_cfg.srgr1 |= CLKGDV(1);
1452                 mcbsp_cfg.pcr0 &= ~FSXM;
1453                 mcbsp_cfg.xcr2 &= ~XDATDLY(3);
1454                 mcbsp_cfg.rcr2 &= ~RDATDLY(3);
1455         }
1456
1457         mcbsp_cfg.xcr2 &= ~XPHASE;
1458         mcbsp_cfg.rcr2 &= ~RPHASE;
1459
1460         omap_mcbsp_config(id, &mcbsp_cfg);
1461 }
1462 EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);
1463
1464 #ifdef CONFIG_ARCH_OMAP3
1465 #define max_thres(m)                    (mcbsp->pdata->buffer_size)
1466 #define valid_threshold(m, val)         ((val) <= max_thres(m))
1467 #define THRESHOLD_PROP_BUILDER(prop)                                    \
1468 static ssize_t prop##_show(struct device *dev,                          \
1469                         struct device_attribute *attr, char *buf)       \
1470 {                                                                       \
1471         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);                \
1472                                                                         \
1473         return sprintf(buf, "%u\n", mcbsp->prop);                       \
1474 }                                                                       \
1475                                                                         \
1476 static ssize_t prop##_store(struct device *dev,                         \
1477                                 struct device_attribute *attr,          \
1478                                 const char *buf, size_t size)           \
1479 {                                                                       \
1480         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);                \
1481         unsigned long val;                                              \
1482         int status;                                                     \
1483                                                                         \
1484         status = strict_strtoul(buf, 0, &val);                          \
1485         if (status)                                                     \
1486                 return status;                                          \
1487                                                                         \
1488         if (!valid_threshold(mcbsp, val))                               \
1489                 return -EDOM;                                           \
1490                                                                         \
1491         mcbsp->prop = val;                                              \
1492         return size;                                                    \
1493 }                                                                       \
1494                                                                         \
1495 static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store);
1496
1497 THRESHOLD_PROP_BUILDER(max_tx_thres);
1498 THRESHOLD_PROP_BUILDER(max_rx_thres);
1499
1500 static const char *dma_op_modes[] = {
1501         "element", "threshold", "frame",
1502 };
1503
1504 static ssize_t dma_op_mode_show(struct device *dev,
1505                         struct device_attribute *attr, char *buf)
1506 {
1507         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1508         int dma_op_mode, i = 0;
1509         ssize_t len = 0;
1510         const char * const *s;
1511
1512         dma_op_mode = mcbsp->dma_op_mode;
1513
1514         for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) {
1515                 if (dma_op_mode == i)
1516                         len += sprintf(buf + len, "[%s] ", *s);
1517                 else
1518                         len += sprintf(buf + len, "%s ", *s);
1519         }
1520         len += sprintf(buf + len, "\n");
1521
1522         return len;
1523 }
1524
1525 static ssize_t dma_op_mode_store(struct device *dev,
1526                                 struct device_attribute *attr,
1527                                 const char *buf, size_t size)
1528 {
1529         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1530         const char * const *s;
1531         int i = 0;
1532
1533         for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++)
1534                 if (sysfs_streq(buf, *s))
1535                         break;
1536
1537         if (i == ARRAY_SIZE(dma_op_modes))
1538                 return -EINVAL;
1539
1540         spin_lock_irq(&mcbsp->lock);
1541         if (!mcbsp->free) {
1542                 size = -EBUSY;
1543                 goto unlock;
1544         }
1545         mcbsp->dma_op_mode = i;
1546
1547 unlock:
1548         spin_unlock_irq(&mcbsp->lock);
1549
1550         return size;
1551 }
1552
1553 static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store);
1554
1555 static ssize_t st_taps_show(struct device *dev,
1556                             struct device_attribute *attr, char *buf)
1557 {
1558         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1559         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1560         ssize_t status = 0;
1561         int i;
1562
1563         spin_lock_irq(&mcbsp->lock);
1564         for (i = 0; i < st_data->nr_taps; i++)
1565                 status += sprintf(&buf[status], (i ? ", %d" : "%d"),
1566                                   st_data->taps[i]);
1567         if (i)
1568                 status += sprintf(&buf[status], "\n");
1569         spin_unlock_irq(&mcbsp->lock);
1570
1571         return status;
1572 }
1573
1574 static ssize_t st_taps_store(struct device *dev,
1575                              struct device_attribute *attr,
1576                              const char *buf, size_t size)
1577 {
1578         struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
1579         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1580         int val, tmp, status, i = 0;
1581
1582         spin_lock_irq(&mcbsp->lock);
1583         memset(st_data->taps, 0, sizeof(st_data->taps));
1584         st_data->nr_taps = 0;
1585
1586         do {
1587                 status = sscanf(buf, "%d%n", &val, &tmp);
1588                 if (status < 0 || status == 0) {
1589                         size = -EINVAL;
1590                         goto out;
1591                 }
1592                 if (val < -32768 || val > 32767) {
1593                         size = -EINVAL;
1594                         goto out;
1595                 }
1596                 st_data->taps[i++] = val;
1597                 buf += tmp;
1598                 if (*buf != ',')
1599                         break;
1600                 buf++;
1601         } while (1);
1602
1603         st_data->nr_taps = i;
1604
1605 out:
1606         spin_unlock_irq(&mcbsp->lock);
1607
1608         return size;
1609 }
1610
1611 static DEVICE_ATTR(st_taps, 0644, st_taps_show, st_taps_store);
1612
1613 static const struct attribute *additional_attrs[] = {
1614         &dev_attr_max_tx_thres.attr,
1615         &dev_attr_max_rx_thres.attr,
1616         &dev_attr_dma_op_mode.attr,
1617         NULL,
1618 };
1619
1620 static const struct attribute_group additional_attr_group = {
1621         .attrs = (struct attribute **)additional_attrs,
1622 };
1623
1624 static inline int __devinit omap_additional_add(struct device *dev)
1625 {
1626         return sysfs_create_group(&dev->kobj, &additional_attr_group);
1627 }
1628
1629 static inline void __devexit omap_additional_remove(struct device *dev)
1630 {
1631         sysfs_remove_group(&dev->kobj, &additional_attr_group);
1632 }
1633
1634 static const struct attribute *sidetone_attrs[] = {
1635         &dev_attr_st_taps.attr,
1636         NULL,
1637 };
1638
1639 static const struct attribute_group sidetone_attr_group = {
1640         .attrs = (struct attribute **)sidetone_attrs,
1641 };
1642
1643 static int __devinit omap_st_add(struct omap_mcbsp *mcbsp)
1644 {
1645         struct platform_device *pdev;
1646         struct resource *res;
1647         struct omap_mcbsp_st_data *st_data;
1648         int err;
1649
1650         st_data = kzalloc(sizeof(*mcbsp->st_data), GFP_KERNEL);
1651         if (!st_data) {
1652                 err = -ENOMEM;
1653                 goto err1;
1654         }
1655
1656         pdev = container_of(mcbsp->dev, struct platform_device, dev);
1657
1658         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sidetone");
1659         st_data->io_base_st = ioremap(res->start, resource_size(res));
1660         if (!st_data->io_base_st) {
1661                 err = -ENOMEM;
1662                 goto err2;
1663         }
1664
1665         err = sysfs_create_group(&mcbsp->dev->kobj, &sidetone_attr_group);
1666         if (err)
1667                 goto err3;
1668
1669         mcbsp->st_data = st_data;
1670         return 0;
1671
1672 err3:
1673         iounmap(st_data->io_base_st);
1674 err2:
1675         kfree(st_data);
1676 err1:
1677         return err;
1678
1679 }
1680
1681 static void __devexit omap_st_remove(struct omap_mcbsp *mcbsp)
1682 {
1683         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
1684
1685         if (st_data) {
1686                 sysfs_remove_group(&mcbsp->dev->kobj, &sidetone_attr_group);
1687                 iounmap(st_data->io_base_st);
1688                 kfree(st_data);
1689         }
1690 }
1691
1692 static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp)
1693 {
1694         mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
1695         if (cpu_is_omap34xx()) {
1696                 /*
1697                  * Initially configure the maximum thresholds to a safe value.
1698                  * The McBSP FIFO usage with these values should not go under
1699                  * 16 locations.
1700                  * If the whole FIFO without safety buffer is used, than there
1701                  * is a possibility that the DMA will be not able to push the
1702                  * new data on time, causing channel shifts in runtime.
1703                  */
1704                 mcbsp->max_tx_thres = max_thres(mcbsp) - 0x10;
1705                 mcbsp->max_rx_thres = max_thres(mcbsp) - 0x10;
1706                 /*
1707                  * REVISIT: Set dmap_op_mode to THRESHOLD as default
1708                  * for mcbsp2 instances.
1709                  */
1710                 if (omap_additional_add(mcbsp->dev))
1711                         dev_warn(mcbsp->dev,
1712                                 "Unable to create additional controls\n");
1713
1714                 if (mcbsp->id == 2 || mcbsp->id == 3)
1715                         if (omap_st_add(mcbsp))
1716                                 dev_warn(mcbsp->dev,
1717                                  "Unable to create sidetone controls\n");
1718
1719         } else {
1720                 mcbsp->max_tx_thres = -EINVAL;
1721                 mcbsp->max_rx_thres = -EINVAL;
1722         }
1723 }
1724
1725 static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp)
1726 {
1727         if (cpu_is_omap34xx()) {
1728                 omap_additional_remove(mcbsp->dev);
1729
1730                 if (mcbsp->id == 2 || mcbsp->id == 3)
1731                         omap_st_remove(mcbsp);
1732         }
1733 }
1734 #else
1735 static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp) {}
1736 static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp) {}
1737 #endif /* CONFIG_ARCH_OMAP3 */
1738
1739 /*
1740  * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
1741  * 730 has only 2 McBSP, and both of them are MPU peripherals.
1742  */
1743 static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
1744 {
1745         struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data;
1746         struct omap_mcbsp *mcbsp;
1747         int id = pdev->id - 1;
1748         struct resource *res;
1749         int ret = 0;
1750
1751         if (!pdata) {
1752                 dev_err(&pdev->dev, "McBSP device initialized without"
1753                                 "platform data\n");
1754                 ret = -EINVAL;
1755                 goto exit;
1756         }
1757
1758         dev_dbg(&pdev->dev, "Initializing OMAP McBSP (%d).\n", pdev->id);
1759
1760         if (id >= omap_mcbsp_count) {
1761                 dev_err(&pdev->dev, "Invalid McBSP device id (%d)\n", id);
1762                 ret = -EINVAL;
1763                 goto exit;
1764         }
1765
1766         mcbsp = kzalloc(sizeof(struct omap_mcbsp), GFP_KERNEL);
1767         if (!mcbsp) {
1768                 ret = -ENOMEM;
1769                 goto exit;
1770         }
1771
1772         spin_lock_init(&mcbsp->lock);
1773         mcbsp->id = id + 1;
1774         mcbsp->free = true;
1775         mcbsp->dma_tx_lch = -1;
1776         mcbsp->dma_rx_lch = -1;
1777
1778         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
1779         if (!res) {
1780                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1781                 if (!res) {
1782                         dev_err(&pdev->dev, "%s:mcbsp%d has invalid memory"
1783                                         "resource\n", __func__, pdev->id);
1784                         ret = -ENOMEM;
1785                         goto exit;
1786                 }
1787         }
1788         mcbsp->phys_base = res->start;
1789         omap_mcbsp_cache_size = resource_size(res);
1790         mcbsp->io_base = ioremap(res->start, resource_size(res));
1791         if (!mcbsp->io_base) {
1792                 ret = -ENOMEM;
1793                 goto err_ioremap;
1794         }
1795
1796         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
1797         if (!res)
1798                 mcbsp->phys_dma_base = mcbsp->phys_base;
1799         else
1800                 mcbsp->phys_dma_base = res->start;
1801
1802         /* Default I/O is IRQ based */
1803         mcbsp->io_type = OMAP_MCBSP_IRQ_IO;
1804
1805         mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx");
1806         mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx");
1807
1808         /* From OMAP4 there will be a single irq line */
1809         if (mcbsp->tx_irq == -ENXIO)
1810                 mcbsp->tx_irq = platform_get_irq(pdev, 0);
1811
1812         res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1813         if (!res) {
1814                 dev_err(&pdev->dev, "%s:mcbsp%d has invalid rx DMA channel\n",
1815                                         __func__, pdev->id);
1816                 ret = -ENODEV;
1817                 goto err_res;
1818         }
1819         mcbsp->dma_rx_sync = res->start;
1820
1821         res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1822         if (!res) {
1823                 dev_err(&pdev->dev, "%s:mcbsp%d has invalid tx DMA channel\n",
1824                                         __func__, pdev->id);
1825                 ret = -ENODEV;
1826                 goto err_res;
1827         }
1828         mcbsp->dma_tx_sync = res->start;
1829
1830         mcbsp->iclk = clk_get(&pdev->dev, "ick");
1831         if (IS_ERR(mcbsp->iclk)) {
1832                 ret = PTR_ERR(mcbsp->iclk);
1833                 dev_err(&pdev->dev, "unable to get ick: %d\n", ret);
1834                 goto err_res;
1835         }
1836
1837         mcbsp->fclk = clk_get(&pdev->dev, "fck");
1838         if (IS_ERR(mcbsp->fclk)) {
1839                 ret = PTR_ERR(mcbsp->fclk);
1840                 dev_err(&pdev->dev, "unable to get fck: %d\n", ret);
1841                 goto err_fclk;
1842         }
1843
1844         mcbsp->pdata = pdata;
1845         mcbsp->dev = &pdev->dev;
1846         mcbsp_ptr[id] = mcbsp;
1847         platform_set_drvdata(pdev, mcbsp);
1848
1849         /* Initialize mcbsp properties for OMAP34XX if needed / applicable */
1850         omap34xx_device_init(mcbsp);
1851
1852         return 0;
1853
1854 err_fclk:
1855         clk_put(mcbsp->iclk);
1856 err_res:
1857         iounmap(mcbsp->io_base);
1858 err_ioremap:
1859         kfree(mcbsp);
1860 exit:
1861         return ret;
1862 }
1863
1864 static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
1865 {
1866         struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
1867
1868         platform_set_drvdata(pdev, NULL);
1869         if (mcbsp) {
1870
1871                 if (mcbsp->pdata && mcbsp->pdata->ops &&
1872                                 mcbsp->pdata->ops->free)
1873                         mcbsp->pdata->ops->free(mcbsp->id);
1874
1875                 omap34xx_device_exit(mcbsp);
1876
1877                 clk_put(mcbsp->fclk);
1878                 clk_put(mcbsp->iclk);
1879
1880                 iounmap(mcbsp->io_base);
1881                 kfree(mcbsp);
1882         }
1883
1884         return 0;
1885 }
1886
1887 static struct platform_driver omap_mcbsp_driver = {
1888         .probe          = omap_mcbsp_probe,
1889         .remove         = __devexit_p(omap_mcbsp_remove),
1890         .driver         = {
1891                 .name   = "omap-mcbsp",
1892         },
1893 };
1894
1895 int __init omap_mcbsp_init(void)
1896 {
1897         /* Register the McBSP driver */
1898         return platform_driver_register(&omap_mcbsp_driver);
1899 }