arch/arm/plat-omap/include/plat/mux.h

   1 /*
   2  * arch/arm/plat-omap/include/mach/mux.h
   3  *
   4  * Table of the Omap register configurations for the FUNC_MUX and
   5  * PULL_DWN combinations.
   6  *
   7  * Copyright (C) 2004 - 2008 Texas Instruments Inc.
   8  * Copyright (C) 2003 - 2008 Nokia Corporation
   9  *
  10  * Written by Tony Lindgren
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; either version 2 of the License, or
  15  * (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  25  *
  26  * NOTE: Please use the following naming style for new pin entries.
  27  *       For example, W8_1610_MMC2_DAT0, where:
  28  *       - W8        = ball
  29  *       - 1610      = 1510 or 1610, none if common for both 1510 and 1610
  30  *       - MMC2_DAT0 = function
  31  */
  32
  33 #ifndef __ASM_ARCH_MUX_H
  34 #define __ASM_ARCH_MUX_H
  35
  36 #define PU_PD_SEL_NA            0       /* No pu_pd reg available */
  37 #define PULL_DWN_CTRL_NA        0       /* No pull-down control needed */
  38
  39 #ifdef  CONFIG_OMAP_MUX_DEBUG
  40 #define MUX_REG(reg, mode_offset, mode) .mux_reg_name = "FUNC_MUX_CTRL_"#reg, \
  41                                         .mux_reg = FUNC_MUX_CTRL_##reg, \
  42                                         .mask_offset = mode_offset, \
  43                                         .mask = mode,
  44
  45 #define PULL_REG(reg, bit, status)      .pull_name = "PULL_DWN_CTRL_"#reg, \
  46                                         .pull_reg = PULL_DWN_CTRL_##reg, \
  47                                         .pull_bit = bit, \
  48                                         .pull_val = status,
  49
  50 #define PU_PD_REG(reg, status)          .pu_pd_name = "PU_PD_SEL_"#reg, \
  51                                         .pu_pd_reg = PU_PD_SEL_##reg, \
  52                                         .pu_pd_val = status,
  53
  54 #define MUX_REG_7XX(reg, mode_offset, mode) .mux_reg_name = "OMAP7XX_IO_CONF_"#reg, \
  55                                         .mux_reg = OMAP7XX_IO_CONF_##reg, \
  56                                         .mask_offset = mode_offset, \
  57                                         .mask = mode,
  58
  59 #define PULL_REG_7XX(reg, bit, status)  .pull_name = "OMAP7XX_IO_CONF_"#reg, \
  60                                         .pull_reg = OMAP7XX_IO_CONF_##reg, \
  61                                         .pull_bit = bit, \
  62                                         .pull_val = status,
  63
  64 #else
  65
  66 #define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \
  67                                         .mask_offset = mode_offset, \
  68                                         .mask = mode,
  69
  70 #define PULL_REG(reg, bit, status)      .pull_reg = PULL_DWN_CTRL_##reg, \
  71                                         .pull_bit = bit, \
  72                                         .pull_val = status,
  73
  74 #define PU_PD_REG(reg, status)          .pu_pd_reg = PU_PD_SEL_##reg, \
  75                                         .pu_pd_val = status,
  76
  77 #define MUX_REG_7XX(reg, mode_offset, mode) \
  78                                         .mux_reg = OMAP7XX_IO_CONF_##reg, \
  79                                         .mask_offset = mode_offset, \
  80                                         .mask = mode,
  81
  82 #define PULL_REG_7XX(reg, bit, status)  .pull_reg = OMAP7XX_IO_CONF_##reg, \
  83                                         .pull_bit = bit, \
  84                                         .pull_val = status,
  85
  86 #endif /* CONFIG_OMAP_MUX_DEBUG */
  87
  88 #define MUX_CFG(desc, mux_reg, mode_offset, mode,       \
  89                 pull_reg, pull_bit, pull_status,        \
  90                 pu_pd_reg, pu_pd_status, debug_status)  \
  91 {                                                       \
  92         .name =  desc,                                  \
  93         .debug = debug_status,                          \
  94         MUX_REG(mux_reg, mode_offset, mode)             \
  95         PULL_REG(pull_reg, pull_bit, pull_status)       \
  96         PU_PD_REG(pu_pd_reg, pu_pd_status)              \
  97 },
  98
  99
 100 /*
 101  * OMAP730/850 has a slightly different config for the pin mux.
 102  * - config regs are the OMAP7XX_IO_CONF_x regs (see omap730.h) regs and
 103  *   not the FUNC_MUX_CTRL_x regs from hardware.h
 104  * - for pull-up/down, only has one enable bit which is is in the same register
 105  *   as mux config
 106  */
 107 #define MUX_CFG_7XX(desc, mux_reg, mode_offset, mode,   \
 108                    pull_bit, pull_status, debug_status)\
 109 {                                                       \
 110         .name =  desc,                                  \
 111         .debug = debug_status,                          \
 112         MUX_REG_7XX(mux_reg, mode_offset, mode)         \
 113         PULL_REG_7XX(mux_reg, pull_bit, pull_status)    \
 114         PU_PD_REG(NA, 0)                \
 115 },
 116
 117 #define MUX_CFG_24XX(desc, reg_offset, mode,                    \
 118                                 pull_en, pull_mode, dbg)        \
 119 {                                                               \
 120         .name           = desc,                                 \
 121         .debug          = dbg,                                  \
 122         .mux_reg        = reg_offset,                           \
 123         .mask           = mode,                                 \
 124         .pull_val       = pull_en,                              \
 125         .pu_pd_val      = pull_mode,                            \
 126 },
 127
 128 /* 24xx/34xx mux bit defines */
 129 #define OMAP2_PULL_ENA          (1 << 3)
 130 #define OMAP2_PULL_UP           (1 << 4)
 131 #define OMAP2_ALTELECTRICALSEL  (1 << 5)
 132
 133 struct pin_config {
 134         char                    *name;
 135         const unsigned int      mux_reg;
 136         unsigned char           debug;
 137
 138 #if     defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP24XX)
 139         const unsigned char mask_offset;
 140         const unsigned char mask;
 141
 142         const char *pull_name;
 143         const unsigned int pull_reg;
 144         const unsigned char pull_val;
 145         const unsigned char pull_bit;
 146
 147         const char *pu_pd_name;
 148         const unsigned int pu_pd_reg;
 149         const unsigned char pu_pd_val;
 150 #endif
 151
 152 #if     defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
 153         const char *mux_reg_name;
 154 #endif
 155
 156 };
 157
 158 enum omap7xx_index {
 159         /* OMAP 730 keyboard */
 160         E2_7XX_KBR0,
 161         J7_7XX_KBR1,
 162         E1_7XX_KBR2,
 163         F3_7XX_KBR3,
 164         D2_7XX_KBR4,
 165         C2_7XX_KBC0,
 166         D3_7XX_KBC1,
 167         E4_7XX_KBC2,
 168         F4_7XX_KBC3,
 169         E3_7XX_KBC4,
 170
 171         /* USB */
 172         AA17_7XX_USB_DM,
 173         W16_7XX_USB_PU_EN,
 174         W17_7XX_USB_VBUSI,
 175         W18_7XX_USB_DMCK_OUT,
 176         W19_7XX_USB_DCRST,
 177
 178         /* MMC */
 179         MMC_7XX_CMD,
 180         MMC_7XX_CLK,
 181         MMC_7XX_DAT0,
 182
 183         /* I2C */
 184         I2C_7XX_SCL,
 185         I2C_7XX_SDA,
 186 };
 187
 188 enum omap1xxx_index {
 189         /* UART1 (BT_UART_GATING)*/
 190         UART1_TX = 0,
 191         UART1_RTS,
 192
 193         /* UART2 (COM_UART_GATING)*/
 194         UART2_TX,
 195         UART2_RX,
 196         UART2_CTS,
 197         UART2_RTS,
 198
 199         /* UART3 (GIGA_UART_GATING) */
 200         UART3_TX,
 201         UART3_RX,
 202         UART3_CTS,
 203         UART3_RTS,
 204         UART3_CLKREQ,
 205         UART3_BCLK,     /* 12MHz clock out */
 206         Y15_1610_UART3_RTS,
 207
 208         /* PWT & PWL */
 209         PWT,
 210         PWL,
 211
 212         /* USB master generic */
 213         R18_USB_VBUS,
 214         R18_1510_USB_GPIO0,
 215         W4_USB_PUEN,
 216         W4_USB_CLKO,
 217         W4_USB_HIGHZ,
 218         W4_GPIO58,
 219
 220         /* USB1 master */
 221         USB1_SUSP,
 222         USB1_SEO,
 223         W13_1610_USB1_SE0,
 224         USB1_TXEN,
 225         USB1_TXD,
 226         USB1_VP,
 227         USB1_VM,
 228         USB1_RCV,
 229         USB1_SPEED,
 230         R13_1610_USB1_SPEED,
 231         R13_1710_USB1_SE0,
 232
 233         /* USB2 master */
 234         USB2_SUSP,
 235         USB2_VP,
 236         USB2_TXEN,
 237         USB2_VM,
 238         USB2_RCV,
 239         USB2_SEO,
 240         USB2_TXD,
 241
 242         /* OMAP-1510 GPIO */
 243         R18_1510_GPIO0,
 244         R19_1510_GPIO1,
 245         M14_1510_GPIO2,
 246
 247         /* OMAP1610 GPIO */
 248         P18_1610_GPIO3,
 249         Y15_1610_GPIO17,
 250
 251         /* OMAP-1710 GPIO */
 252         R18_1710_GPIO0,
 253         V2_1710_GPIO10,
 254         N21_1710_GPIO14,
 255         W15_1710_GPIO40,
 256
 257         /* MPUIO */
 258         MPUIO2,
 259         N15_1610_MPUIO2,
 260         MPUIO4,
 261         MPUIO5,
 262         T20_1610_MPUIO5,
 263         W11_1610_MPUIO6,
 264         V10_1610_MPUIO7,
 265         W11_1610_MPUIO9,
 266         V10_1610_MPUIO10,
 267         W10_1610_MPUIO11,
 268         E20_1610_MPUIO13,
 269         U20_1610_MPUIO14,
 270         E19_1610_MPUIO15,
 271
 272         /* MCBSP2 */
 273         MCBSP2_CLKR,
 274         MCBSP2_CLKX,
 275         MCBSP2_DR,
 276         MCBSP2_DX,
 277         MCBSP2_FSR,
 278         MCBSP2_FSX,
 279
 280         /* MCBSP3 */
 281         MCBSP3_CLKX,
 282
 283         /* Misc ballouts */
 284         BALLOUT_V8_ARMIO3,
 285         N20_HDQ,
 286
 287         /* OMAP-1610 MMC2 */
 288         W8_1610_MMC2_DAT0,
 289         V8_1610_MMC2_DAT1,
 290         W15_1610_MMC2_DAT2,
 291         R10_1610_MMC2_DAT3,
 292         Y10_1610_MMC2_CLK,
 293         Y8_1610_MMC2_CMD,
 294         V9_1610_MMC2_CMDDIR,
 295         V5_1610_MMC2_DATDIR0,
 296         W19_1610_MMC2_DATDIR1,
 297         R18_1610_MMC2_CLKIN,
 298
 299         /* OMAP-1610 External Trace Interface */
 300         M19_1610_ETM_PSTAT0,
 301         L15_1610_ETM_PSTAT1,
 302         L18_1610_ETM_PSTAT2,
 303         L19_1610_ETM_D0,
 304         J19_1610_ETM_D6,
 305         J18_1610_ETM_D7,
 306
 307         /* OMAP16XX GPIO */
 308         P20_1610_GPIO4,
 309         V9_1610_GPIO7,
 310         W8_1610_GPIO9,
 311         N20_1610_GPIO11,
 312         N19_1610_GPIO13,
 313         P10_1610_GPIO22,
 314         V5_1610_GPIO24,
 315         AA20_1610_GPIO_41,
 316         W19_1610_GPIO48,
 317         M7_1610_GPIO62,
 318         V14_16XX_GPIO37,
 319         R9_16XX_GPIO18,
 320         L14_16XX_GPIO49,
 321
 322         /* OMAP-1610 uWire */
 323         V19_1610_UWIRE_SCLK,
 324         U18_1610_UWIRE_SDI,
 325         W21_1610_UWIRE_SDO,
 326         N14_1610_UWIRE_CS0,
 327         P15_1610_UWIRE_CS3,
 328         N15_1610_UWIRE_CS1,
 329
 330         /* OMAP-1610 SPI */
 331         U19_1610_SPIF_SCK,
 332         U18_1610_SPIF_DIN,
 333         P20_1610_SPIF_DIN,
 334         W21_1610_SPIF_DOUT,
 335         R18_1610_SPIF_DOUT,
 336         N14_1610_SPIF_CS0,
 337         N15_1610_SPIF_CS1,
 338         T19_1610_SPIF_CS2,
 339         P15_1610_SPIF_CS3,
 340
 341         /* OMAP-1610 Flash */
 342         L3_1610_FLASH_CS2B_OE,
 343         M8_1610_FLASH_CS2B_WE,
 344
 345         /* First MMC */
 346         MMC_CMD,
 347         MMC_DAT1,
 348         MMC_DAT2,
 349         MMC_DAT0,
 350         MMC_CLK,
 351         MMC_DAT3,
 352
 353         /* OMAP-1710 MMC CMDDIR and DATDIR0 */
 354         M15_1710_MMC_CLKI,
 355         P19_1710_MMC_CMDDIR,
 356         P20_1710_MMC_DATDIR0,
 357
 358         /* OMAP-1610 USB0 alternate pin configuration */
 359         W9_USB0_TXEN,
 360         AA9_USB0_VP,
 361         Y5_USB0_RCV,
 362         R9_USB0_VM,
 363         V6_USB0_TXD,
 364         W5_USB0_SE0,
 365         V9_USB0_SPEED,
 366         V9_USB0_SUSP,
 367
 368         /* USB2 */
 369         W9_USB2_TXEN,
 370         AA9_USB2_VP,
 371         Y5_USB2_RCV,
 372         R9_USB2_VM,
 373         V6_USB2_TXD,
 374         W5_USB2_SE0,
 375
 376         /* 16XX UART */
 377         R13_1610_UART1_TX,
 378         V14_16XX_UART1_RX,
 379         R14_1610_UART1_CTS,
 380         AA15_1610_UART1_RTS,
 381         R9_16XX_UART2_RX,
 382         L14_16XX_UART3_RX,
 383
 384         /* I2C OMAP-1610 */
 385         I2C_SCL,
 386         I2C_SDA,
 387
 388         /* Keypad */
 389         F18_1610_KBC0,
 390         D20_1610_KBC1,
 391         D19_1610_KBC2,
 392         E18_1610_KBC3,
 393         C21_1610_KBC4,
 394         G18_1610_KBR0,
 395         F19_1610_KBR1,
 396         H14_1610_KBR2,
 397         E20_1610_KBR3,
 398         E19_1610_KBR4,
 399         N19_1610_KBR5,
 400
 401         /* Power management */
 402         T20_1610_LOW_PWR,
 403
 404         /* MCLK Settings */
 405         V5_1710_MCLK_ON,
 406         V5_1710_MCLK_OFF,
 407         R10_1610_MCLK_ON,
 408         R10_1610_MCLK_OFF,
 409
 410         /* CompactFlash controller */
 411         P11_1610_CF_CD2,
 412         R11_1610_CF_IOIS16,
 413         V10_1610_CF_IREQ,
 414         W10_1610_CF_RESET,
 415         W11_1610_CF_CD1,
 416
 417         /* parallel camera */
 418         J15_1610_CAM_LCLK,
 419         J18_1610_CAM_D7,
 420         J19_1610_CAM_D6,
 421         J14_1610_CAM_D5,
 422         K18_1610_CAM_D4,
 423         K19_1610_CAM_D3,
 424         K15_1610_CAM_D2,
 425         K14_1610_CAM_D1,
 426         L19_1610_CAM_D0,
 427         L18_1610_CAM_VS,
 428         L15_1610_CAM_HS,
 429         M19_1610_CAM_RSTZ,
 430         Y15_1610_CAM_OUTCLK,
 431
 432         /* serial camera */
 433         H19_1610_CAM_EXCLK,
 434         Y12_1610_CCP_CLKP,
 435         W13_1610_CCP_CLKM,
 436         W14_1610_CCP_DATAP,
 437         Y14_1610_CCP_DATAM,
 438
 439 };
 440
 441 enum omap24xx_index {
 442         /* 24xx I2C */
 443         M19_24XX_I2C1_SCL,
 444         L15_24XX_I2C1_SDA,
 445         J15_24XX_I2C2_SCL,
 446         H19_24XX_I2C2_SDA,
 447
 448         /* 24xx Menelaus interrupt */
 449         W19_24XX_SYS_NIRQ,
 450
 451         /* 24xx clock */
 452         W14_24XX_SYS_CLKOUT,
 453
 454         /* 24xx GPMC chipselects, wait pin monitoring */
 455         E2_GPMC_NCS2,
 456         L2_GPMC_NCS7,
 457         L3_GPMC_WAIT0,
 458         N7_GPMC_WAIT1,
 459         M1_GPMC_WAIT2,
 460         P1_GPMC_WAIT3,
 461
 462         /* 242X McBSP */
 463         Y15_24XX_MCBSP2_CLKX,
 464         R14_24XX_MCBSP2_FSX,
 465         W15_24XX_MCBSP2_DR,
 466         V15_24XX_MCBSP2_DX,
 467
 468         /* 24xx GPIO */
 469         M21_242X_GPIO11,
 470         P21_242X_GPIO12,
 471         AA10_242X_GPIO13,
 472         AA6_242X_GPIO14,
 473         AA4_242X_GPIO15,
 474         Y11_242X_GPIO16,
 475         AA12_242X_GPIO17,
 476         AA8_242X_GPIO58,
 477         Y20_24XX_GPIO60,
 478         W4__24XX_GPIO74,
 479         N15_24XX_GPIO85,
 480         M15_24XX_GPIO92,
 481         P20_24XX_GPIO93,
 482         P18_24XX_GPIO95,
 483         M18_24XX_GPIO96,
 484         L14_24XX_GPIO97,
 485         J15_24XX_GPIO99,
 486         V14_24XX_GPIO117,
 487         P14_24XX_GPIO125,
 488
 489         /* 242x DBG GPIO */
 490         V4_242X_GPIO49,
 491         W2_242X_GPIO50,
 492         U4_242X_GPIO51,
 493         V3_242X_GPIO52,
 494         V2_242X_GPIO53,
 495         V6_242X_GPIO53,
 496         T4_242X_GPIO54,
 497         Y4_242X_GPIO54,
 498         T3_242X_GPIO55,
 499         U2_242X_GPIO56,
 500
 501         /* 24xx external DMA requests */
 502         AA10_242X_DMAREQ0,
 503         AA6_242X_DMAREQ1,
 504         E4_242X_DMAREQ2,
 505         G4_242X_DMAREQ3,
 506         D3_242X_DMAREQ4,
 507         E3_242X_DMAREQ5,
 508
 509         /* UART3 */
 510         K15_24XX_UART3_TX,
 511         K14_24XX_UART3_RX,
 512
 513         /* MMC/SDIO */
 514         G19_24XX_MMC_CLKO,
 515         H18_24XX_MMC_CMD,
 516         F20_24XX_MMC_DAT0,
 517         H14_24XX_MMC_DAT1,
 518         E19_24XX_MMC_DAT2,
 519         D19_24XX_MMC_DAT3,
 520         F19_24XX_MMC_DAT_DIR0,
 521         E20_24XX_MMC_DAT_DIR1,
 522         F18_24XX_MMC_DAT_DIR2,
 523         E18_24XX_MMC_DAT_DIR3,
 524         G18_24XX_MMC_CMD_DIR,
 525         H15_24XX_MMC_CLKI,
 526
 527         /* Full speed USB */
 528         J20_24XX_USB0_PUEN,
 529         J19_24XX_USB0_VP,
 530         K20_24XX_USB0_VM,
 531         J18_24XX_USB0_RCV,
 532         K19_24XX_USB0_TXEN,
 533         J14_24XX_USB0_SE0,
 534         K18_24XX_USB0_DAT,
 535
 536         N14_24XX_USB1_SE0,
 537         W12_24XX_USB1_SE0,
 538         P15_24XX_USB1_DAT,
 539         R13_24XX_USB1_DAT,
 540         W20_24XX_USB1_TXEN,
 541         P13_24XX_USB1_TXEN,
 542         V19_24XX_USB1_RCV,
 543         V12_24XX_USB1_RCV,
 544
 545         AA10_24XX_USB2_SE0,
 546         Y11_24XX_USB2_DAT,
 547         AA12_24XX_USB2_TXEN,
 548         AA6_24XX_USB2_RCV,
 549         AA4_24XX_USB2_TLLSE0,
 550
 551         /* Keypad GPIO*/
 552         T19_24XX_KBR0,
 553         R19_24XX_KBR1,
 554         V18_24XX_KBR2,
 555         M21_24XX_KBR3,
 556         E5__24XX_KBR4,
 557         M18_24XX_KBR5,
 558         R20_24XX_KBC0,
 559         M14_24XX_KBC1,
 560         H19_24XX_KBC2,
 561         V17_24XX_KBC3,
 562         P21_24XX_KBC4,
 563         L14_24XX_KBC5,
 564         N19_24XX_KBC6,
 565
 566         /* 24xx Menelaus Keypad GPIO */
 567         B3__24XX_KBR5,
 568         AA4_24XX_KBC2,
 569         B13_24XX_KBC6,
 570
 571         /* 2430 USB */
 572         AD9_2430_USB0_PUEN,
 573         Y11_2430_USB0_VP,
 574         AD7_2430_USB0_VM,
 575         AE7_2430_USB0_RCV,
 576         AD4_2430_USB0_TXEN,
 577         AF9_2430_USB0_SE0,
 578         AE6_2430_USB0_DAT,
 579         AD24_2430_USB1_SE0,
 580         AB24_2430_USB1_RCV,
 581         Y25_2430_USB1_TXEN,
 582         AA26_2430_USB1_DAT,
 583
 584         /* 2430 HS-USB */
 585         AD9_2430_USB0HS_DATA3,
 586         Y11_2430_USB0HS_DATA4,
 587         AD7_2430_USB0HS_DATA5,
 588         AE7_2430_USB0HS_DATA6,
 589         AD4_2430_USB0HS_DATA2,
 590         AF9_2430_USB0HS_DATA0,
 591         AE6_2430_USB0HS_DATA1,
 592         AE8_2430_USB0HS_CLK,
 593         AD8_2430_USB0HS_DIR,
 594         AE5_2430_USB0HS_STP,
 595         AE9_2430_USB0HS_NXT,
 596         AC7_2430_USB0HS_DATA7,
 597
 598         /* 2430 McBSP */
 599         AD6_2430_MCBSP_CLKS,
 600
 601         AB2_2430_MCBSP1_CLKR,
 602         AD5_2430_MCBSP1_FSR,
 603         AA1_2430_MCBSP1_DX,
 604         AF3_2430_MCBSP1_DR,
 605         AB3_2430_MCBSP1_FSX,
 606         Y9_2430_MCBSP1_CLKX,
 607
 608         AC10_2430_MCBSP2_FSX,
 609         AD16_2430_MCBSP2_CLX,
 610         AE13_2430_MCBSP2_DX,
 611         AD13_2430_MCBSP2_DR,
 612         AC10_2430_MCBSP2_FSX_OFF,
 613         AD16_2430_MCBSP2_CLX_OFF,
 614         AE13_2430_MCBSP2_DX_OFF,
 615         AD13_2430_MCBSP2_DR_OFF,
 616
 617         AC9_2430_MCBSP3_CLKX,
 618         AE4_2430_MCBSP3_FSX,
 619         AE2_2430_MCBSP3_DR,
 620         AF4_2430_MCBSP3_DX,
 621
 622         N3_2430_MCBSP4_CLKX,
 623         AD23_2430_MCBSP4_DR,
 624         AB25_2430_MCBSP4_DX,
 625         AC25_2430_MCBSP4_FSX,
 626
 627         AE16_2430_MCBSP5_CLKX,
 628         AF12_2430_MCBSP5_FSX,
 629         K7_2430_MCBSP5_DX,
 630         M1_2430_MCBSP5_DR,
 631
 632         /* 2430 McSPI*/
 633         Y18_2430_MCSPI1_CLK,
 634         AD15_2430_MCSPI1_SIMO,
 635         AE17_2430_MCSPI1_SOMI,
 636         U1_2430_MCSPI1_CS0,
 637
 638         /* Touchscreen GPIO */
 639         AF19_2430_GPIO_85,
 640
 641 };
 642
 643 struct omap_mux_cfg {
 644         struct pin_config       *pins;
 645         unsigned long           size;
 646         int                     (*cfg_reg)(const struct pin_config *cfg);
 647 };
 648
 649 #ifdef  CONFIG_OMAP_MUX
 650 /* setup pin muxing in Linux */
 651 extern int omap1_mux_init(void);
 652 extern int omap_mux_register(struct omap_mux_cfg *);
 653 extern int omap_cfg_reg(unsigned long reg_cfg);
 654 #else
 655 /* boot loader does it all (no warnings from CONFIG_OMAP_MUX_WARNINGS) */
 656 static inline int omap1_mux_init(void) { return 0; }
 657 static inline int omap_cfg_reg(unsigned long reg_cfg) { return 0; }
 658 #endif
 659
 660 extern int omap2_mux_init(void);
 661
 662 #endif