2 * arch/arm/plat-omap/include/mach/mcbsp.h
4 * Defines for Multi-Channel Buffered Serial Port
6 * Copyright (C) 2002 RidgeRun, Inc.
7 * Author: Steve Johnson
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #ifndef __ASM_ARCH_OMAP_MCBSP_H
25 #define __ASM_ARCH_OMAP_MCBSP_H
27 #include <linux/completion.h>
28 #include <linux/spinlock.h>
30 #include <mach/hardware.h>
31 #include <plat/clock.h>
33 /* macro for building platform_device for McBSP ports */
34 #define OMAP_MCBSP_PLATFORM_DEVICE(port_nr) \
35 static struct platform_device omap_mcbsp##port_nr = { \
36 .name = "omap-mcbsp-dai", \
37 .id = OMAP_MCBSP##port_nr, \
40 #define OMAP7XX_MCBSP1_BASE 0xfffb1000
41 #define OMAP7XX_MCBSP2_BASE 0xfffb1800
43 #define OMAP1510_MCBSP1_BASE 0xe1011800
44 #define OMAP1510_MCBSP2_BASE 0xfffb1000
45 #define OMAP1510_MCBSP3_BASE 0xe1017000
47 #define OMAP1610_MCBSP1_BASE 0xe1011800
48 #define OMAP1610_MCBSP2_BASE 0xfffb1000
49 #define OMAP1610_MCBSP3_BASE 0xe1017000
51 #define OMAP24XX_MCBSP1_BASE 0x48074000
52 #define OMAP24XX_MCBSP2_BASE 0x48076000
53 #define OMAP2430_MCBSP3_BASE 0x4808c000
54 #define OMAP2430_MCBSP4_BASE 0x4808e000
55 #define OMAP2430_MCBSP5_BASE 0x48096000
57 #define OMAP34XX_MCBSP1_BASE 0x48074000
58 #define OMAP34XX_MCBSP2_BASE 0x49022000
59 #define OMAP34XX_MCBSP2_ST_BASE 0x49028000
60 #define OMAP34XX_MCBSP3_BASE 0x49024000
61 #define OMAP34XX_MCBSP3_ST_BASE 0x4902A000
62 #define OMAP34XX_MCBSP3_BASE 0x49024000
63 #define OMAP34XX_MCBSP4_BASE 0x49026000
64 #define OMAP34XX_MCBSP5_BASE 0x48096000
66 #define OMAP44XX_MCBSP1_BASE 0x49022000
67 #define OMAP44XX_MCBSP2_BASE 0x49024000
68 #define OMAP44XX_MCBSP3_BASE 0x49026000
69 #define OMAP44XX_MCBSP4_BASE 0x48096000
71 #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
73 #define OMAP_MCBSP_REG_DRR2 0x00
74 #define OMAP_MCBSP_REG_DRR1 0x02
75 #define OMAP_MCBSP_REG_DXR2 0x04
76 #define OMAP_MCBSP_REG_DXR1 0x06
77 #define OMAP_MCBSP_REG_SPCR2 0x08
78 #define OMAP_MCBSP_REG_SPCR1 0x0a
79 #define OMAP_MCBSP_REG_RCR2 0x0c
80 #define OMAP_MCBSP_REG_RCR1 0x0e
81 #define OMAP_MCBSP_REG_XCR2 0x10
82 #define OMAP_MCBSP_REG_XCR1 0x12
83 #define OMAP_MCBSP_REG_SRGR2 0x14
84 #define OMAP_MCBSP_REG_SRGR1 0x16
85 #define OMAP_MCBSP_REG_MCR2 0x18
86 #define OMAP_MCBSP_REG_MCR1 0x1a
87 #define OMAP_MCBSP_REG_RCERA 0x1c
88 #define OMAP_MCBSP_REG_RCERB 0x1e
89 #define OMAP_MCBSP_REG_XCERA 0x20
90 #define OMAP_MCBSP_REG_XCERB 0x22
91 #define OMAP_MCBSP_REG_PCR0 0x24
92 #define OMAP_MCBSP_REG_RCERC 0x26
93 #define OMAP_MCBSP_REG_RCERD 0x28
94 #define OMAP_MCBSP_REG_XCERC 0x2A
95 #define OMAP_MCBSP_REG_XCERD 0x2C
96 #define OMAP_MCBSP_REG_RCERE 0x2E
97 #define OMAP_MCBSP_REG_RCERF 0x30
98 #define OMAP_MCBSP_REG_XCERE 0x32
99 #define OMAP_MCBSP_REG_XCERF 0x34
100 #define OMAP_MCBSP_REG_RCERG 0x36
101 #define OMAP_MCBSP_REG_RCERH 0x38
102 #define OMAP_MCBSP_REG_XCERG 0x3A
103 #define OMAP_MCBSP_REG_XCERH 0x3C
105 /* Dummy defines, these are not available on omap1 */
106 #define OMAP_MCBSP_REG_XCCR 0x00
107 #define OMAP_MCBSP_REG_RCCR 0x00
111 #define OMAP_MCBSP_REG_DRR2 0x00
112 #define OMAP_MCBSP_REG_DRR1 0x04
113 #define OMAP_MCBSP_REG_DXR2 0x08
114 #define OMAP_MCBSP_REG_DXR1 0x0C
115 #define OMAP_MCBSP_REG_DRR 0x00
116 #define OMAP_MCBSP_REG_DXR 0x08
117 #define OMAP_MCBSP_REG_SPCR2 0x10
118 #define OMAP_MCBSP_REG_SPCR1 0x14
119 #define OMAP_MCBSP_REG_RCR2 0x18
120 #define OMAP_MCBSP_REG_RCR1 0x1C
121 #define OMAP_MCBSP_REG_XCR2 0x20
122 #define OMAP_MCBSP_REG_XCR1 0x24
123 #define OMAP_MCBSP_REG_SRGR2 0x28
124 #define OMAP_MCBSP_REG_SRGR1 0x2C
125 #define OMAP_MCBSP_REG_MCR2 0x30
126 #define OMAP_MCBSP_REG_MCR1 0x34
127 #define OMAP_MCBSP_REG_RCERA 0x38
128 #define OMAP_MCBSP_REG_RCERB 0x3C
129 #define OMAP_MCBSP_REG_XCERA 0x40
130 #define OMAP_MCBSP_REG_XCERB 0x44
131 #define OMAP_MCBSP_REG_PCR0 0x48
132 #define OMAP_MCBSP_REG_RCERC 0x4C
133 #define OMAP_MCBSP_REG_RCERD 0x50
134 #define OMAP_MCBSP_REG_XCERC 0x54
135 #define OMAP_MCBSP_REG_XCERD 0x58
136 #define OMAP_MCBSP_REG_RCERE 0x5C
137 #define OMAP_MCBSP_REG_RCERF 0x60
138 #define OMAP_MCBSP_REG_XCERE 0x64
139 #define OMAP_MCBSP_REG_XCERF 0x68
140 #define OMAP_MCBSP_REG_RCERG 0x6C
141 #define OMAP_MCBSP_REG_RCERH 0x70
142 #define OMAP_MCBSP_REG_XCERG 0x74
143 #define OMAP_MCBSP_REG_XCERH 0x78
144 #define OMAP_MCBSP_REG_SYSCON 0x8C
145 #define OMAP_MCBSP_REG_THRSH2 0x90
146 #define OMAP_MCBSP_REG_THRSH1 0x94
147 #define OMAP_MCBSP_REG_IRQST 0xA0
148 #define OMAP_MCBSP_REG_IRQEN 0xA4
149 #define OMAP_MCBSP_REG_WAKEUPEN 0xA8
150 #define OMAP_MCBSP_REG_XCCR 0xAC
151 #define OMAP_MCBSP_REG_RCCR 0xB0
152 #define OMAP_MCBSP_REG_XBUFFSTAT 0xB4
153 #define OMAP_MCBSP_REG_RBUFFSTAT 0xB8
154 #define OMAP_MCBSP_REG_SSELCR 0xBC
156 #define OMAP_ST_REG_REV 0x00
157 #define OMAP_ST_REG_SYSCONFIG 0x10
158 #define OMAP_ST_REG_IRQSTATUS 0x18
159 #define OMAP_ST_REG_IRQENABLE 0x1C
160 #define OMAP_ST_REG_SGAINCR 0x24
161 #define OMAP_ST_REG_SFIRCR 0x28
162 #define OMAP_ST_REG_SSELCR 0x2C
166 /************************** McBSP SPCR1 bit definitions ***********************/
170 #define RSYNC_ERR 0x0008
171 #define RINTM(value) ((value)<<4) /* bits 4:5 */
174 #define CLKSTP(value) ((value)<<11) /* bits 11:12 */
175 #define RJUST(value) ((value)<<13) /* bits 13:14 */
179 /************************** McBSP SPCR2 bit definitions ***********************/
182 #define XEMPTY 0x0004
183 #define XSYNC_ERR 0x0008
184 #define XINTM(value) ((value)<<4) /* bits 4:5 */
190 /************************** McBSP PCR bit definitions *************************/
195 #define DR_STAT 0x0010
196 #define DX_STAT 0x0020
197 #define CLKS_STAT 0x0040
198 #define SCLKME 0x0080
205 #define IDLE_EN 0x4000
207 /************************** McBSP RCR1 bit definitions ************************/
208 #define RWDLEN1(value) ((value)<<5) /* Bits 5:7 */
209 #define RFRLEN1(value) ((value)<<8) /* Bits 8:14 */
211 /************************** McBSP XCR1 bit definitions ************************/
212 #define XWDLEN1(value) ((value)<<5) /* Bits 5:7 */
213 #define XFRLEN1(value) ((value)<<8) /* Bits 8:14 */
215 /*************************** McBSP RCR2 bit definitions ***********************/
216 #define RDATDLY(value) (value) /* Bits 0:1 */
218 #define RCOMPAND(value) ((value)<<3) /* Bits 3:4 */
219 #define RWDLEN2(value) ((value)<<5) /* Bits 5:7 */
220 #define RFRLEN2(value) ((value)<<8) /* Bits 8:14 */
221 #define RPHASE 0x8000
223 /*************************** McBSP XCR2 bit definitions ***********************/
224 #define XDATDLY(value) (value) /* Bits 0:1 */
226 #define XCOMPAND(value) ((value)<<3) /* Bits 3:4 */
227 #define XWDLEN2(value) ((value)<<5) /* Bits 5:7 */
228 #define XFRLEN2(value) ((value)<<8) /* Bits 8:14 */
229 #define XPHASE 0x8000
231 /************************* McBSP SRGR1 bit definitions ************************/
232 #define CLKGDV(value) (value) /* Bits 0:7 */
233 #define FWID(value) ((value)<<8) /* Bits 8:15 */
235 /************************* McBSP SRGR2 bit definitions ************************/
236 #define FPER(value) (value) /* Bits 0:11 */
242 /************************* McBSP MCR1 bit definitions *************************/
244 #define RCBLK(value) ((value)<<2) /* Bits 2:4 */
245 #define RPABLK(value) ((value)<<5) /* Bits 5:6 */
246 #define RPBBLK(value) ((value)<<7) /* Bits 7:8 */
248 /************************* McBSP MCR2 bit definitions *************************/
249 #define XMCM(value) (value) /* Bits 0:1 */
250 #define XCBLK(value) ((value)<<2) /* Bits 2:4 */
251 #define XPABLK(value) ((value)<<5) /* Bits 5:6 */
252 #define XPBBLK(value) ((value)<<7) /* Bits 7:8 */
254 /*********************** McBSP XCCR bit definitions *************************/
255 #define EXTCLKGATE 0x8000
256 #define PPCONNECT 0x4000
257 #define DXENDLY(value) ((value)<<12) /* Bits 12:13 */
258 #define XFULL_CYCLE 0x0800
260 #define XDMAEN 0x0008
261 #define XDISABLE 0x0001
263 /********************** McBSP RCCR bit definitions *************************/
264 #define RFULL_CYCLE 0x0800
265 #define RDMAEN 0x0008
266 #define RDISABLE 0x0001
268 /********************** McBSP SYSCONFIG bit definitions ********************/
269 #define CLOCKACTIVITY(value) ((value)<<8)
270 #define SIDLEMODE(value) ((value)<<3)
271 #define ENAWAKEUP 0x0004
272 #define SOFTRST 0x0002
274 /********************** McBSP SSELCR bit definitions ***********************/
275 #define SIDETONEEN 0x0400
277 /********************** McBSP Sidetone SYSCONFIG bit definitions ***********/
278 #define ST_AUTOIDLE 0x0001
280 /********************** McBSP Sidetone SGAINCR bit definitions *************/
281 #define ST_CH1GAIN(value) ((value<<16)) /* Bits 16:31 */
282 #define ST_CH0GAIN(value) (value) /* Bits 0:15 */
284 /********************** McBSP Sidetone SFIRCR bit definitions **************/
285 #define ST_FIRCOEFF(value) (value) /* Bits 0:15 */
287 /********************** McBSP Sidetone SSELCR bit definitions **************/
288 #define ST_COEFFWRDONE 0x0004
289 #define ST_COEFFWREN 0x0002
290 #define ST_SIDETONEEN 0x0001
292 /********************** McBSP DMA operating modes **************************/
293 #define MCBSP_DMA_MODE_ELEMENT 0
294 #define MCBSP_DMA_MODE_THRESHOLD 1
295 #define MCBSP_DMA_MODE_FRAME 2
297 /********************** McBSP WAKEUPEN bit definitions *********************/
298 #define XEMPTYEOFEN 0x4000
299 #define XRDYEN 0x0400
300 #define XEOFEN 0x0200
301 #define XFSXEN 0x0100
302 #define XSYNCERREN 0x0080
303 #define RRDYEN 0x0008
304 #define REOFEN 0x0004
305 #define RFSREN 0x0002
306 #define RSYNCERREN 0x0001
308 /* CLKR signal muxing options */
309 #define CLKR_SRC_CLKR 0
310 #define CLKR_SRC_CLKX 1
312 /* FSR signal muxing options */
313 #define FSR_SRC_FSR 0
314 #define FSR_SRC_FSX 1
316 /* McBSP functional clock sources */
317 #define MCBSP_CLKS_PRCM_SRC 0
318 #define MCBSP_CLKS_PAD_SRC 1
320 /* we don't do multichannel for now */
321 struct omap_mcbsp_reg_cfg {
357 typedef int __bitwise omap_mcbsp_io_type_t;
358 #define OMAP_MCBSP_IRQ_IO ((__force omap_mcbsp_io_type_t) 1)
359 #define OMAP_MCBSP_POLL_IO ((__force omap_mcbsp_io_type_t) 2)
362 OMAP_MCBSP_WORD_8 = 0,
368 } omap_mcbsp_word_length;
371 OMAP_MCBSP_CLK_RISING = 0,
372 OMAP_MCBSP_CLK_FALLING,
373 } omap_mcbsp_clk_polarity;
376 OMAP_MCBSP_FS_ACTIVE_HIGH = 0,
377 OMAP_MCBSP_FS_ACTIVE_LOW,
378 } omap_mcbsp_fs_polarity;
381 OMAP_MCBSP_CLK_STP_MODE_NO_DELAY = 0,
382 OMAP_MCBSP_CLK_STP_MODE_DELAY,
383 } omap_mcbsp_clk_stp_mode;
386 /******* SPI specific mode **********/
388 OMAP_MCBSP_SPI_MASTER = 0,
389 OMAP_MCBSP_SPI_SLAVE,
390 } omap_mcbsp_spi_mode;
392 struct omap_mcbsp_spi_cfg {
393 omap_mcbsp_spi_mode spi_mode;
394 omap_mcbsp_clk_polarity rx_clock_polarity;
395 omap_mcbsp_clk_polarity tx_clock_polarity;
396 omap_mcbsp_fs_polarity fsx_polarity;
398 omap_mcbsp_clk_stp_mode clk_stp_mode;
399 omap_mcbsp_word_length word_length;
402 /* Platform specific configuration */
403 struct omap_mcbsp_ops {
404 void (*request)(unsigned int);
405 void (*free)(unsigned int);
406 int (*set_clks_src)(u8, u8);
409 struct omap_mcbsp_platform_data {
410 unsigned long phys_base;
411 u8 dma_rx_sync, dma_tx_sync;
413 struct omap_mcbsp_ops *ops;
414 #ifdef CONFIG_ARCH_OMAP3
415 /* Sidetone block for McBSP 2 and 3 */
416 unsigned long phys_base_st;
421 struct omap_mcbsp_st_data {
422 void __iomem *io_base_st;
425 s16 taps[128]; /* Sidetone filter coefficients */
426 int nr_taps; /* Number of filter coefficients in use */
433 unsigned long phys_base;
434 void __iomem *io_base;
437 omap_mcbsp_word_length rx_word_length;
438 omap_mcbsp_word_length tx_word_length;
440 omap_mcbsp_io_type_t io_type; /* IRQ or poll */
441 /* IRQ based TX/RX */
451 /* Completion queues */
452 struct completion tx_irq_completion;
453 struct completion rx_irq_completion;
454 struct completion tx_dma_completion;
455 struct completion rx_dma_completion;
457 /* Protect the field .free, while checking if the mcbsp is in use */
459 struct omap_mcbsp_platform_data *pdata;
462 #ifdef CONFIG_ARCH_OMAP3
463 struct omap_mcbsp_st_data *st_data;
470 extern struct omap_mcbsp **mcbsp_ptr;
471 extern int omap_mcbsp_count, omap_mcbsp_cache_size;
473 #define omap_mcbsp_check_valid_id(id) (id < omap_mcbsp_count)
474 #define id_to_mcbsp_ptr(id) mcbsp_ptr[id];
476 int omap_mcbsp_init(void);
477 void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
479 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
480 #ifdef CONFIG_ARCH_OMAP3
481 void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold);
482 void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold);
483 u16 omap_mcbsp_get_max_tx_threshold(unsigned int id);
484 u16 omap_mcbsp_get_max_rx_threshold(unsigned int id);
485 u16 omap_mcbsp_get_fifo_size(unsigned int id);
486 u16 omap_mcbsp_get_tx_delay(unsigned int id);
487 u16 omap_mcbsp_get_rx_delay(unsigned int id);
488 int omap_mcbsp_get_dma_op_mode(unsigned int id);
490 static inline void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
492 static inline void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
494 static inline u16 omap_mcbsp_get_max_tx_threshold(unsigned int id) { return 0; }
495 static inline u16 omap_mcbsp_get_max_rx_threshold(unsigned int id) { return 0; }
496 static inline u16 omap_mcbsp_get_fifo_size(unsigned int id) { return 0; }
497 static inline u16 omap_mcbsp_get_tx_delay(unsigned int id) { return 0; }
498 static inline u16 omap_mcbsp_get_rx_delay(unsigned int id) { return 0; }
499 static inline int omap_mcbsp_get_dma_op_mode(unsigned int id) { return 0; }
501 int omap_mcbsp_request(unsigned int id);
502 void omap_mcbsp_free(unsigned int id);
503 void omap_mcbsp_start(unsigned int id, int tx, int rx);
504 void omap_mcbsp_stop(unsigned int id, int tx, int rx);
505 void omap_mcbsp_xmit_word(unsigned int id, u32 word);
506 u32 omap_mcbsp_recv_word(unsigned int id);
508 int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
509 int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
510 int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word);
511 int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word);
514 /* McBSP functional clock source changing function */
515 extern int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id);
516 /* SPI specific API */
517 void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg);
519 /* Polled read/write functions */
520 int omap_mcbsp_pollread(unsigned int id, u16 * buf);
521 int omap_mcbsp_pollwrite(unsigned int id, u16 buf);
522 int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type);
524 /* McBSP signal muxing API */
525 void omap2_mcbsp1_mux_clkr_src(u8 mux);
526 void omap2_mcbsp1_mux_fsr_src(u8 mux);
528 #ifdef CONFIG_ARCH_OMAP3
529 /* Sidetone specific API */
530 int omap_st_set_chgain(unsigned int id, int channel, s16 chgain);
531 int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain);
532 int omap_st_enable(unsigned int id);
533 int omap_st_disable(unsigned int id);
534 int omap_st_is_enabled(unsigned int id);
536 static inline int omap_st_set_chgain(unsigned int id, int channel,
537 s16 chgain) { return 0; }
538 static inline int omap_st_get_chgain(unsigned int id, int channel,
539 s16 *chgain) { return 0; }
540 static inline int omap_st_enable(unsigned int id) { return 0; }
541 static inline int omap_st_disable(unsigned int id) { return 0; }
542 static inline int omap_st_is_enabled(unsigned int id) { return 0; }