arch/arm/plat-omap/include/plat/dmtimer.h

   1 /*
   2  * arch/arm/plat-omap/include/plat/dmtimer.h
   3  *
   4  * OMAP Dual-Mode Timers
   5  *
   6  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
   7  * Tarun Kanti DebBarma <tarun.kanti@ti.com>
   8  * Thara Gopinath <thara@ti.com>
   9  *
  10  * Platform device conversion and hwmod support.
  11  *
  12  * Copyright (C) 2005 Nokia Corporation
  13  * Author: Lauri Leukkunen <lauri.leukkunen@nokia.com>
  14  * PWM and clock framwork support by Timo Teras.
  15  *
  16  * This program is free software; you can redistribute it and/or modify it
  17  * under the terms of the GNU General Public License as published by the
  18  * Free Software Foundation; either version 2 of the License, or (at your
  19  * option) any later version.
  20  *
  21  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  22  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  23  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  24  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  25  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  26  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  27  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  28  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29  *
  30  * You should have received a copy of the  GNU General Public License along
  31  * with this program; if not, write  to the Free Software Foundation, Inc.,
  32  * 675 Mass Ave, Cambridge, MA 02139, USA.
  33  */
  34
  35 #include <linux/clk.h>
  36 #include <linux/delay.h>
  37 #include <linux/io.h>
  38 #include <linux/platform_device.h>
  39
  40 #ifndef __ASM_ARCH_DMTIMER_H
  41 #define __ASM_ARCH_DMTIMER_H
  42
  43 /* clock sources */
  44 #define OMAP_TIMER_SRC_SYS_CLK                  0x00
  45 #define OMAP_TIMER_SRC_32_KHZ                   0x01
  46 #define OMAP_TIMER_SRC_EXT_CLK                  0x02
  47
  48 /* timer interrupt enable bits */
  49 #define OMAP_TIMER_INT_CAPTURE                  (1 << 2)
  50 #define OMAP_TIMER_INT_OVERFLOW                 (1 << 1)
  51 #define OMAP_TIMER_INT_MATCH                    (1 << 0)
  52
  53 /* trigger types */
  54 #define OMAP_TIMER_TRIGGER_NONE                 0x00
  55 #define OMAP_TIMER_TRIGGER_OVERFLOW             0x01
  56 #define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02
  57
  58 /*
  59  * IP revision identifier so that Highlander IP
  60  * in OMAP4 can be distinguished.
  61  */
  62 #define OMAP_TIMER_IP_VERSION_1                        0x1
  63
  64 /* posted mode types */
  65 #define OMAP_TIMER_NONPOSTED                    0x00
  66 #define OMAP_TIMER_POSTED                       0x01
  67
  68 /* timer capabilities used in hwmod database */
  69 #define OMAP_TIMER_SECURE                               0x80000000
  70 #define OMAP_TIMER_ALWON                                0x40000000
  71 #define OMAP_TIMER_HAS_PWM                              0x20000000
  72
  73 /*
  74  * timer errata flags
  75  *
  76  * Errata i103/i767 impacts all OMAP3/4/5 devices including AM33xx. This
  77  * errata prevents us from using posted mode on these devices, unless the
  78  * timer counter register is never read. For more details please refer to
  79  * the OMAP3/4/5 errata documents.
  80  */
  81 #define OMAP_TIMER_ERRATA_I103_I767                     0x80000000
  82
  83 struct omap_timer_capability_dev_attr {
  84         u32 timer_capability;
  85 };
  86
  87 struct omap_dm_timer;
  88 struct clk;
  89
  90 struct timer_regs {
  91         u32 tidr;
  92         u32 tier;
  93         u32 twer;
  94         u32 tclr;
  95         u32 tcrr;
  96         u32 tldr;
  97         u32 ttrg;
  98         u32 twps;
  99         u32 tmar;
 100         u32 tcar1;
 101         u32 tsicr;
 102         u32 tcar2;
 103         u32 tpir;
 104         u32 tnir;
 105         u32 tcvr;
 106         u32 tocr;
 107         u32 towr;
 108 };
 109
 110 struct dmtimer_platform_data {
 111         int (*set_timer_src)(struct platform_device *pdev, int source);
 112         int timer_ip_version;
 113         u32 needs_manual_reset:1;
 114         bool reserved;
 115
 116         bool loses_context;
 117         u32 timer_errata;
 118
 119         int (*get_context_loss_count)(struct device *dev);
 120 };
 121
 122 struct omap_dm_timer *omap_dm_timer_request(void);
 123 struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id);
 124 int omap_dm_timer_free(struct omap_dm_timer *timer);
 125 void omap_dm_timer_enable(struct omap_dm_timer *timer);
 126 void omap_dm_timer_disable(struct omap_dm_timer *timer);
 127
 128 int omap_dm_timer_get_irq(struct omap_dm_timer *timer);
 129
 130 u32 omap_dm_timer_modify_idlect_mask(u32 inputmask);
 131 struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer);
 132
 133 int omap_dm_timer_trigger(struct omap_dm_timer *timer);
 134 int omap_dm_timer_start(struct omap_dm_timer *timer);
 135 int omap_dm_timer_stop(struct omap_dm_timer *timer);
 136
 137 int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source);
 138 int omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int value);
 139 int omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, unsigned int value);
 140 int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match);
 141 int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle, int trigger);
 142 int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler);
 143
 144 int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, unsigned int value);
 145
 146 unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer);
 147 int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value);
 148 unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer);
 149 int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value);
 150
 151 int omap_dm_timers_active(void);
 152
 153 /*
 154  * Do not use the defines below, they are not needed. They should be only
 155  * used by dmtimer.c and sys_timer related code.
 156  */
 157
 158 /*
 159  * The interrupt registers are different between v1 and v2 ip.
 160  * These registers are offsets from timer->iobase.
 161  */
 162 #define OMAP_TIMER_ID_OFFSET            0x00
 163 #define OMAP_TIMER_OCP_CFG_OFFSET       0x10
 164
 165 #define OMAP_TIMER_V1_SYS_STAT_OFFSET   0x14
 166 #define OMAP_TIMER_V1_STAT_OFFSET       0x18
 167 #define OMAP_TIMER_V1_INT_EN_OFFSET     0x1c
 168
 169 #define OMAP_TIMER_V2_IRQSTATUS_RAW     0x24
 170 #define OMAP_TIMER_V2_IRQSTATUS         0x28
 171 #define OMAP_TIMER_V2_IRQENABLE_SET     0x2c
 172 #define OMAP_TIMER_V2_IRQENABLE_CLR     0x30
 173
 174 /*
 175  * The functional registers have a different base on v1 and v2 ip.
 176  * These registers are offsets from timer->func_base. The func_base
 177  * is samae as io_base for v1 and io_base + 0x14 for v2 ip.
 178  *
 179  */
 180 #define OMAP_TIMER_V2_FUNC_OFFSET               0x14
 181
 182 #define _OMAP_TIMER_WAKEUP_EN_OFFSET    0x20
 183 #define _OMAP_TIMER_CTRL_OFFSET         0x24
 184 #define         OMAP_TIMER_CTRL_GPOCFG          (1 << 14)
 185 #define         OMAP_TIMER_CTRL_CAPTMODE        (1 << 13)
 186 #define         OMAP_TIMER_CTRL_PT              (1 << 12)
 187 #define         OMAP_TIMER_CTRL_TCM_LOWTOHIGH   (0x1 << 8)
 188 #define         OMAP_TIMER_CTRL_TCM_HIGHTOLOW   (0x2 << 8)
 189 #define         OMAP_TIMER_CTRL_TCM_BOTHEDGES   (0x3 << 8)
 190 #define         OMAP_TIMER_CTRL_SCPWM           (1 << 7)
 191 #define         OMAP_TIMER_CTRL_CE              (1 << 6) /* compare enable */
 192 #define         OMAP_TIMER_CTRL_PRE             (1 << 5) /* prescaler enable */
 193 #define         OMAP_TIMER_CTRL_PTV_SHIFT       2 /* prescaler value shift */
 194 #define         OMAP_TIMER_CTRL_POSTED          (1 << 2)
 195 #define         OMAP_TIMER_CTRL_AR              (1 << 1) /* auto-reload enable */
 196 #define         OMAP_TIMER_CTRL_ST              (1 << 0) /* start timer */
 197 #define _OMAP_TIMER_COUNTER_OFFSET      0x28
 198 #define _OMAP_TIMER_LOAD_OFFSET         0x2c
 199 #define _OMAP_TIMER_TRIGGER_OFFSET      0x30
 200 #define _OMAP_TIMER_WRITE_PEND_OFFSET   0x34
 201 #define         WP_NONE                 0       /* no write pending bit */
 202 #define         WP_TCLR                 (1 << 0)
 203 #define         WP_TCRR                 (1 << 1)
 204 #define         WP_TLDR                 (1 << 2)
 205 #define         WP_TTGR                 (1 << 3)
 206 #define         WP_TMAR                 (1 << 4)
 207 #define         WP_TPIR                 (1 << 5)
 208 #define         WP_TNIR                 (1 << 6)
 209 #define         WP_TCVR                 (1 << 7)
 210 #define         WP_TOCR                 (1 << 8)
 211 #define         WP_TOWR                 (1 << 9)
 212 #define _OMAP_TIMER_MATCH_OFFSET        0x38
 213 #define _OMAP_TIMER_CAPTURE_OFFSET      0x3c
 214 #define _OMAP_TIMER_IF_CTRL_OFFSET      0x40
 215 #define _OMAP_TIMER_CAPTURE2_OFFSET             0x44    /* TCAR2, 34xx only */
 216 #define _OMAP_TIMER_TICK_POS_OFFSET             0x48    /* TPIR, 34xx only */
 217 #define _OMAP_TIMER_TICK_NEG_OFFSET             0x4c    /* TNIR, 34xx only */
 218 #define _OMAP_TIMER_TICK_COUNT_OFFSET           0x50    /* TCVR, 34xx only */
 219 #define _OMAP_TIMER_TICK_INT_MASK_SET_OFFSET    0x54    /* TOCR, 34xx only */
 220 #define _OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET  0x58    /* TOWR, 34xx only */
 221
 222 /* register offsets with the write pending bit encoded */
 223 #define WPSHIFT                                 16
 224
 225 #define OMAP_TIMER_WAKEUP_EN_REG                (_OMAP_TIMER_WAKEUP_EN_OFFSET \
 226                                                         | (WP_NONE << WPSHIFT))
 227
 228 #define OMAP_TIMER_CTRL_REG                     (_OMAP_TIMER_CTRL_OFFSET \
 229                                                         | (WP_TCLR << WPSHIFT))
 230
 231 #define OMAP_TIMER_COUNTER_REG                  (_OMAP_TIMER_COUNTER_OFFSET \
 232                                                         | (WP_TCRR << WPSHIFT))
 233
 234 #define OMAP_TIMER_LOAD_REG                     (_OMAP_TIMER_LOAD_OFFSET \
 235                                                         | (WP_TLDR << WPSHIFT))
 236
 237 #define OMAP_TIMER_TRIGGER_REG                  (_OMAP_TIMER_TRIGGER_OFFSET \
 238                                                         | (WP_TTGR << WPSHIFT))
 239
 240 #define OMAP_TIMER_WRITE_PEND_REG               (_OMAP_TIMER_WRITE_PEND_OFFSET \
 241                                                         | (WP_NONE << WPSHIFT))
 242
 243 #define OMAP_TIMER_MATCH_REG                    (_OMAP_TIMER_MATCH_OFFSET \
 244                                                         | (WP_TMAR << WPSHIFT))
 245
 246 #define OMAP_TIMER_CAPTURE_REG                  (_OMAP_TIMER_CAPTURE_OFFSET \
 247                                                         | (WP_NONE << WPSHIFT))
 248
 249 #define OMAP_TIMER_IF_CTRL_REG                  (_OMAP_TIMER_IF_CTRL_OFFSET \
 250                                                         | (WP_NONE << WPSHIFT))
 251
 252 #define OMAP_TIMER_CAPTURE2_REG                 (_OMAP_TIMER_CAPTURE2_OFFSET \
 253                                                         | (WP_NONE << WPSHIFT))
 254
 255 #define OMAP_TIMER_TICK_POS_REG                 (_OMAP_TIMER_TICK_POS_OFFSET \
 256                                                         | (WP_TPIR << WPSHIFT))
 257
 258 #define OMAP_TIMER_TICK_NEG_REG                 (_OMAP_TIMER_TICK_NEG_OFFSET \
 259                                                         | (WP_TNIR << WPSHIFT))
 260
 261 #define OMAP_TIMER_TICK_COUNT_REG               (_OMAP_TIMER_TICK_COUNT_OFFSET \
 262                                                         | (WP_TCVR << WPSHIFT))
 263
 264 #define OMAP_TIMER_TICK_INT_MASK_SET_REG                                \
 265                 (_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET | (WP_TOCR << WPSHIFT))
 266
 267 #define OMAP_TIMER_TICK_INT_MASK_COUNT_REG                              \
 268                 (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))
 269
 270 struct omap_dm_timer {
 271         unsigned long phys_base;
 272         int id;
 273         int irq;
 274         struct clk *fclk;
 275
 276         void __iomem    *io_base;
 277         void __iomem    *sys_stat;      /* TISTAT timer status */
 278         void __iomem    *irq_stat;      /* TISR/IRQSTATUS interrupt status */
 279         void __iomem    *irq_ena;       /* irq enable */
 280         void __iomem    *irq_dis;       /* irq disable, only on v2 ip */
 281         void __iomem    *pend;          /* write pending */
 282         void __iomem    *func_base;     /* function register base */
 283
 284         unsigned long rate;
 285         unsigned reserved:1;
 286         unsigned posted:1;
 287         struct timer_regs context;
 288         bool loses_context;
 289         int ctx_loss_count;
 290         int revision;
 291         u32 errata;
 292         struct platform_device *pdev;
 293         struct list_head node;
 294
 295         int (*get_context_loss_count)(struct device *dev);
 296 };
 297
 298 int omap_dm_timer_prepare(struct omap_dm_timer *timer);
 299
 300 static inline u32 __omap_dm_timer_read(struct omap_dm_timer *timer, u32 reg,
 301                                                 int posted)
 302 {
 303         if (posted)
 304                 while (__raw_readl(timer->pend) & (reg >> WPSHIFT))
 305                         cpu_relax();
 306
 307         return __raw_readl(timer->func_base + (reg & 0xff));
 308 }
 309
 310 static inline void __omap_dm_timer_write(struct omap_dm_timer *timer,
 311                                         u32 reg, u32 val, int posted)
 312 {
 313         if (posted)
 314                 while (__raw_readl(timer->pend) & (reg >> WPSHIFT))
 315                         cpu_relax();
 316
 317         __raw_writel(val, timer->func_base + (reg & 0xff));
 318 }
 319
 320 static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer)
 321 {
 322         u32 tidr;
 323
 324         /* Assume v1 ip if bits [31:16] are zero */
 325         tidr = __raw_readl(timer->io_base);
 326         if (!(tidr >> 16)) {
 327                 timer->revision = 1;
 328                 timer->sys_stat = timer->io_base +
 329                                 OMAP_TIMER_V1_SYS_STAT_OFFSET;
 330                 timer->irq_stat = timer->io_base + OMAP_TIMER_V1_STAT_OFFSET;
 331                 timer->irq_ena = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET;
 332                 timer->irq_dis = 0;
 333                 timer->pend = timer->io_base + _OMAP_TIMER_WRITE_PEND_OFFSET;
 334                 timer->func_base = timer->io_base;
 335         } else {
 336                 timer->revision = 2;
 337                 timer->sys_stat = 0;
 338                 timer->irq_stat = timer->io_base + OMAP_TIMER_V2_IRQSTATUS;
 339                 timer->irq_ena = timer->io_base + OMAP_TIMER_V2_IRQENABLE_SET;
 340                 timer->irq_dis = timer->io_base + OMAP_TIMER_V2_IRQENABLE_CLR;
 341                 timer->pend = timer->io_base +
 342                         _OMAP_TIMER_WRITE_PEND_OFFSET +
 343                                 OMAP_TIMER_V2_FUNC_OFFSET;
 344                 timer->func_base = timer->io_base + OMAP_TIMER_V2_FUNC_OFFSET;
 345         }
 346 }
 347
 348 /* Assumes the source clock has been set by caller */
 349 static inline void __omap_dm_timer_reset(struct omap_dm_timer *timer,
 350                                         int autoidle, int wakeup)
 351 {
 352         u32 l;
 353
 354         l = __raw_readl(timer->io_base + OMAP_TIMER_OCP_CFG_OFFSET);
 355         l |= 0x02 << 3;  /* Set to smart-idle mode */
 356         l |= 0x2 << 8;   /* Set clock activity to perserve f-clock on idle */
 357
 358         if (autoidle)
 359                 l |= 0x1 << 0;
 360
 361         if (wakeup)
 362                 l |= 1 << 2;
 363
 364         __raw_writel(l, timer->io_base + OMAP_TIMER_OCP_CFG_OFFSET);
 365 }
 366
 367 /*
 368  * __omap_dm_timer_enable_posted - enables write posted mode
 369  * @timer:      pointer to timer instance handle
 370  *
 371  * Enables the write posted mode for the timer. When posted mode is enabled
 372  * writes to certain timer registers are immediately acknowledged by the
 373  * internal bus and hence prevents stalling the CPU waiting for the write to
 374  * complete. Enabling this feature can improve performance for writing to the
 375  * timer registers.
 376  */
 377 static inline void __omap_dm_timer_enable_posted(struct omap_dm_timer *timer)
 378 {
 379         if (timer->posted)
 380                 return;
 381
 382         if (timer->errata & OMAP_TIMER_ERRATA_I103_I767)
 383                 return;
 384
 385         __omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG,
 386                               OMAP_TIMER_CTRL_POSTED, 0);
 387         timer->context.tsicr = OMAP_TIMER_CTRL_POSTED;
 388         timer->posted = OMAP_TIMER_POSTED;
 389 }
 390
 391 /**
 392  * __omap_dm_timer_override_errata - override errata flags for a timer
 393  * @timer:      pointer to timer handle
 394  * @errata:     errata flags to be ignored
 395  *
 396  * For a given timer, override a timer errata by clearing the flags
 397  * specified by the errata argument. A specific erratum should only be
 398  * overridden for a timer if the timer is used in such a way the erratum
 399  * has no impact.
 400  */
 401 static inline void __omap_dm_timer_override_errata(struct omap_dm_timer *timer,
 402                                                    u32 errata)
 403 {
 404         timer->errata &= ~errata;
 405 }
 406
 407 static inline int __omap_dm_timer_set_source(struct clk *timer_fck,
 408                                                 struct clk *parent)
 409 {
 410         int ret;
 411
 412         clk_disable(timer_fck);
 413         ret = clk_set_parent(timer_fck, parent);
 414         clk_enable(timer_fck);
 415
 416         /*
 417          * When the functional clock disappears, too quick writes seem
 418          * to cause an abort. XXX Is this still necessary?
 419          */
 420         __delay(300000);
 421
 422         return ret;
 423 }
 424
 425 static inline void __omap_dm_timer_stop(struct omap_dm_timer *timer,
 426                                         int posted, unsigned long rate)
 427 {
 428         u32 l;
 429
 430         l = __omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted);
 431         if (l & OMAP_TIMER_CTRL_ST) {
 432                 l &= ~0x1;
 433                 __omap_dm_timer_write(timer, OMAP_TIMER_CTRL_REG, l, posted);
 434 #ifdef CONFIG_ARCH_OMAP2PLUS
 435                 /* Readback to make sure write has completed */
 436                 __omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted);
 437                 /*
 438                  * Wait for functional clock period x 3.5 to make sure that
 439                  * timer is stopped
 440                  */
 441                 udelay(3500000 / rate + 1);
 442 #endif
 443         }
 444
 445         /* Ack possibly pending interrupt */
 446         __raw_writel(OMAP_TIMER_INT_OVERFLOW, timer->irq_stat);
 447 }
 448
 449 static inline void __omap_dm_timer_load_start(struct omap_dm_timer *timer,
 450                                                 u32 ctrl, unsigned int load,
 451                                                 int posted)
 452 {
 453         __omap_dm_timer_write(timer, OMAP_TIMER_COUNTER_REG, load, posted);
 454         __omap_dm_timer_write(timer, OMAP_TIMER_CTRL_REG, ctrl, posted);
 455 }
 456
 457 static inline void __omap_dm_timer_int_enable(struct omap_dm_timer *timer,
 458                                                 unsigned int value)
 459 {
 460         __raw_writel(value, timer->irq_ena);
 461         __omap_dm_timer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, value, 0);
 462 }
 463
 464 static inline unsigned int
 465 __omap_dm_timer_read_counter(struct omap_dm_timer *timer, int posted)
 466 {
 467         return __omap_dm_timer_read(timer, OMAP_TIMER_COUNTER_REG, posted);
 468 }
 469
 470 static inline void __omap_dm_timer_write_status(struct omap_dm_timer *timer,
 471                                                 unsigned int value)
 472 {
 473         __raw_writel(value, timer->irq_stat);
 474 }
 475
 476 #endif /* __ASM_ARCH_DMTIMER_H */