2 * linux/arch/arm/plat-omap/gpio.c
4 * Support functions for OMAP GPIO
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
9 * Copyright (C) 2009 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/interrupt.h>
20 #include <linux/sysdev.h>
21 #include <linux/err.h>
22 #include <linux/clk.h>
24 #include <linux/slab.h>
25 #include <linux/pm_runtime.h>
27 #include <mach/hardware.h>
29 #include <mach/irqs.h>
30 #include <mach/gpio.h>
31 #include <asm/mach/irq.h>
34 * OMAP1510 GPIO registers
36 #define OMAP1510_GPIO_DATA_INPUT 0x00
37 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
38 #define OMAP1510_GPIO_DIR_CONTROL 0x08
39 #define OMAP1510_GPIO_INT_CONTROL 0x0c
40 #define OMAP1510_GPIO_INT_MASK 0x10
41 #define OMAP1510_GPIO_INT_STATUS 0x14
42 #define OMAP1510_GPIO_PIN_CONTROL 0x18
44 #define OMAP1510_IH_GPIO_BASE 64
47 * OMAP1610 specific GPIO registers
49 #define OMAP1610_GPIO_REVISION 0x0000
50 #define OMAP1610_GPIO_SYSCONFIG 0x0010
51 #define OMAP1610_GPIO_SYSSTATUS 0x0014
52 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
53 #define OMAP1610_GPIO_IRQENABLE1 0x001c
54 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
55 #define OMAP1610_GPIO_DATAIN 0x002c
56 #define OMAP1610_GPIO_DATAOUT 0x0030
57 #define OMAP1610_GPIO_DIRECTION 0x0034
58 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
59 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
60 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
61 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
62 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
63 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
64 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
65 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
68 * OMAP7XX specific GPIO registers
70 #define OMAP7XX_GPIO_DATA_INPUT 0x00
71 #define OMAP7XX_GPIO_DATA_OUTPUT 0x04
72 #define OMAP7XX_GPIO_DIR_CONTROL 0x08
73 #define OMAP7XX_GPIO_INT_CONTROL 0x0c
74 #define OMAP7XX_GPIO_INT_MASK 0x10
75 #define OMAP7XX_GPIO_INT_STATUS 0x14
78 * omap2+ specific GPIO registers
80 #define OMAP24XX_GPIO_REVISION 0x0000
81 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
82 #define OMAP24XX_GPIO_IRQSTATUS2 0x0028
83 #define OMAP24XX_GPIO_IRQENABLE2 0x002c
84 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
85 #define OMAP24XX_GPIO_WAKE_EN 0x0020
86 #define OMAP24XX_GPIO_CTRL 0x0030
87 #define OMAP24XX_GPIO_OE 0x0034
88 #define OMAP24XX_GPIO_DATAIN 0x0038
89 #define OMAP24XX_GPIO_DATAOUT 0x003c
90 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
91 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
92 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
93 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
94 #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
95 #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
96 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
97 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
98 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
99 #define OMAP24XX_GPIO_SETWKUENA 0x0084
100 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
101 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
103 #define OMAP4_GPIO_REVISION 0x0000
104 #define OMAP4_GPIO_EOI 0x0020
105 #define OMAP4_GPIO_IRQSTATUSRAW0 0x0024
106 #define OMAP4_GPIO_IRQSTATUSRAW1 0x0028
107 #define OMAP4_GPIO_IRQSTATUS0 0x002c
108 #define OMAP4_GPIO_IRQSTATUS1 0x0030
109 #define OMAP4_GPIO_IRQSTATUSSET0 0x0034
110 #define OMAP4_GPIO_IRQSTATUSSET1 0x0038
111 #define OMAP4_GPIO_IRQSTATUSCLR0 0x003c
112 #define OMAP4_GPIO_IRQSTATUSCLR1 0x0040
113 #define OMAP4_GPIO_IRQWAKEN0 0x0044
114 #define OMAP4_GPIO_IRQWAKEN1 0x0048
115 #define OMAP4_GPIO_IRQENABLE1 0x011c
116 #define OMAP4_GPIO_WAKE_EN 0x0120
117 #define OMAP4_GPIO_IRQSTATUS2 0x0128
118 #define OMAP4_GPIO_IRQENABLE2 0x012c
119 #define OMAP4_GPIO_CTRL 0x0130
120 #define OMAP4_GPIO_OE 0x0134
121 #define OMAP4_GPIO_DATAIN 0x0138
122 #define OMAP4_GPIO_DATAOUT 0x013c
123 #define OMAP4_GPIO_LEVELDETECT0 0x0140
124 #define OMAP4_GPIO_LEVELDETECT1 0x0144
125 #define OMAP4_GPIO_RISINGDETECT 0x0148
126 #define OMAP4_GPIO_FALLINGDETECT 0x014c
127 #define OMAP4_GPIO_DEBOUNCENABLE 0x0150
128 #define OMAP4_GPIO_DEBOUNCINGTIME 0x0154
129 #define OMAP4_GPIO_CLEARIRQENABLE1 0x0160
130 #define OMAP4_GPIO_SETIRQENABLE1 0x0164
131 #define OMAP4_GPIO_CLEARWKUENA 0x0180
132 #define OMAP4_GPIO_SETWKUENA 0x0184
133 #define OMAP4_GPIO_CLEARDATAOUT 0x0190
134 #define OMAP4_GPIO_SETDATAOUT 0x0194
140 u16 virtual_irq_start;
142 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
146 u32 non_wakeup_gpios;
147 u32 enabled_non_wakeup_gpios;
150 u32 saved_fallingdetect;
151 u32 saved_risingdetect;
155 struct gpio_chip chip;
158 u32 dbck_enable_mask;
164 #ifdef CONFIG_ARCH_OMAP3
165 struct omap3_gpio_regs {
178 static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
182 * TODO: Cleanup gpio_bank usage as it is having information
183 * related to all instances of the device
185 static struct gpio_bank *gpio_bank;
187 static int bank_width;
189 /* TODO: Analyze removing gpio_bank_count usage from driver code */
192 static inline struct gpio_bank *get_gpio_bank(int gpio)
194 if (cpu_is_omap15xx()) {
195 if (OMAP_GPIO_IS_MPUIO(gpio))
196 return &gpio_bank[0];
197 return &gpio_bank[1];
199 if (cpu_is_omap16xx()) {
200 if (OMAP_GPIO_IS_MPUIO(gpio))
201 return &gpio_bank[0];
202 return &gpio_bank[1 + (gpio >> 4)];
204 if (cpu_is_omap7xx()) {
205 if (OMAP_GPIO_IS_MPUIO(gpio))
206 return &gpio_bank[0];
207 return &gpio_bank[1 + (gpio >> 5)];
209 if (cpu_is_omap24xx())
210 return &gpio_bank[gpio >> 5];
211 if (cpu_is_omap34xx() || cpu_is_omap44xx())
212 return &gpio_bank[gpio >> 5];
217 static inline int get_gpio_index(int gpio)
219 if (cpu_is_omap7xx())
221 if (cpu_is_omap24xx())
223 if (cpu_is_omap34xx() || cpu_is_omap44xx())
228 static inline int gpio_valid(int gpio)
232 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
233 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
237 if (cpu_is_omap15xx() && gpio < 16)
239 if ((cpu_is_omap16xx()) && gpio < 64)
241 if (cpu_is_omap7xx() && gpio < 192)
243 if (cpu_is_omap2420() && gpio < 128)
245 if (cpu_is_omap2430() && gpio < 160)
247 if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192)
252 static int check_gpio(int gpio)
254 if (unlikely(gpio_valid(gpio) < 0)) {
255 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
262 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
264 void __iomem *reg = bank->base;
267 switch (bank->method) {
268 #ifdef CONFIG_ARCH_OMAP1
270 reg += OMAP_MPUIO_IO_CNTL / bank->stride;
273 #ifdef CONFIG_ARCH_OMAP15XX
274 case METHOD_GPIO_1510:
275 reg += OMAP1510_GPIO_DIR_CONTROL;
278 #ifdef CONFIG_ARCH_OMAP16XX
279 case METHOD_GPIO_1610:
280 reg += OMAP1610_GPIO_DIRECTION;
283 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
284 case METHOD_GPIO_7XX:
285 reg += OMAP7XX_GPIO_DIR_CONTROL;
288 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
289 case METHOD_GPIO_24XX:
290 reg += OMAP24XX_GPIO_OE;
293 #if defined(CONFIG_ARCH_OMAP4)
294 case METHOD_GPIO_44XX:
295 reg += OMAP4_GPIO_OE;
302 l = __raw_readl(reg);
307 __raw_writel(l, reg);
310 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
312 void __iomem *reg = bank->base;
315 switch (bank->method) {
316 #ifdef CONFIG_ARCH_OMAP1
318 reg += OMAP_MPUIO_OUTPUT / bank->stride;
319 l = __raw_readl(reg);
326 #ifdef CONFIG_ARCH_OMAP15XX
327 case METHOD_GPIO_1510:
328 reg += OMAP1510_GPIO_DATA_OUTPUT;
329 l = __raw_readl(reg);
336 #ifdef CONFIG_ARCH_OMAP16XX
337 case METHOD_GPIO_1610:
339 reg += OMAP1610_GPIO_SET_DATAOUT;
341 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
345 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
346 case METHOD_GPIO_7XX:
347 reg += OMAP7XX_GPIO_DATA_OUTPUT;
348 l = __raw_readl(reg);
355 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
356 case METHOD_GPIO_24XX:
358 reg += OMAP24XX_GPIO_SETDATAOUT;
360 reg += OMAP24XX_GPIO_CLEARDATAOUT;
364 #ifdef CONFIG_ARCH_OMAP4
365 case METHOD_GPIO_44XX:
367 reg += OMAP4_GPIO_SETDATAOUT;
369 reg += OMAP4_GPIO_CLEARDATAOUT;
377 __raw_writel(l, reg);
380 static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
384 if (check_gpio(gpio) < 0)
387 switch (bank->method) {
388 #ifdef CONFIG_ARCH_OMAP1
390 reg += OMAP_MPUIO_INPUT_LATCH / bank->stride;
393 #ifdef CONFIG_ARCH_OMAP15XX
394 case METHOD_GPIO_1510:
395 reg += OMAP1510_GPIO_DATA_INPUT;
398 #ifdef CONFIG_ARCH_OMAP16XX
399 case METHOD_GPIO_1610:
400 reg += OMAP1610_GPIO_DATAIN;
403 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
404 case METHOD_GPIO_7XX:
405 reg += OMAP7XX_GPIO_DATA_INPUT;
408 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
409 case METHOD_GPIO_24XX:
410 reg += OMAP24XX_GPIO_DATAIN;
413 #ifdef CONFIG_ARCH_OMAP4
414 case METHOD_GPIO_44XX:
415 reg += OMAP4_GPIO_DATAIN;
421 return (__raw_readl(reg)
422 & (1 << get_gpio_index(gpio))) != 0;
425 static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
429 if (check_gpio(gpio) < 0)
433 switch (bank->method) {
434 #ifdef CONFIG_ARCH_OMAP1
436 reg += OMAP_MPUIO_OUTPUT / bank->stride;
439 #ifdef CONFIG_ARCH_OMAP15XX
440 case METHOD_GPIO_1510:
441 reg += OMAP1510_GPIO_DATA_OUTPUT;
444 #ifdef CONFIG_ARCH_OMAP16XX
445 case METHOD_GPIO_1610:
446 reg += OMAP1610_GPIO_DATAOUT;
449 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
450 case METHOD_GPIO_7XX:
451 reg += OMAP7XX_GPIO_DATA_OUTPUT;
454 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
455 case METHOD_GPIO_24XX:
456 reg += OMAP24XX_GPIO_DATAOUT;
459 #ifdef CONFIG_ARCH_OMAP4
460 case METHOD_GPIO_44XX:
461 reg += OMAP4_GPIO_DATAOUT;
468 return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0;
471 #define MOD_REG_BIT(reg, bit_mask, set) \
473 int l = __raw_readl(base + reg); \
474 if (set) l |= bit_mask; \
475 else l &= ~bit_mask; \
476 __raw_writel(l, base + reg); \
480 * _set_gpio_debounce - low level gpio debounce time
481 * @bank: the gpio bank we're acting upon
482 * @gpio: the gpio number on this @gpio
483 * @debounce: debounce time to use
485 * OMAP's debounce time is in 31us steps so we need
486 * to convert and round up to the closest unit.
488 static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
491 void __iomem *reg = bank->base;
495 if (!bank->dbck_flag)
500 else if (debounce > 7936)
503 debounce = (debounce / 0x1f) - 1;
505 l = 1 << get_gpio_index(gpio);
507 if (bank->method == METHOD_GPIO_44XX)
508 reg += OMAP4_GPIO_DEBOUNCINGTIME;
510 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
512 __raw_writel(debounce, reg);
515 if (bank->method == METHOD_GPIO_44XX)
516 reg += OMAP4_GPIO_DEBOUNCENABLE;
518 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
520 val = __raw_readl(reg);
524 clk_enable(bank->dbck);
527 clk_disable(bank->dbck);
529 bank->dbck_enable_mask = val;
531 __raw_writel(val, reg);
534 #ifdef CONFIG_ARCH_OMAP2PLUS
535 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
538 void __iomem *base = bank->base;
539 u32 gpio_bit = 1 << gpio;
542 if (cpu_is_omap44xx()) {
543 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
544 trigger & IRQ_TYPE_LEVEL_LOW);
545 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
546 trigger & IRQ_TYPE_LEVEL_HIGH);
547 MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
548 trigger & IRQ_TYPE_EDGE_RISING);
549 MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
550 trigger & IRQ_TYPE_EDGE_FALLING);
552 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
553 trigger & IRQ_TYPE_LEVEL_LOW);
554 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
555 trigger & IRQ_TYPE_LEVEL_HIGH);
556 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
557 trigger & IRQ_TYPE_EDGE_RISING);
558 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
559 trigger & IRQ_TYPE_EDGE_FALLING);
561 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
562 if (cpu_is_omap44xx()) {
564 __raw_writel(1 << gpio, bank->base+
565 OMAP4_GPIO_IRQWAKEN0);
567 val = __raw_readl(bank->base +
568 OMAP4_GPIO_IRQWAKEN0);
569 __raw_writel(val & (~(1 << gpio)), bank->base +
570 OMAP4_GPIO_IRQWAKEN0);
574 * GPIO wakeup request can only be generated on edge
577 if (trigger & IRQ_TYPE_EDGE_BOTH)
578 __raw_writel(1 << gpio, bank->base
579 + OMAP24XX_GPIO_SETWKUENA);
581 __raw_writel(1 << gpio, bank->base
582 + OMAP24XX_GPIO_CLEARWKUENA);
585 /* This part needs to be executed always for OMAP34xx */
586 if (cpu_is_omap34xx() || (bank->non_wakeup_gpios & gpio_bit)) {
588 * Log the edge gpio and manually trigger the IRQ
589 * after resume if the input level changes
590 * to avoid irq lost during PER RET/OFF mode
591 * Applies for omap2 non-wakeup gpio and all omap3 gpios
593 if (trigger & IRQ_TYPE_EDGE_BOTH)
594 bank->enabled_non_wakeup_gpios |= gpio_bit;
596 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
599 if (cpu_is_omap44xx()) {
601 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
602 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
605 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
606 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
611 #ifdef CONFIG_ARCH_OMAP1
613 * This only applies to chips that can't do both rising and falling edge
614 * detection at once. For all other chips, this function is a noop.
616 static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
618 void __iomem *reg = bank->base;
621 switch (bank->method) {
623 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
625 #ifdef CONFIG_ARCH_OMAP15XX
626 case METHOD_GPIO_1510:
627 reg += OMAP1510_GPIO_INT_CONTROL;
630 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
631 case METHOD_GPIO_7XX:
632 reg += OMAP7XX_GPIO_INT_CONTROL;
639 l = __raw_readl(reg);
645 __raw_writel(l, reg);
649 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
651 void __iomem *reg = bank->base;
654 switch (bank->method) {
655 #ifdef CONFIG_ARCH_OMAP1
657 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
658 l = __raw_readl(reg);
659 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
660 bank->toggle_mask |= 1 << gpio;
661 if (trigger & IRQ_TYPE_EDGE_RISING)
663 else if (trigger & IRQ_TYPE_EDGE_FALLING)
669 #ifdef CONFIG_ARCH_OMAP15XX
670 case METHOD_GPIO_1510:
671 reg += OMAP1510_GPIO_INT_CONTROL;
672 l = __raw_readl(reg);
673 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
674 bank->toggle_mask |= 1 << gpio;
675 if (trigger & IRQ_TYPE_EDGE_RISING)
677 else if (trigger & IRQ_TYPE_EDGE_FALLING)
683 #ifdef CONFIG_ARCH_OMAP16XX
684 case METHOD_GPIO_1610:
686 reg += OMAP1610_GPIO_EDGE_CTRL2;
688 reg += OMAP1610_GPIO_EDGE_CTRL1;
690 l = __raw_readl(reg);
691 l &= ~(3 << (gpio << 1));
692 if (trigger & IRQ_TYPE_EDGE_RISING)
693 l |= 2 << (gpio << 1);
694 if (trigger & IRQ_TYPE_EDGE_FALLING)
695 l |= 1 << (gpio << 1);
697 /* Enable wake-up during idle for dynamic tick */
698 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
700 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
703 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
704 case METHOD_GPIO_7XX:
705 reg += OMAP7XX_GPIO_INT_CONTROL;
706 l = __raw_readl(reg);
707 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
708 bank->toggle_mask |= 1 << gpio;
709 if (trigger & IRQ_TYPE_EDGE_RISING)
711 else if (trigger & IRQ_TYPE_EDGE_FALLING)
717 #ifdef CONFIG_ARCH_OMAP2PLUS
718 case METHOD_GPIO_24XX:
719 case METHOD_GPIO_44XX:
720 set_24xx_gpio_triggering(bank, gpio, trigger);
726 __raw_writel(l, reg);
732 static int gpio_irq_type(struct irq_data *d, unsigned type)
734 struct gpio_bank *bank;
739 if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE)
740 gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
742 gpio = d->irq - IH_GPIO_BASE;
744 if (check_gpio(gpio) < 0)
747 if (type & ~IRQ_TYPE_SENSE_MASK)
750 /* OMAP1 allows only only edge triggering */
751 if (!cpu_class_is_omap2()
752 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
755 bank = irq_data_get_irq_chip_data(d);
756 spin_lock_irqsave(&bank->lock, flags);
757 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
759 irq_desc[d->irq].status &= ~IRQ_TYPE_SENSE_MASK;
760 irq_desc[d->irq].status |= type;
762 spin_unlock_irqrestore(&bank->lock, flags);
764 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
765 __set_irq_handler_unlocked(d->irq, handle_level_irq);
766 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
767 __set_irq_handler_unlocked(d->irq, handle_edge_irq);
772 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
774 void __iomem *reg = bank->base;
776 switch (bank->method) {
777 #ifdef CONFIG_ARCH_OMAP1
779 /* MPUIO irqstatus is reset by reading the status register,
780 * so do nothing here */
783 #ifdef CONFIG_ARCH_OMAP15XX
784 case METHOD_GPIO_1510:
785 reg += OMAP1510_GPIO_INT_STATUS;
788 #ifdef CONFIG_ARCH_OMAP16XX
789 case METHOD_GPIO_1610:
790 reg += OMAP1610_GPIO_IRQSTATUS1;
793 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
794 case METHOD_GPIO_7XX:
795 reg += OMAP7XX_GPIO_INT_STATUS;
798 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
799 case METHOD_GPIO_24XX:
800 reg += OMAP24XX_GPIO_IRQSTATUS1;
803 #if defined(CONFIG_ARCH_OMAP4)
804 case METHOD_GPIO_44XX:
805 reg += OMAP4_GPIO_IRQSTATUS0;
812 __raw_writel(gpio_mask, reg);
814 /* Workaround for clearing DSP GPIO interrupts to allow retention */
815 if (cpu_is_omap24xx() || cpu_is_omap34xx())
816 reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
817 else if (cpu_is_omap44xx())
818 reg = bank->base + OMAP4_GPIO_IRQSTATUS1;
820 if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
821 __raw_writel(gpio_mask, reg);
823 /* Flush posted write for the irq status to avoid spurious interrupts */
828 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
830 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
833 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
835 void __iomem *reg = bank->base;
840 switch (bank->method) {
841 #ifdef CONFIG_ARCH_OMAP1
843 reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride;
848 #ifdef CONFIG_ARCH_OMAP15XX
849 case METHOD_GPIO_1510:
850 reg += OMAP1510_GPIO_INT_MASK;
855 #ifdef CONFIG_ARCH_OMAP16XX
856 case METHOD_GPIO_1610:
857 reg += OMAP1610_GPIO_IRQENABLE1;
861 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
862 case METHOD_GPIO_7XX:
863 reg += OMAP7XX_GPIO_INT_MASK;
868 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
869 case METHOD_GPIO_24XX:
870 reg += OMAP24XX_GPIO_IRQENABLE1;
874 #if defined(CONFIG_ARCH_OMAP4)
875 case METHOD_GPIO_44XX:
876 reg += OMAP4_GPIO_IRQSTATUSSET0;
885 l = __raw_readl(reg);
892 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
894 void __iomem *reg = bank->base;
897 switch (bank->method) {
898 #ifdef CONFIG_ARCH_OMAP1
900 reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride;
901 l = __raw_readl(reg);
908 #ifdef CONFIG_ARCH_OMAP15XX
909 case METHOD_GPIO_1510:
910 reg += OMAP1510_GPIO_INT_MASK;
911 l = __raw_readl(reg);
918 #ifdef CONFIG_ARCH_OMAP16XX
919 case METHOD_GPIO_1610:
921 reg += OMAP1610_GPIO_SET_IRQENABLE1;
923 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
927 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
928 case METHOD_GPIO_7XX:
929 reg += OMAP7XX_GPIO_INT_MASK;
930 l = __raw_readl(reg);
937 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
938 case METHOD_GPIO_24XX:
940 reg += OMAP24XX_GPIO_SETIRQENABLE1;
942 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
946 #ifdef CONFIG_ARCH_OMAP4
947 case METHOD_GPIO_44XX:
949 reg += OMAP4_GPIO_IRQSTATUSSET0;
951 reg += OMAP4_GPIO_IRQSTATUSCLR0;
959 __raw_writel(l, reg);
962 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
964 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
968 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
969 * 1510 does not seem to have a wake-up register. If JTAG is connected
970 * to the target, system will wake up always on GPIO events. While
971 * system is running all registered GPIO interrupts need to have wake-up
972 * enabled. When system is suspended, only selected GPIO interrupts need
973 * to have wake-up enabled.
975 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
977 unsigned long uninitialized_var(flags);
979 switch (bank->method) {
980 #ifdef CONFIG_ARCH_OMAP16XX
982 case METHOD_GPIO_1610:
983 spin_lock_irqsave(&bank->lock, flags);
985 bank->suspend_wakeup |= (1 << gpio);
987 bank->suspend_wakeup &= ~(1 << gpio);
988 spin_unlock_irqrestore(&bank->lock, flags);
991 #ifdef CONFIG_ARCH_OMAP2PLUS
992 case METHOD_GPIO_24XX:
993 case METHOD_GPIO_44XX:
994 if (bank->non_wakeup_gpios & (1 << gpio)) {
995 printk(KERN_ERR "Unable to modify wakeup on "
996 "non-wakeup GPIO%d\n",
997 (bank - gpio_bank) * 32 + gpio);
1000 spin_lock_irqsave(&bank->lock, flags);
1002 bank->suspend_wakeup |= (1 << gpio);
1004 bank->suspend_wakeup &= ~(1 << gpio);
1005 spin_unlock_irqrestore(&bank->lock, flags);
1009 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
1015 static void _reset_gpio(struct gpio_bank *bank, int gpio)
1017 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
1018 _set_gpio_irqenable(bank, gpio, 0);
1019 _clear_gpio_irqstatus(bank, gpio);
1020 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
1023 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
1024 static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
1026 unsigned int gpio = d->irq - IH_GPIO_BASE;
1027 struct gpio_bank *bank;
1030 if (check_gpio(gpio) < 0)
1032 bank = irq_data_get_irq_chip_data(d);
1033 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
1038 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
1040 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
1041 unsigned long flags;
1043 spin_lock_irqsave(&bank->lock, flags);
1045 /* Set trigger to none. You need to enable the desired trigger with
1046 * request_irq() or set_irq_type().
1048 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
1050 #ifdef CONFIG_ARCH_OMAP15XX
1051 if (bank->method == METHOD_GPIO_1510) {
1054 /* Claim the pin for MPU */
1055 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
1056 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
1059 if (!cpu_class_is_omap1()) {
1060 if (!bank->mod_usage) {
1061 void __iomem *reg = bank->base;
1064 if (cpu_is_omap24xx() || cpu_is_omap34xx())
1065 reg += OMAP24XX_GPIO_CTRL;
1066 else if (cpu_is_omap44xx())
1067 reg += OMAP4_GPIO_CTRL;
1068 ctrl = __raw_readl(reg);
1069 /* Module is enabled, clocks are not gated */
1071 __raw_writel(ctrl, reg);
1073 bank->mod_usage |= 1 << offset;
1075 spin_unlock_irqrestore(&bank->lock, flags);
1080 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
1082 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
1083 unsigned long flags;
1085 spin_lock_irqsave(&bank->lock, flags);
1086 #ifdef CONFIG_ARCH_OMAP16XX
1087 if (bank->method == METHOD_GPIO_1610) {
1088 /* Disable wake-up during idle for dynamic tick */
1089 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1090 __raw_writel(1 << offset, reg);
1093 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1094 if (bank->method == METHOD_GPIO_24XX) {
1095 /* Disable wake-up during idle for dynamic tick */
1096 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1097 __raw_writel(1 << offset, reg);
1100 #ifdef CONFIG_ARCH_OMAP4
1101 if (bank->method == METHOD_GPIO_44XX) {
1102 /* Disable wake-up during idle for dynamic tick */
1103 void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0;
1104 __raw_writel(1 << offset, reg);
1107 if (!cpu_class_is_omap1()) {
1108 bank->mod_usage &= ~(1 << offset);
1109 if (!bank->mod_usage) {
1110 void __iomem *reg = bank->base;
1113 if (cpu_is_omap24xx() || cpu_is_omap34xx())
1114 reg += OMAP24XX_GPIO_CTRL;
1115 else if (cpu_is_omap44xx())
1116 reg += OMAP4_GPIO_CTRL;
1117 ctrl = __raw_readl(reg);
1118 /* Module is disabled, clocks are gated */
1120 __raw_writel(ctrl, reg);
1123 _reset_gpio(bank, bank->chip.base + offset);
1124 spin_unlock_irqrestore(&bank->lock, flags);
1128 * We need to unmask the GPIO bank interrupt as soon as possible to
1129 * avoid missing GPIO interrupts for other lines in the bank.
1130 * Then we need to mask-read-clear-unmask the triggered GPIO lines
1131 * in the bank to avoid missing nested interrupts for a GPIO line.
1132 * If we wait to unmask individual GPIO lines in the bank after the
1133 * line's interrupt handler has been run, we may miss some nested
1136 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1138 void __iomem *isr_reg = NULL;
1140 unsigned int gpio_irq, gpio_index;
1141 struct gpio_bank *bank;
1145 desc->irq_data.chip->irq_ack(&desc->irq_data);
1147 bank = get_irq_data(irq);
1148 #ifdef CONFIG_ARCH_OMAP1
1149 if (bank->method == METHOD_MPUIO)
1150 isr_reg = bank->base +
1151 OMAP_MPUIO_GPIO_INT / bank->stride;
1153 #ifdef CONFIG_ARCH_OMAP15XX
1154 if (bank->method == METHOD_GPIO_1510)
1155 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1157 #if defined(CONFIG_ARCH_OMAP16XX)
1158 if (bank->method == METHOD_GPIO_1610)
1159 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1161 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1162 if (bank->method == METHOD_GPIO_7XX)
1163 isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS;
1165 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1166 if (bank->method == METHOD_GPIO_24XX)
1167 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
1169 #if defined(CONFIG_ARCH_OMAP4)
1170 if (bank->method == METHOD_GPIO_44XX)
1171 isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0;
1174 if (WARN_ON(!isr_reg))
1178 u32 isr_saved, level_mask = 0;
1181 enabled = _get_gpio_irqbank_mask(bank);
1182 isr_saved = isr = __raw_readl(isr_reg) & enabled;
1184 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1187 if (cpu_class_is_omap2()) {
1188 level_mask = bank->level_mask & enabled;
1191 /* clear edge sensitive interrupts before handler(s) are
1192 called so that we don't miss any interrupt occurred while
1194 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1195 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1196 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1198 /* if there is only edge sensitive GPIO pin interrupts
1199 configured, we could unmask GPIO bank interrupt immediately */
1200 if (!level_mask && !unmasked) {
1202 desc->irq_data.chip->irq_unmask(&desc->irq_data);
1210 gpio_irq = bank->virtual_irq_start;
1211 for (; isr != 0; isr >>= 1, gpio_irq++) {
1212 gpio_index = get_gpio_index(irq_to_gpio(gpio_irq));
1217 #ifdef CONFIG_ARCH_OMAP1
1219 * Some chips can't respond to both rising and falling
1220 * at the same time. If this irq was requested with
1221 * both flags, we need to flip the ICR data for the IRQ
1222 * to respond to the IRQ for the opposite direction.
1223 * This will be indicated in the bank toggle_mask.
1225 if (bank->toggle_mask & (1 << gpio_index))
1226 _toggle_gpio_edge_triggering(bank, gpio_index);
1229 generic_handle_irq(gpio_irq);
1232 /* if bank has any level sensitive GPIO pin interrupt
1233 configured, we must unmask the bank interrupt only after
1234 handler(s) are executed in order to avoid spurious bank
1238 desc->irq_data.chip->irq_unmask(&desc->irq_data);
1241 static void gpio_irq_shutdown(struct irq_data *d)
1243 unsigned int gpio = d->irq - IH_GPIO_BASE;
1244 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1246 _reset_gpio(bank, gpio);
1249 static void gpio_ack_irq(struct irq_data *d)
1251 unsigned int gpio = d->irq - IH_GPIO_BASE;
1252 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1254 _clear_gpio_irqstatus(bank, gpio);
1257 static void gpio_mask_irq(struct irq_data *d)
1259 unsigned int gpio = d->irq - IH_GPIO_BASE;
1260 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1262 _set_gpio_irqenable(bank, gpio, 0);
1263 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
1266 static void gpio_unmask_irq(struct irq_data *d)
1268 unsigned int gpio = d->irq - IH_GPIO_BASE;
1269 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1270 unsigned int irq_mask = 1 << get_gpio_index(gpio);
1271 struct irq_desc *desc = irq_to_desc(d->irq);
1272 u32 trigger = desc->status & IRQ_TYPE_SENSE_MASK;
1275 _set_gpio_triggering(bank, get_gpio_index(gpio), trigger);
1277 /* For level-triggered GPIOs, the clearing must be done after
1278 * the HW source is cleared, thus after the handler has run */
1279 if (bank->level_mask & irq_mask) {
1280 _set_gpio_irqenable(bank, gpio, 0);
1281 _clear_gpio_irqstatus(bank, gpio);
1284 _set_gpio_irqenable(bank, gpio, 1);
1287 static struct irq_chip gpio_irq_chip = {
1289 .irq_shutdown = gpio_irq_shutdown,
1290 .irq_ack = gpio_ack_irq,
1291 .irq_mask = gpio_mask_irq,
1292 .irq_unmask = gpio_unmask_irq,
1293 .irq_set_type = gpio_irq_type,
1294 .irq_set_wake = gpio_wake_enable,
1297 /*---------------------------------------------------------------------*/
1299 #ifdef CONFIG_ARCH_OMAP1
1301 /* MPUIO uses the always-on 32k clock */
1303 static void mpuio_ack_irq(struct irq_data *d)
1305 /* The ISR is reset automatically, so do nothing here. */
1308 static void mpuio_mask_irq(struct irq_data *d)
1310 unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
1311 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1313 _set_gpio_irqenable(bank, gpio, 0);
1316 static void mpuio_unmask_irq(struct irq_data *d)
1318 unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
1319 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
1321 _set_gpio_irqenable(bank, gpio, 1);
1324 static struct irq_chip mpuio_irq_chip = {
1326 .irq_ack = mpuio_ack_irq,
1327 .irq_mask = mpuio_mask_irq,
1328 .irq_unmask = mpuio_unmask_irq,
1329 .irq_set_type = gpio_irq_type,
1330 #ifdef CONFIG_ARCH_OMAP16XX
1331 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1332 .irq_set_wake = gpio_wake_enable,
1337 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1340 #ifdef CONFIG_ARCH_OMAP16XX
1342 #include <linux/platform_device.h>
1344 static int omap_mpuio_suspend_noirq(struct device *dev)
1346 struct platform_device *pdev = to_platform_device(dev);
1347 struct gpio_bank *bank = platform_get_drvdata(pdev);
1348 void __iomem *mask_reg = bank->base +
1349 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
1350 unsigned long flags;
1352 spin_lock_irqsave(&bank->lock, flags);
1353 bank->saved_wakeup = __raw_readl(mask_reg);
1354 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
1355 spin_unlock_irqrestore(&bank->lock, flags);
1360 static int omap_mpuio_resume_noirq(struct device *dev)
1362 struct platform_device *pdev = to_platform_device(dev);
1363 struct gpio_bank *bank = platform_get_drvdata(pdev);
1364 void __iomem *mask_reg = bank->base +
1365 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
1366 unsigned long flags;
1368 spin_lock_irqsave(&bank->lock, flags);
1369 __raw_writel(bank->saved_wakeup, mask_reg);
1370 spin_unlock_irqrestore(&bank->lock, flags);
1375 static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
1376 .suspend_noirq = omap_mpuio_suspend_noirq,
1377 .resume_noirq = omap_mpuio_resume_noirq,
1380 /* use platform_driver for this, now that there's no longer any
1381 * point to sys_device (other than not disturbing old code).
1383 static struct platform_driver omap_mpuio_driver = {
1386 .pm = &omap_mpuio_dev_pm_ops,
1390 static struct platform_device omap_mpuio_device = {
1394 .driver = &omap_mpuio_driver.driver,
1396 /* could list the /proc/iomem resources */
1399 static inline void mpuio_init(void)
1401 struct gpio_bank *bank = get_gpio_bank(OMAP_MPUIO(0));
1402 platform_set_drvdata(&omap_mpuio_device, bank);
1404 if (platform_driver_register(&omap_mpuio_driver) == 0)
1405 (void) platform_device_register(&omap_mpuio_device);
1409 static inline void mpuio_init(void) {}
1414 extern struct irq_chip mpuio_irq_chip;
1416 #define bank_is_mpuio(bank) 0
1417 static inline void mpuio_init(void) {}
1421 /*---------------------------------------------------------------------*/
1423 /* REVISIT these are stupid implementations! replace by ones that
1424 * don't switch on METHOD_* and which mostly avoid spinlocks
1427 static int gpio_input(struct gpio_chip *chip, unsigned offset)
1429 struct gpio_bank *bank;
1430 unsigned long flags;
1432 bank = container_of(chip, struct gpio_bank, chip);
1433 spin_lock_irqsave(&bank->lock, flags);
1434 _set_gpio_direction(bank, offset, 1);
1435 spin_unlock_irqrestore(&bank->lock, flags);
1439 static int gpio_is_input(struct gpio_bank *bank, int mask)
1441 void __iomem *reg = bank->base;
1443 switch (bank->method) {
1445 reg += OMAP_MPUIO_IO_CNTL / bank->stride;
1447 case METHOD_GPIO_1510:
1448 reg += OMAP1510_GPIO_DIR_CONTROL;
1450 case METHOD_GPIO_1610:
1451 reg += OMAP1610_GPIO_DIRECTION;
1453 case METHOD_GPIO_7XX:
1454 reg += OMAP7XX_GPIO_DIR_CONTROL;
1456 case METHOD_GPIO_24XX:
1457 reg += OMAP24XX_GPIO_OE;
1459 case METHOD_GPIO_44XX:
1460 reg += OMAP4_GPIO_OE;
1463 WARN_ONCE(1, "gpio_is_input: incorrect OMAP GPIO method");
1466 return __raw_readl(reg) & mask;
1469 static int gpio_get(struct gpio_chip *chip, unsigned offset)
1471 struct gpio_bank *bank;
1476 gpio = chip->base + offset;
1477 bank = get_gpio_bank(gpio);
1479 mask = 1 << get_gpio_index(gpio);
1481 if (gpio_is_input(bank, mask))
1482 return _get_gpio_datain(bank, gpio);
1484 return _get_gpio_dataout(bank, gpio);
1487 static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1489 struct gpio_bank *bank;
1490 unsigned long flags;
1492 bank = container_of(chip, struct gpio_bank, chip);
1493 spin_lock_irqsave(&bank->lock, flags);
1494 _set_gpio_dataout(bank, offset, value);
1495 _set_gpio_direction(bank, offset, 0);
1496 spin_unlock_irqrestore(&bank->lock, flags);
1500 static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
1503 struct gpio_bank *bank;
1504 unsigned long flags;
1506 bank = container_of(chip, struct gpio_bank, chip);
1509 bank->dbck = clk_get(bank->dev, "dbclk");
1510 if (IS_ERR(bank->dbck))
1511 dev_err(bank->dev, "Could not get gpio dbck\n");
1514 spin_lock_irqsave(&bank->lock, flags);
1515 _set_gpio_debounce(bank, offset, debounce);
1516 spin_unlock_irqrestore(&bank->lock, flags);
1521 static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1523 struct gpio_bank *bank;
1524 unsigned long flags;
1526 bank = container_of(chip, struct gpio_bank, chip);
1527 spin_lock_irqsave(&bank->lock, flags);
1528 _set_gpio_dataout(bank, offset, value);
1529 spin_unlock_irqrestore(&bank->lock, flags);
1532 static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1534 struct gpio_bank *bank;
1536 bank = container_of(chip, struct gpio_bank, chip);
1537 return bank->virtual_irq_start + offset;
1540 /*---------------------------------------------------------------------*/
1542 static void __init omap_gpio_show_rev(struct gpio_bank *bank)
1546 if (cpu_is_omap16xx() && !(bank->method != METHOD_MPUIO))
1547 rev = __raw_readw(bank->base + OMAP1610_GPIO_REVISION);
1548 else if (cpu_is_omap24xx() || cpu_is_omap34xx())
1549 rev = __raw_readl(bank->base + OMAP24XX_GPIO_REVISION);
1550 else if (cpu_is_omap44xx())
1551 rev = __raw_readl(bank->base + OMAP4_GPIO_REVISION);
1555 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1556 (rev >> 4) & 0x0f, rev & 0x0f);
1559 /* This lock class tells lockdep that GPIO irqs are in a different
1560 * category than their parents, so it won't report false recursion.
1562 static struct lock_class_key gpio_lock_class;
1564 static inline int init_gpio_info(struct platform_device *pdev)
1566 /* TODO: Analyze removing gpio_bank_count usage from driver code */
1567 gpio_bank = kzalloc(gpio_bank_count * sizeof(struct gpio_bank),
1570 dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n");
1576 /* TODO: Cleanup cpu_is_* checks */
1577 static void omap_gpio_mod_init(struct gpio_bank *bank, int id)
1579 if (cpu_class_is_omap2()) {
1580 if (cpu_is_omap44xx()) {
1581 __raw_writel(0xffffffff, bank->base +
1582 OMAP4_GPIO_IRQSTATUSCLR0);
1583 __raw_writel(0x00000000, bank->base +
1584 OMAP4_GPIO_DEBOUNCENABLE);
1585 /* Initialize interface clk ungated, module enabled */
1586 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
1587 } else if (cpu_is_omap34xx()) {
1588 __raw_writel(0x00000000, bank->base +
1589 OMAP24XX_GPIO_IRQENABLE1);
1590 __raw_writel(0xffffffff, bank->base +
1591 OMAP24XX_GPIO_IRQSTATUS1);
1592 __raw_writel(0x00000000, bank->base +
1593 OMAP24XX_GPIO_DEBOUNCE_EN);
1595 /* Initialize interface clk ungated, module enabled */
1596 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1597 } else if (cpu_is_omap24xx()) {
1598 static const u32 non_wakeup_gpios[] = {
1599 0xe203ffc0, 0x08700040
1601 if (id < ARRAY_SIZE(non_wakeup_gpios))
1602 bank->non_wakeup_gpios = non_wakeup_gpios[id];
1604 } else if (cpu_class_is_omap1()) {
1605 if (bank_is_mpuio(bank))
1606 __raw_writew(0xffff, bank->base +
1607 OMAP_MPUIO_GPIO_MASKIT / bank->stride);
1608 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1609 __raw_writew(0xffff, bank->base
1610 + OMAP1510_GPIO_INT_MASK);
1611 __raw_writew(0x0000, bank->base
1612 + OMAP1510_GPIO_INT_STATUS);
1614 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1615 __raw_writew(0x0000, bank->base
1616 + OMAP1610_GPIO_IRQENABLE1);
1617 __raw_writew(0xffff, bank->base
1618 + OMAP1610_GPIO_IRQSTATUS1);
1619 __raw_writew(0x0014, bank->base
1620 + OMAP1610_GPIO_SYSCONFIG);
1623 * Enable system clock for GPIO module.
1624 * The CAM_CLK_CTRL *is* really the right place.
1626 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
1629 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
1630 __raw_writel(0xffffffff, bank->base
1631 + OMAP7XX_GPIO_INT_MASK);
1632 __raw_writel(0x00000000, bank->base
1633 + OMAP7XX_GPIO_INT_STATUS);
1638 static void __init omap_gpio_chip_init(struct gpio_bank *bank)
1643 bank->mod_usage = 0;
1645 * REVISIT eventually switch from OMAP-specific gpio structs
1646 * over to the generic ones
1648 bank->chip.request = omap_gpio_request;
1649 bank->chip.free = omap_gpio_free;
1650 bank->chip.direction_input = gpio_input;
1651 bank->chip.get = gpio_get;
1652 bank->chip.direction_output = gpio_output;
1653 bank->chip.set_debounce = gpio_debounce;
1654 bank->chip.set = gpio_set;
1655 bank->chip.to_irq = gpio_2irq;
1656 if (bank_is_mpuio(bank)) {
1657 bank->chip.label = "mpuio";
1658 #ifdef CONFIG_ARCH_OMAP16XX
1659 bank->chip.dev = &omap_mpuio_device.dev;
1661 bank->chip.base = OMAP_MPUIO(0);
1663 bank->chip.label = "gpio";
1664 bank->chip.base = gpio;
1667 bank->chip.ngpio = bank_width;
1669 gpiochip_add(&bank->chip);
1671 for (j = bank->virtual_irq_start;
1672 j < bank->virtual_irq_start + bank_width; j++) {
1673 lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
1674 set_irq_chip_data(j, bank);
1675 if (bank_is_mpuio(bank))
1676 set_irq_chip(j, &mpuio_irq_chip);
1678 set_irq_chip(j, &gpio_irq_chip);
1679 set_irq_handler(j, handle_simple_irq);
1680 set_irq_flags(j, IRQF_VALID);
1682 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1683 set_irq_data(bank->irq, bank);
1686 static int __devinit omap_gpio_probe(struct platform_device *pdev)
1688 static int gpio_init_done;
1689 struct omap_gpio_platform_data *pdata;
1690 struct resource *res;
1692 struct gpio_bank *bank;
1694 if (!pdev->dev.platform_data)
1697 pdata = pdev->dev.platform_data;
1699 if (!gpio_init_done) {
1702 ret = init_gpio_info(pdev);
1708 bank = &gpio_bank[id];
1710 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1711 if (unlikely(!res)) {
1712 dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n", id);
1716 bank->irq = res->start;
1717 bank->virtual_irq_start = pdata->virtual_irq_start;
1718 bank->method = pdata->bank_type;
1719 bank->dev = &pdev->dev;
1720 bank->dbck_flag = pdata->dbck_flag;
1721 bank->stride = pdata->bank_stride;
1722 bank_width = pdata->bank_width;
1724 spin_lock_init(&bank->lock);
1726 /* Static mapping, never released */
1727 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1728 if (unlikely(!res)) {
1729 dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n", id);
1733 bank->base = ioremap(res->start, resource_size(res));
1735 dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n", id);
1739 pm_runtime_enable(bank->dev);
1740 pm_runtime_get_sync(bank->dev);
1742 omap_gpio_mod_init(bank, id);
1743 omap_gpio_chip_init(bank);
1744 omap_gpio_show_rev(bank);
1746 if (!gpio_init_done)
1752 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
1753 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1757 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1760 for (i = 0; i < gpio_bank_count; i++) {
1761 struct gpio_bank *bank = &gpio_bank[i];
1762 void __iomem *wake_status;
1763 void __iomem *wake_clear;
1764 void __iomem *wake_set;
1765 unsigned long flags;
1767 switch (bank->method) {
1768 #ifdef CONFIG_ARCH_OMAP16XX
1769 case METHOD_GPIO_1610:
1770 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1771 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1772 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1775 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1776 case METHOD_GPIO_24XX:
1777 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
1778 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1779 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1782 #ifdef CONFIG_ARCH_OMAP4
1783 case METHOD_GPIO_44XX:
1784 wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
1785 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1786 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1793 spin_lock_irqsave(&bank->lock, flags);
1794 bank->saved_wakeup = __raw_readl(wake_status);
1795 __raw_writel(0xffffffff, wake_clear);
1796 __raw_writel(bank->suspend_wakeup, wake_set);
1797 spin_unlock_irqrestore(&bank->lock, flags);
1803 static int omap_gpio_resume(struct sys_device *dev)
1807 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1810 for (i = 0; i < gpio_bank_count; i++) {
1811 struct gpio_bank *bank = &gpio_bank[i];
1812 void __iomem *wake_clear;
1813 void __iomem *wake_set;
1814 unsigned long flags;
1816 switch (bank->method) {
1817 #ifdef CONFIG_ARCH_OMAP16XX
1818 case METHOD_GPIO_1610:
1819 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1820 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1823 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1824 case METHOD_GPIO_24XX:
1825 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1826 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1829 #ifdef CONFIG_ARCH_OMAP4
1830 case METHOD_GPIO_44XX:
1831 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1832 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1839 spin_lock_irqsave(&bank->lock, flags);
1840 __raw_writel(0xffffffff, wake_clear);
1841 __raw_writel(bank->saved_wakeup, wake_set);
1842 spin_unlock_irqrestore(&bank->lock, flags);
1848 static struct sysdev_class omap_gpio_sysclass = {
1850 .suspend = omap_gpio_suspend,
1851 .resume = omap_gpio_resume,
1854 static struct sys_device omap_gpio_device = {
1856 .cls = &omap_gpio_sysclass,
1861 #ifdef CONFIG_ARCH_OMAP2PLUS
1863 static int workaround_enabled;
1865 void omap2_gpio_prepare_for_idle(int off_mode)
1870 if (cpu_is_omap34xx())
1873 for (i = min; i < gpio_bank_count; i++) {
1874 struct gpio_bank *bank = &gpio_bank[i];
1878 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
1879 clk_disable(bank->dbck);
1884 /* If going to OFF, remove triggering for all
1885 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1886 * generated. See OMAP2420 Errata item 1.101. */
1887 if (!(bank->enabled_non_wakeup_gpios))
1890 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1891 bank->saved_datain = __raw_readl(bank->base +
1892 OMAP24XX_GPIO_DATAIN);
1893 l1 = __raw_readl(bank->base +
1894 OMAP24XX_GPIO_FALLINGDETECT);
1895 l2 = __raw_readl(bank->base +
1896 OMAP24XX_GPIO_RISINGDETECT);
1899 if (cpu_is_omap44xx()) {
1900 bank->saved_datain = __raw_readl(bank->base +
1902 l1 = __raw_readl(bank->base +
1903 OMAP4_GPIO_FALLINGDETECT);
1904 l2 = __raw_readl(bank->base +
1905 OMAP4_GPIO_RISINGDETECT);
1908 bank->saved_fallingdetect = l1;
1909 bank->saved_risingdetect = l2;
1910 l1 &= ~bank->enabled_non_wakeup_gpios;
1911 l2 &= ~bank->enabled_non_wakeup_gpios;
1913 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1914 __raw_writel(l1, bank->base +
1915 OMAP24XX_GPIO_FALLINGDETECT);
1916 __raw_writel(l2, bank->base +
1917 OMAP24XX_GPIO_RISINGDETECT);
1920 if (cpu_is_omap44xx()) {
1921 __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
1922 __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
1928 workaround_enabled = 0;
1931 workaround_enabled = 1;
1934 void omap2_gpio_resume_after_idle(void)
1939 if (cpu_is_omap34xx())
1941 for (i = min; i < gpio_bank_count; i++) {
1942 struct gpio_bank *bank = &gpio_bank[i];
1943 u32 l = 0, gen, gen0, gen1;
1946 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
1947 clk_enable(bank->dbck);
1949 if (!workaround_enabled)
1952 if (!(bank->enabled_non_wakeup_gpios))
1955 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1956 __raw_writel(bank->saved_fallingdetect,
1957 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1958 __raw_writel(bank->saved_risingdetect,
1959 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1960 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1963 if (cpu_is_omap44xx()) {
1964 __raw_writel(bank->saved_fallingdetect,
1965 bank->base + OMAP4_GPIO_FALLINGDETECT);
1966 __raw_writel(bank->saved_risingdetect,
1967 bank->base + OMAP4_GPIO_RISINGDETECT);
1968 l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
1971 /* Check if any of the non-wakeup interrupt GPIOs have changed
1972 * state. If so, generate an IRQ by software. This is
1973 * horribly racy, but it's the best we can do to work around
1974 * this silicon bug. */
1975 l ^= bank->saved_datain;
1976 l &= bank->enabled_non_wakeup_gpios;
1979 * No need to generate IRQs for the rising edge for gpio IRQs
1980 * configured with falling edge only; and vice versa.
1982 gen0 = l & bank->saved_fallingdetect;
1983 gen0 &= bank->saved_datain;
1985 gen1 = l & bank->saved_risingdetect;
1986 gen1 &= ~(bank->saved_datain);
1988 /* FIXME: Consider GPIO IRQs with level detections properly! */
1989 gen = l & (~(bank->saved_fallingdetect) &
1990 ~(bank->saved_risingdetect));
1991 /* Consider all GPIO IRQs needed to be updated */
1997 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1998 old0 = __raw_readl(bank->base +
1999 OMAP24XX_GPIO_LEVELDETECT0);
2000 old1 = __raw_readl(bank->base +
2001 OMAP24XX_GPIO_LEVELDETECT1);
2002 __raw_writel(old0 | gen, bank->base +
2003 OMAP24XX_GPIO_LEVELDETECT0);
2004 __raw_writel(old1 | gen, bank->base +
2005 OMAP24XX_GPIO_LEVELDETECT1);
2006 __raw_writel(old0, bank->base +
2007 OMAP24XX_GPIO_LEVELDETECT0);
2008 __raw_writel(old1, bank->base +
2009 OMAP24XX_GPIO_LEVELDETECT1);
2012 if (cpu_is_omap44xx()) {
2013 old0 = __raw_readl(bank->base +
2014 OMAP4_GPIO_LEVELDETECT0);
2015 old1 = __raw_readl(bank->base +
2016 OMAP4_GPIO_LEVELDETECT1);
2017 __raw_writel(old0 | l, bank->base +
2018 OMAP4_GPIO_LEVELDETECT0);
2019 __raw_writel(old1 | l, bank->base +
2020 OMAP4_GPIO_LEVELDETECT1);
2021 __raw_writel(old0, bank->base +
2022 OMAP4_GPIO_LEVELDETECT0);
2023 __raw_writel(old1, bank->base +
2024 OMAP4_GPIO_LEVELDETECT1);
2033 #ifdef CONFIG_ARCH_OMAP3
2034 /* save the registers of bank 2-6 */
2035 void omap_gpio_save_context(void)
2039 /* saving banks from 2-6 only since GPIO1 is in WKUP */
2040 for (i = 1; i < gpio_bank_count; i++) {
2041 struct gpio_bank *bank = &gpio_bank[i];
2042 gpio_context[i].irqenable1 =
2043 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
2044 gpio_context[i].irqenable2 =
2045 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
2046 gpio_context[i].wake_en =
2047 __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
2048 gpio_context[i].ctrl =
2049 __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
2050 gpio_context[i].oe =
2051 __raw_readl(bank->base + OMAP24XX_GPIO_OE);
2052 gpio_context[i].leveldetect0 =
2053 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2054 gpio_context[i].leveldetect1 =
2055 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2056 gpio_context[i].risingdetect =
2057 __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
2058 gpio_context[i].fallingdetect =
2059 __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2060 gpio_context[i].dataout =
2061 __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
2065 /* restore the required registers of bank 2-6 */
2066 void omap_gpio_restore_context(void)
2070 for (i = 1; i < gpio_bank_count; i++) {
2071 struct gpio_bank *bank = &gpio_bank[i];
2072 __raw_writel(gpio_context[i].irqenable1,
2073 bank->base + OMAP24XX_GPIO_IRQENABLE1);
2074 __raw_writel(gpio_context[i].irqenable2,
2075 bank->base + OMAP24XX_GPIO_IRQENABLE2);
2076 __raw_writel(gpio_context[i].wake_en,
2077 bank->base + OMAP24XX_GPIO_WAKE_EN);
2078 __raw_writel(gpio_context[i].ctrl,
2079 bank->base + OMAP24XX_GPIO_CTRL);
2080 __raw_writel(gpio_context[i].oe,
2081 bank->base + OMAP24XX_GPIO_OE);
2082 __raw_writel(gpio_context[i].leveldetect0,
2083 bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2084 __raw_writel(gpio_context[i].leveldetect1,
2085 bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2086 __raw_writel(gpio_context[i].risingdetect,
2087 bank->base + OMAP24XX_GPIO_RISINGDETECT);
2088 __raw_writel(gpio_context[i].fallingdetect,
2089 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2090 __raw_writel(gpio_context[i].dataout,
2091 bank->base + OMAP24XX_GPIO_DATAOUT);
2096 static struct platform_driver omap_gpio_driver = {
2097 .probe = omap_gpio_probe,
2099 .name = "omap_gpio",
2104 * gpio driver register needs to be done before
2105 * machine_init functions access gpio APIs.
2106 * Hence omap_gpio_drv_reg() is a postcore_initcall.
2108 static int __init omap_gpio_drv_reg(void)
2110 return platform_driver_register(&omap_gpio_driver);
2112 postcore_initcall(omap_gpio_drv_reg);
2114 static int __init omap_gpio_sysinit(void)
2120 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
2121 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
2123 ret = sysdev_class_register(&omap_gpio_sysclass);
2125 ret = sysdev_register(&omap_gpio_device);
2133 arch_initcall(omap_gpio_sysinit);