2 * linux/arch/arm/plat-omap/gpio.c
4 * Support functions for OMAP GPIO
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
9 * Copyright (C) 2009 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/interrupt.h>
20 #include <linux/sysdev.h>
21 #include <linux/err.h>
22 #include <linux/clk.h>
25 #include <mach/hardware.h>
27 #include <mach/irqs.h>
28 #include <mach/gpio.h>
29 #include <asm/mach/irq.h>
32 * OMAP1510 GPIO registers
34 #define OMAP1510_GPIO_BASE IO_ADDRESS(0xfffce000)
35 #define OMAP1510_GPIO_DATA_INPUT 0x00
36 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
37 #define OMAP1510_GPIO_DIR_CONTROL 0x08
38 #define OMAP1510_GPIO_INT_CONTROL 0x0c
39 #define OMAP1510_GPIO_INT_MASK 0x10
40 #define OMAP1510_GPIO_INT_STATUS 0x14
41 #define OMAP1510_GPIO_PIN_CONTROL 0x18
43 #define OMAP1510_IH_GPIO_BASE 64
46 * OMAP1610 specific GPIO registers
48 #define OMAP1610_GPIO1_BASE IO_ADDRESS(0xfffbe400)
49 #define OMAP1610_GPIO2_BASE IO_ADDRESS(0xfffbec00)
50 #define OMAP1610_GPIO3_BASE IO_ADDRESS(0xfffbb400)
51 #define OMAP1610_GPIO4_BASE IO_ADDRESS(0xfffbbc00)
52 #define OMAP1610_GPIO_REVISION 0x0000
53 #define OMAP1610_GPIO_SYSCONFIG 0x0010
54 #define OMAP1610_GPIO_SYSSTATUS 0x0014
55 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
56 #define OMAP1610_GPIO_IRQENABLE1 0x001c
57 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
58 #define OMAP1610_GPIO_DATAIN 0x002c
59 #define OMAP1610_GPIO_DATAOUT 0x0030
60 #define OMAP1610_GPIO_DIRECTION 0x0034
61 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
62 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
63 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
64 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
65 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
66 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
67 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
68 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
71 * OMAP730 specific GPIO registers
73 #define OMAP730_GPIO1_BASE IO_ADDRESS(0xfffbc000)
74 #define OMAP730_GPIO2_BASE IO_ADDRESS(0xfffbc800)
75 #define OMAP730_GPIO3_BASE IO_ADDRESS(0xfffbd000)
76 #define OMAP730_GPIO4_BASE IO_ADDRESS(0xfffbd800)
77 #define OMAP730_GPIO5_BASE IO_ADDRESS(0xfffbe000)
78 #define OMAP730_GPIO6_BASE IO_ADDRESS(0xfffbe800)
79 #define OMAP730_GPIO_DATA_INPUT 0x00
80 #define OMAP730_GPIO_DATA_OUTPUT 0x04
81 #define OMAP730_GPIO_DIR_CONTROL 0x08
82 #define OMAP730_GPIO_INT_CONTROL 0x0c
83 #define OMAP730_GPIO_INT_MASK 0x10
84 #define OMAP730_GPIO_INT_STATUS 0x14
87 * OMAP850 specific GPIO registers
89 #define OMAP850_GPIO1_BASE IO_ADDRESS(0xfffbc000)
90 #define OMAP850_GPIO2_BASE IO_ADDRESS(0xfffbc800)
91 #define OMAP850_GPIO3_BASE IO_ADDRESS(0xfffbd000)
92 #define OMAP850_GPIO4_BASE IO_ADDRESS(0xfffbd800)
93 #define OMAP850_GPIO5_BASE IO_ADDRESS(0xfffbe000)
94 #define OMAP850_GPIO6_BASE IO_ADDRESS(0xfffbe800)
95 #define OMAP850_GPIO_DATA_INPUT 0x00
96 #define OMAP850_GPIO_DATA_OUTPUT 0x04
97 #define OMAP850_GPIO_DIR_CONTROL 0x08
98 #define OMAP850_GPIO_INT_CONTROL 0x0c
99 #define OMAP850_GPIO_INT_MASK 0x10
100 #define OMAP850_GPIO_INT_STATUS 0x14
103 * omap24xx specific GPIO registers
105 #define OMAP242X_GPIO1_BASE IO_ADDRESS(0x48018000)
106 #define OMAP242X_GPIO2_BASE IO_ADDRESS(0x4801a000)
107 #define OMAP242X_GPIO3_BASE IO_ADDRESS(0x4801c000)
108 #define OMAP242X_GPIO4_BASE IO_ADDRESS(0x4801e000)
110 #define OMAP243X_GPIO1_BASE IO_ADDRESS(0x4900C000)
111 #define OMAP243X_GPIO2_BASE IO_ADDRESS(0x4900E000)
112 #define OMAP243X_GPIO3_BASE IO_ADDRESS(0x49010000)
113 #define OMAP243X_GPIO4_BASE IO_ADDRESS(0x49012000)
114 #define OMAP243X_GPIO5_BASE IO_ADDRESS(0x480B6000)
116 #define OMAP24XX_GPIO_REVISION 0x0000
117 #define OMAP24XX_GPIO_SYSCONFIG 0x0010
118 #define OMAP24XX_GPIO_SYSSTATUS 0x0014
119 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
120 #define OMAP24XX_GPIO_IRQSTATUS2 0x0028
121 #define OMAP24XX_GPIO_IRQENABLE2 0x002c
122 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
123 #define OMAP24XX_GPIO_WAKE_EN 0x0020
124 #define OMAP24XX_GPIO_CTRL 0x0030
125 #define OMAP24XX_GPIO_OE 0x0034
126 #define OMAP24XX_GPIO_DATAIN 0x0038
127 #define OMAP24XX_GPIO_DATAOUT 0x003c
128 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
129 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
130 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
131 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
132 #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
133 #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
134 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
135 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
136 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
137 #define OMAP24XX_GPIO_SETWKUENA 0x0084
138 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
139 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
141 #define OMAP4_GPIO_REVISION 0x0000
142 #define OMAP4_GPIO_SYSCONFIG 0x0010
143 #define OMAP4_GPIO_EOI 0x0020
144 #define OMAP4_GPIO_IRQSTATUSRAW0 0x0024
145 #define OMAP4_GPIO_IRQSTATUSRAW1 0x0028
146 #define OMAP4_GPIO_IRQSTATUS0 0x002c
147 #define OMAP4_GPIO_IRQSTATUS1 0x0030
148 #define OMAP4_GPIO_IRQSTATUSSET0 0x0034
149 #define OMAP4_GPIO_IRQSTATUSSET1 0x0038
150 #define OMAP4_GPIO_IRQSTATUSCLR0 0x003c
151 #define OMAP4_GPIO_IRQSTATUSCLR1 0x0040
152 #define OMAP4_GPIO_IRQWAKEN0 0x0044
153 #define OMAP4_GPIO_IRQWAKEN1 0x0048
154 #define OMAP4_GPIO_SYSSTATUS 0x0104
155 #define OMAP4_GPIO_CTRL 0x0130
156 #define OMAP4_GPIO_OE 0x0134
157 #define OMAP4_GPIO_DATAIN 0x0138
158 #define OMAP4_GPIO_DATAOUT 0x013c
159 #define OMAP4_GPIO_LEVELDETECT0 0x0140
160 #define OMAP4_GPIO_LEVELDETECT1 0x0144
161 #define OMAP4_GPIO_RISINGDETECT 0x0148
162 #define OMAP4_GPIO_FALLINGDETECT 0x014c
163 #define OMAP4_GPIO_DEBOUNCENABLE 0x0150
164 #define OMAP4_GPIO_DEBOUNCINGTIME 0x0154
165 #define OMAP4_GPIO_CLEARDATAOUT 0x0190
166 #define OMAP4_GPIO_SETDATAOUT 0x0194
168 * omap34xx specific GPIO registers
171 #define OMAP34XX_GPIO1_BASE IO_ADDRESS(0x48310000)
172 #define OMAP34XX_GPIO2_BASE IO_ADDRESS(0x49050000)
173 #define OMAP34XX_GPIO3_BASE IO_ADDRESS(0x49052000)
174 #define OMAP34XX_GPIO4_BASE IO_ADDRESS(0x49054000)
175 #define OMAP34XX_GPIO5_BASE IO_ADDRESS(0x49056000)
176 #define OMAP34XX_GPIO6_BASE IO_ADDRESS(0x49058000)
179 * OMAP44XX specific GPIO registers
181 #define OMAP44XX_GPIO1_BASE IO_ADDRESS(0x4a310000)
182 #define OMAP44XX_GPIO2_BASE IO_ADDRESS(0x48055000)
183 #define OMAP44XX_GPIO3_BASE IO_ADDRESS(0x48057000)
184 #define OMAP44XX_GPIO4_BASE IO_ADDRESS(0x48059000)
185 #define OMAP44XX_GPIO5_BASE IO_ADDRESS(0x4805B000)
186 #define OMAP44XX_GPIO6_BASE IO_ADDRESS(0x4805D000)
188 #define OMAP_MPUIO_VBASE IO_ADDRESS(OMAP_MPUIO_BASE)
193 u16 virtual_irq_start;
195 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
196 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
200 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
201 defined(CONFIG_ARCH_OMAP4)
202 u32 non_wakeup_gpios;
203 u32 enabled_non_wakeup_gpios;
206 u32 saved_fallingdetect;
207 u32 saved_risingdetect;
211 struct gpio_chip chip;
215 #define METHOD_MPUIO 0
216 #define METHOD_GPIO_1510 1
217 #define METHOD_GPIO_1610 2
218 #define METHOD_GPIO_730 3
219 #define METHOD_GPIO_850 4
220 #define METHOD_GPIO_24XX 5
222 #ifdef CONFIG_ARCH_OMAP16XX
223 static struct gpio_bank gpio_bank_1610[5] = {
224 { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
225 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
226 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
227 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
228 { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
232 #ifdef CONFIG_ARCH_OMAP15XX
233 static struct gpio_bank gpio_bank_1510[2] = {
234 { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
235 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
239 #ifdef CONFIG_ARCH_OMAP730
240 static struct gpio_bank gpio_bank_730[7] = {
241 { OMAP_MPUIO_VBASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
242 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
243 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
244 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
245 { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 },
246 { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 },
247 { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 },
251 #ifdef CONFIG_ARCH_OMAP850
252 static struct gpio_bank gpio_bank_850[7] = {
253 { OMAP_MPUIO_BASE, INT_850_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
254 { OMAP850_GPIO1_BASE, INT_850_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_850 },
255 { OMAP850_GPIO2_BASE, INT_850_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_850 },
256 { OMAP850_GPIO3_BASE, INT_850_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_850 },
257 { OMAP850_GPIO4_BASE, INT_850_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_850 },
258 { OMAP850_GPIO5_BASE, INT_850_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_850 },
259 { OMAP850_GPIO6_BASE, INT_850_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_850 },
264 #ifdef CONFIG_ARCH_OMAP24XX
266 static struct gpio_bank gpio_bank_242x[4] = {
267 { OMAP242X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
268 { OMAP242X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
269 { OMAP242X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
270 { OMAP242X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
273 static struct gpio_bank gpio_bank_243x[5] = {
274 { OMAP243X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
275 { OMAP243X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
276 { OMAP243X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
277 { OMAP243X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
278 { OMAP243X_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
283 #ifdef CONFIG_ARCH_OMAP34XX
284 static struct gpio_bank gpio_bank_34xx[6] = {
285 { OMAP34XX_GPIO1_BASE, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
286 { OMAP34XX_GPIO2_BASE, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
287 { OMAP34XX_GPIO3_BASE, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
288 { OMAP34XX_GPIO4_BASE, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
289 { OMAP34XX_GPIO5_BASE, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
290 { OMAP34XX_GPIO6_BASE, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_24XX },
295 #ifdef CONFIG_ARCH_OMAP4
296 static struct gpio_bank gpio_bank_44xx[6] = {
297 { OMAP44XX_GPIO1_BASE, INT_44XX_GPIO_BANK1, IH_GPIO_BASE, \
299 { OMAP44XX_GPIO2_BASE, INT_44XX_GPIO_BANK2, IH_GPIO_BASE + 32, \
301 { OMAP44XX_GPIO3_BASE, INT_44XX_GPIO_BANK3, IH_GPIO_BASE + 64, \
303 { OMAP44XX_GPIO4_BASE, INT_44XX_GPIO_BANK4, IH_GPIO_BASE + 96, \
305 { OMAP44XX_GPIO5_BASE, INT_44XX_GPIO_BANK5, IH_GPIO_BASE + 128, \
307 { OMAP44XX_GPIO6_BASE, INT_44XX_GPIO_BANK6, IH_GPIO_BASE + 160, \
313 static struct gpio_bank *gpio_bank;
314 static int gpio_bank_count;
316 static inline struct gpio_bank *get_gpio_bank(int gpio)
318 if (cpu_is_omap15xx()) {
319 if (OMAP_GPIO_IS_MPUIO(gpio))
320 return &gpio_bank[0];
321 return &gpio_bank[1];
323 if (cpu_is_omap16xx()) {
324 if (OMAP_GPIO_IS_MPUIO(gpio))
325 return &gpio_bank[0];
326 return &gpio_bank[1 + (gpio >> 4)];
328 if (cpu_is_omap7xx()) {
329 if (OMAP_GPIO_IS_MPUIO(gpio))
330 return &gpio_bank[0];
331 return &gpio_bank[1 + (gpio >> 5)];
333 if (cpu_is_omap24xx())
334 return &gpio_bank[gpio >> 5];
335 if (cpu_is_omap34xx() || cpu_is_omap44xx())
336 return &gpio_bank[gpio >> 5];
341 static inline int get_gpio_index(int gpio)
343 if (cpu_is_omap7xx())
345 if (cpu_is_omap24xx())
347 if (cpu_is_omap34xx() || cpu_is_omap44xx())
352 static inline int gpio_valid(int gpio)
356 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
357 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
361 if (cpu_is_omap15xx() && gpio < 16)
363 if ((cpu_is_omap16xx()) && gpio < 64)
365 if (cpu_is_omap7xx() && gpio < 192)
367 if (cpu_is_omap24xx() && gpio < 128)
369 if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192)
374 static int check_gpio(int gpio)
376 if (unlikely(gpio_valid(gpio)) < 0) {
377 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
384 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
386 void __iomem *reg = bank->base;
389 switch (bank->method) {
390 #ifdef CONFIG_ARCH_OMAP1
392 reg += OMAP_MPUIO_IO_CNTL;
395 #ifdef CONFIG_ARCH_OMAP15XX
396 case METHOD_GPIO_1510:
397 reg += OMAP1510_GPIO_DIR_CONTROL;
400 #ifdef CONFIG_ARCH_OMAP16XX
401 case METHOD_GPIO_1610:
402 reg += OMAP1610_GPIO_DIRECTION;
405 #ifdef CONFIG_ARCH_OMAP730
406 case METHOD_GPIO_730:
407 reg += OMAP730_GPIO_DIR_CONTROL;
410 #ifdef CONFIG_ARCH_OMAP850
411 case METHOD_GPIO_850:
412 reg += OMAP850_GPIO_DIR_CONTROL;
415 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
416 case METHOD_GPIO_24XX:
417 reg += OMAP24XX_GPIO_OE;
420 #if defined(CONFIG_ARCH_OMAP4)
421 case METHOD_GPIO_24XX:
422 reg += OMAP4_GPIO_OE;
429 l = __raw_readl(reg);
434 __raw_writel(l, reg);
437 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
439 void __iomem *reg = bank->base;
442 switch (bank->method) {
443 #ifdef CONFIG_ARCH_OMAP1
445 reg += OMAP_MPUIO_OUTPUT;
446 l = __raw_readl(reg);
453 #ifdef CONFIG_ARCH_OMAP15XX
454 case METHOD_GPIO_1510:
455 reg += OMAP1510_GPIO_DATA_OUTPUT;
456 l = __raw_readl(reg);
463 #ifdef CONFIG_ARCH_OMAP16XX
464 case METHOD_GPIO_1610:
466 reg += OMAP1610_GPIO_SET_DATAOUT;
468 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
472 #ifdef CONFIG_ARCH_OMAP730
473 case METHOD_GPIO_730:
474 reg += OMAP730_GPIO_DATA_OUTPUT;
475 l = __raw_readl(reg);
482 #ifdef CONFIG_ARCH_OMAP850
483 case METHOD_GPIO_850:
484 reg += OMAP850_GPIO_DATA_OUTPUT;
485 l = __raw_readl(reg);
492 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
493 case METHOD_GPIO_24XX:
495 reg += OMAP24XX_GPIO_SETDATAOUT;
497 reg += OMAP24XX_GPIO_CLEARDATAOUT;
501 #ifdef CONFIG_ARCH_OMAP4
502 case METHOD_GPIO_24XX:
504 reg += OMAP4_GPIO_SETDATAOUT;
506 reg += OMAP4_GPIO_CLEARDATAOUT;
514 __raw_writel(l, reg);
517 static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
521 if (check_gpio(gpio) < 0)
524 switch (bank->method) {
525 #ifdef CONFIG_ARCH_OMAP1
527 reg += OMAP_MPUIO_INPUT_LATCH;
530 #ifdef CONFIG_ARCH_OMAP15XX
531 case METHOD_GPIO_1510:
532 reg += OMAP1510_GPIO_DATA_INPUT;
535 #ifdef CONFIG_ARCH_OMAP16XX
536 case METHOD_GPIO_1610:
537 reg += OMAP1610_GPIO_DATAIN;
540 #ifdef CONFIG_ARCH_OMAP730
541 case METHOD_GPIO_730:
542 reg += OMAP730_GPIO_DATA_INPUT;
545 #ifdef CONFIG_ARCH_OMAP850
546 case METHOD_GPIO_850:
547 reg += OMAP850_GPIO_DATA_INPUT;
550 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
551 case METHOD_GPIO_24XX:
552 reg += OMAP24XX_GPIO_DATAIN;
555 #ifdef CONFIG_ARCH_OMAP4
556 case METHOD_GPIO_24XX:
557 reg += OMAP4_GPIO_DATAIN;
563 return (__raw_readl(reg)
564 & (1 << get_gpio_index(gpio))) != 0;
567 static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
571 if (check_gpio(gpio) < 0)
575 switch (bank->method) {
576 #ifdef CONFIG_ARCH_OMAP1
578 reg += OMAP_MPUIO_OUTPUT;
581 #ifdef CONFIG_ARCH_OMAP15XX
582 case METHOD_GPIO_1510:
583 reg += OMAP1510_GPIO_DATA_OUTPUT;
586 #ifdef CONFIG_ARCH_OMAP16XX
587 case METHOD_GPIO_1610:
588 reg += OMAP1610_GPIO_DATAOUT;
591 #ifdef CONFIG_ARCH_OMAP730
592 case METHOD_GPIO_730:
593 reg += OMAP730_GPIO_DATA_OUTPUT;
596 #ifdef CONFIG_ARCH_OMAP850
597 case METHOD_GPIO_850:
598 reg += OMAP850_GPIO_DATA_OUTPUT;
601 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
602 defined(CONFIG_ARCH_OMAP4)
603 case METHOD_GPIO_24XX:
604 reg += OMAP24XX_GPIO_DATAOUT;
611 return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0;
614 #define MOD_REG_BIT(reg, bit_mask, set) \
616 int l = __raw_readl(base + reg); \
617 if (set) l |= bit_mask; \
618 else l &= ~bit_mask; \
619 __raw_writel(l, base + reg); \
622 void omap_set_gpio_debounce(int gpio, int enable)
624 struct gpio_bank *bank;
627 u32 val, l = 1 << get_gpio_index(gpio);
629 if (cpu_class_is_omap1())
632 bank = get_gpio_bank(gpio);
634 #ifdef CONFIG_ARCH_OMAP4
635 reg += OMAP4_GPIO_DEBOUNCENABLE;
637 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
640 spin_lock_irqsave(&bank->lock, flags);
641 val = __raw_readl(reg);
643 if (enable && !(val & l))
645 else if (!enable && (val & l))
650 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
652 clk_enable(bank->dbck);
654 clk_disable(bank->dbck);
657 __raw_writel(val, reg);
659 spin_unlock_irqrestore(&bank->lock, flags);
661 EXPORT_SYMBOL(omap_set_gpio_debounce);
663 void omap_set_gpio_debounce_time(int gpio, int enc_time)
665 struct gpio_bank *bank;
668 if (cpu_class_is_omap1())
671 bank = get_gpio_bank(gpio);
675 #ifdef CONFIG_ARCH_OMAP4
676 reg += OMAP4_GPIO_DEBOUNCINGTIME;
678 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
680 __raw_writel(enc_time, reg);
682 EXPORT_SYMBOL(omap_set_gpio_debounce_time);
684 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
685 defined(CONFIG_ARCH_OMAP4)
686 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
689 void __iomem *base = bank->base;
690 u32 gpio_bit = 1 << gpio;
693 if (cpu_is_omap44xx()) {
694 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
695 trigger & IRQ_TYPE_LEVEL_LOW);
696 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
697 trigger & IRQ_TYPE_LEVEL_HIGH);
698 MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
699 trigger & IRQ_TYPE_EDGE_RISING);
700 MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
701 trigger & IRQ_TYPE_EDGE_FALLING);
703 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
704 trigger & IRQ_TYPE_LEVEL_LOW);
705 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
706 trigger & IRQ_TYPE_LEVEL_HIGH);
707 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
708 trigger & IRQ_TYPE_EDGE_RISING);
709 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
710 trigger & IRQ_TYPE_EDGE_FALLING);
712 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
713 if (cpu_is_omap44xx()) {
715 __raw_writel(1 << gpio, bank->base+
716 OMAP4_GPIO_IRQWAKEN0);
718 val = __raw_readl(bank->base +
719 OMAP4_GPIO_IRQWAKEN0);
720 __raw_writel(val & (~(1 << gpio)), bank->base +
721 OMAP4_GPIO_IRQWAKEN0);
725 __raw_writel(1 << gpio, bank->base
726 + OMAP24XX_GPIO_SETWKUENA);
728 __raw_writel(1 << gpio, bank->base
729 + OMAP24XX_GPIO_CLEARWKUENA);
733 bank->enabled_non_wakeup_gpios |= gpio_bit;
735 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
738 if (cpu_is_omap44xx()) {
740 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
741 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
744 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
745 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
750 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
752 void __iomem *reg = bank->base;
755 switch (bank->method) {
756 #ifdef CONFIG_ARCH_OMAP1
758 reg += OMAP_MPUIO_GPIO_INT_EDGE;
759 l = __raw_readl(reg);
760 if (trigger & IRQ_TYPE_EDGE_RISING)
762 else if (trigger & IRQ_TYPE_EDGE_FALLING)
768 #ifdef CONFIG_ARCH_OMAP15XX
769 case METHOD_GPIO_1510:
770 reg += OMAP1510_GPIO_INT_CONTROL;
771 l = __raw_readl(reg);
772 if (trigger & IRQ_TYPE_EDGE_RISING)
774 else if (trigger & IRQ_TYPE_EDGE_FALLING)
780 #ifdef CONFIG_ARCH_OMAP16XX
781 case METHOD_GPIO_1610:
783 reg += OMAP1610_GPIO_EDGE_CTRL2;
785 reg += OMAP1610_GPIO_EDGE_CTRL1;
787 l = __raw_readl(reg);
788 l &= ~(3 << (gpio << 1));
789 if (trigger & IRQ_TYPE_EDGE_RISING)
790 l |= 2 << (gpio << 1);
791 if (trigger & IRQ_TYPE_EDGE_FALLING)
792 l |= 1 << (gpio << 1);
794 /* Enable wake-up during idle for dynamic tick */
795 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
797 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
800 #ifdef CONFIG_ARCH_OMAP730
801 case METHOD_GPIO_730:
802 reg += OMAP730_GPIO_INT_CONTROL;
803 l = __raw_readl(reg);
804 if (trigger & IRQ_TYPE_EDGE_RISING)
806 else if (trigger & IRQ_TYPE_EDGE_FALLING)
812 #ifdef CONFIG_ARCH_OMAP850
813 case METHOD_GPIO_850:
814 reg += OMAP850_GPIO_INT_CONTROL;
815 l = __raw_readl(reg);
816 if (trigger & IRQ_TYPE_EDGE_RISING)
818 else if (trigger & IRQ_TYPE_EDGE_FALLING)
824 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
825 defined(CONFIG_ARCH_OMAP4)
826 case METHOD_GPIO_24XX:
827 set_24xx_gpio_triggering(bank, gpio, trigger);
833 __raw_writel(l, reg);
839 static int gpio_irq_type(unsigned irq, unsigned type)
841 struct gpio_bank *bank;
846 if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
847 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
849 gpio = irq - IH_GPIO_BASE;
851 if (check_gpio(gpio) < 0)
854 if (type & ~IRQ_TYPE_SENSE_MASK)
857 /* OMAP1 allows only only edge triggering */
858 if (!cpu_class_is_omap2()
859 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
862 bank = get_irq_chip_data(irq);
863 spin_lock_irqsave(&bank->lock, flags);
864 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
866 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
867 irq_desc[irq].status |= type;
869 spin_unlock_irqrestore(&bank->lock, flags);
871 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
872 __set_irq_handler_unlocked(irq, handle_level_irq);
873 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
874 __set_irq_handler_unlocked(irq, handle_edge_irq);
879 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
881 void __iomem *reg = bank->base;
883 switch (bank->method) {
884 #ifdef CONFIG_ARCH_OMAP1
886 /* MPUIO irqstatus is reset by reading the status register,
887 * so do nothing here */
890 #ifdef CONFIG_ARCH_OMAP15XX
891 case METHOD_GPIO_1510:
892 reg += OMAP1510_GPIO_INT_STATUS;
895 #ifdef CONFIG_ARCH_OMAP16XX
896 case METHOD_GPIO_1610:
897 reg += OMAP1610_GPIO_IRQSTATUS1;
900 #ifdef CONFIG_ARCH_OMAP730
901 case METHOD_GPIO_730:
902 reg += OMAP730_GPIO_INT_STATUS;
905 #ifdef CONFIG_ARCH_OMAP850
906 case METHOD_GPIO_850:
907 reg += OMAP850_GPIO_INT_STATUS;
910 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
911 case METHOD_GPIO_24XX:
912 reg += OMAP24XX_GPIO_IRQSTATUS1;
915 #if defined(CONFIG_ARCH_OMAP4)
916 case METHOD_GPIO_24XX:
917 reg += OMAP4_GPIO_IRQSTATUS0;
924 __raw_writel(gpio_mask, reg);
926 /* Workaround for clearing DSP GPIO interrupts to allow retention */
927 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
928 reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
930 #if defined(CONFIG_ARCH_OMAP4)
931 reg = bank->base + OMAP4_GPIO_IRQSTATUS1;
933 if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
934 __raw_writel(gpio_mask, reg);
936 /* Flush posted write for the irq status to avoid spurious interrupts */
941 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
943 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
946 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
948 void __iomem *reg = bank->base;
953 switch (bank->method) {
954 #ifdef CONFIG_ARCH_OMAP1
956 reg += OMAP_MPUIO_GPIO_MASKIT;
961 #ifdef CONFIG_ARCH_OMAP15XX
962 case METHOD_GPIO_1510:
963 reg += OMAP1510_GPIO_INT_MASK;
968 #ifdef CONFIG_ARCH_OMAP16XX
969 case METHOD_GPIO_1610:
970 reg += OMAP1610_GPIO_IRQENABLE1;
974 #ifdef CONFIG_ARCH_OMAP730
975 case METHOD_GPIO_730:
976 reg += OMAP730_GPIO_INT_MASK;
981 #ifdef CONFIG_ARCH_OMAP850
982 case METHOD_GPIO_850:
983 reg += OMAP850_GPIO_INT_MASK;
988 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
989 case METHOD_GPIO_24XX:
990 reg += OMAP24XX_GPIO_IRQENABLE1;
994 #if defined(CONFIG_ARCH_OMAP4)
995 case METHOD_GPIO_24XX:
996 reg += OMAP4_GPIO_IRQSTATUSSET0;
1005 l = __raw_readl(reg);
1012 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
1014 void __iomem *reg = bank->base;
1017 switch (bank->method) {
1018 #ifdef CONFIG_ARCH_OMAP1
1020 reg += OMAP_MPUIO_GPIO_MASKIT;
1021 l = __raw_readl(reg);
1028 #ifdef CONFIG_ARCH_OMAP15XX
1029 case METHOD_GPIO_1510:
1030 reg += OMAP1510_GPIO_INT_MASK;
1031 l = __raw_readl(reg);
1038 #ifdef CONFIG_ARCH_OMAP16XX
1039 case METHOD_GPIO_1610:
1041 reg += OMAP1610_GPIO_SET_IRQENABLE1;
1043 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
1047 #ifdef CONFIG_ARCH_OMAP730
1048 case METHOD_GPIO_730:
1049 reg += OMAP730_GPIO_INT_MASK;
1050 l = __raw_readl(reg);
1057 #ifdef CONFIG_ARCH_OMAP850
1058 case METHOD_GPIO_850:
1059 reg += OMAP850_GPIO_INT_MASK;
1060 l = __raw_readl(reg);
1067 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1068 case METHOD_GPIO_24XX:
1070 reg += OMAP24XX_GPIO_SETIRQENABLE1;
1072 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
1076 #ifdef CONFIG_ARCH_OMAP4
1077 case METHOD_GPIO_24XX:
1079 reg += OMAP4_GPIO_IRQSTATUSSET0;
1081 reg += OMAP4_GPIO_IRQSTATUSCLR0;
1089 __raw_writel(l, reg);
1092 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
1094 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
1098 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
1099 * 1510 does not seem to have a wake-up register. If JTAG is connected
1100 * to the target, system will wake up always on GPIO events. While
1101 * system is running all registered GPIO interrupts need to have wake-up
1102 * enabled. When system is suspended, only selected GPIO interrupts need
1103 * to have wake-up enabled.
1105 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
1107 unsigned long flags;
1109 switch (bank->method) {
1110 #ifdef CONFIG_ARCH_OMAP16XX
1112 case METHOD_GPIO_1610:
1113 spin_lock_irqsave(&bank->lock, flags);
1115 bank->suspend_wakeup |= (1 << gpio);
1117 bank->suspend_wakeup &= ~(1 << gpio);
1118 spin_unlock_irqrestore(&bank->lock, flags);
1121 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1122 defined(CONFIG_ARCH_OMAP4)
1123 case METHOD_GPIO_24XX:
1124 if (bank->non_wakeup_gpios & (1 << gpio)) {
1125 printk(KERN_ERR "Unable to modify wakeup on "
1126 "non-wakeup GPIO%d\n",
1127 (bank - gpio_bank) * 32 + gpio);
1130 spin_lock_irqsave(&bank->lock, flags);
1132 bank->suspend_wakeup |= (1 << gpio);
1134 bank->suspend_wakeup &= ~(1 << gpio);
1135 spin_unlock_irqrestore(&bank->lock, flags);
1139 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
1145 static void _reset_gpio(struct gpio_bank *bank, int gpio)
1147 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
1148 _set_gpio_irqenable(bank, gpio, 0);
1149 _clear_gpio_irqstatus(bank, gpio);
1150 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
1153 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
1154 static int gpio_wake_enable(unsigned int irq, unsigned int enable)
1156 unsigned int gpio = irq - IH_GPIO_BASE;
1157 struct gpio_bank *bank;
1160 if (check_gpio(gpio) < 0)
1162 bank = get_irq_chip_data(irq);
1163 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
1168 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
1170 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
1171 unsigned long flags;
1173 spin_lock_irqsave(&bank->lock, flags);
1175 /* Set trigger to none. You need to enable the desired trigger with
1176 * request_irq() or set_irq_type().
1178 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
1180 #ifdef CONFIG_ARCH_OMAP15XX
1181 if (bank->method == METHOD_GPIO_1510) {
1184 /* Claim the pin for MPU */
1185 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
1186 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
1189 spin_unlock_irqrestore(&bank->lock, flags);
1194 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
1196 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
1197 unsigned long flags;
1199 spin_lock_irqsave(&bank->lock, flags);
1200 #ifdef CONFIG_ARCH_OMAP16XX
1201 if (bank->method == METHOD_GPIO_1610) {
1202 /* Disable wake-up during idle for dynamic tick */
1203 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1204 __raw_writel(1 << offset, reg);
1207 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1208 defined(CONFIG_ARCH_OMAP4)
1209 if (bank->method == METHOD_GPIO_24XX) {
1210 /* Disable wake-up during idle for dynamic tick */
1211 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1212 __raw_writel(1 << offset, reg);
1215 _reset_gpio(bank, bank->chip.base + offset);
1216 spin_unlock_irqrestore(&bank->lock, flags);
1220 * We need to unmask the GPIO bank interrupt as soon as possible to
1221 * avoid missing GPIO interrupts for other lines in the bank.
1222 * Then we need to mask-read-clear-unmask the triggered GPIO lines
1223 * in the bank to avoid missing nested interrupts for a GPIO line.
1224 * If we wait to unmask individual GPIO lines in the bank after the
1225 * line's interrupt handler has been run, we may miss some nested
1228 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1230 void __iomem *isr_reg = NULL;
1232 unsigned int gpio_irq;
1233 struct gpio_bank *bank;
1237 desc->chip->ack(irq);
1239 bank = get_irq_data(irq);
1240 #ifdef CONFIG_ARCH_OMAP1
1241 if (bank->method == METHOD_MPUIO)
1242 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
1244 #ifdef CONFIG_ARCH_OMAP15XX
1245 if (bank->method == METHOD_GPIO_1510)
1246 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1248 #if defined(CONFIG_ARCH_OMAP16XX)
1249 if (bank->method == METHOD_GPIO_1610)
1250 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1252 #ifdef CONFIG_ARCH_OMAP730
1253 if (bank->method == METHOD_GPIO_730)
1254 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
1256 #ifdef CONFIG_ARCH_OMAP850
1257 if (bank->method == METHOD_GPIO_850)
1258 isr_reg = bank->base + OMAP850_GPIO_INT_STATUS;
1260 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1261 if (bank->method == METHOD_GPIO_24XX)
1262 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
1264 #if defined(CONFIG_ARCH_OMAP4)
1265 if (bank->method == METHOD_GPIO_24XX)
1266 isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0;
1269 u32 isr_saved, level_mask = 0;
1272 enabled = _get_gpio_irqbank_mask(bank);
1273 isr_saved = isr = __raw_readl(isr_reg) & enabled;
1275 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1278 if (cpu_class_is_omap2()) {
1279 level_mask = bank->level_mask & enabled;
1282 /* clear edge sensitive interrupts before handler(s) are
1283 called so that we don't miss any interrupt occurred while
1285 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1286 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1287 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1289 /* if there is only edge sensitive GPIO pin interrupts
1290 configured, we could unmask GPIO bank interrupt immediately */
1291 if (!level_mask && !unmasked) {
1293 desc->chip->unmask(irq);
1301 gpio_irq = bank->virtual_irq_start;
1302 for (; isr != 0; isr >>= 1, gpio_irq++) {
1306 generic_handle_irq(gpio_irq);
1309 /* if bank has any level sensitive GPIO pin interrupt
1310 configured, we must unmask the bank interrupt only after
1311 handler(s) are executed in order to avoid spurious bank
1314 desc->chip->unmask(irq);
1318 static void gpio_irq_shutdown(unsigned int irq)
1320 unsigned int gpio = irq - IH_GPIO_BASE;
1321 struct gpio_bank *bank = get_irq_chip_data(irq);
1323 _reset_gpio(bank, gpio);
1326 static void gpio_ack_irq(unsigned int irq)
1328 unsigned int gpio = irq - IH_GPIO_BASE;
1329 struct gpio_bank *bank = get_irq_chip_data(irq);
1331 _clear_gpio_irqstatus(bank, gpio);
1334 static void gpio_mask_irq(unsigned int irq)
1336 unsigned int gpio = irq - IH_GPIO_BASE;
1337 struct gpio_bank *bank = get_irq_chip_data(irq);
1339 _set_gpio_irqenable(bank, gpio, 0);
1340 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
1343 static void gpio_unmask_irq(unsigned int irq)
1345 unsigned int gpio = irq - IH_GPIO_BASE;
1346 struct gpio_bank *bank = get_irq_chip_data(irq);
1347 unsigned int irq_mask = 1 << get_gpio_index(gpio);
1348 struct irq_desc *desc = irq_to_desc(irq);
1349 u32 trigger = desc->status & IRQ_TYPE_SENSE_MASK;
1352 _set_gpio_triggering(bank, get_gpio_index(gpio), trigger);
1354 /* For level-triggered GPIOs, the clearing must be done after
1355 * the HW source is cleared, thus after the handler has run */
1356 if (bank->level_mask & irq_mask) {
1357 _set_gpio_irqenable(bank, gpio, 0);
1358 _clear_gpio_irqstatus(bank, gpio);
1361 _set_gpio_irqenable(bank, gpio, 1);
1364 static struct irq_chip gpio_irq_chip = {
1366 .shutdown = gpio_irq_shutdown,
1367 .ack = gpio_ack_irq,
1368 .mask = gpio_mask_irq,
1369 .unmask = gpio_unmask_irq,
1370 .set_type = gpio_irq_type,
1371 .set_wake = gpio_wake_enable,
1374 /*---------------------------------------------------------------------*/
1376 #ifdef CONFIG_ARCH_OMAP1
1378 /* MPUIO uses the always-on 32k clock */
1380 static void mpuio_ack_irq(unsigned int irq)
1382 /* The ISR is reset automatically, so do nothing here. */
1385 static void mpuio_mask_irq(unsigned int irq)
1387 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1388 struct gpio_bank *bank = get_irq_chip_data(irq);
1390 _set_gpio_irqenable(bank, gpio, 0);
1393 static void mpuio_unmask_irq(unsigned int irq)
1395 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1396 struct gpio_bank *bank = get_irq_chip_data(irq);
1398 _set_gpio_irqenable(bank, gpio, 1);
1401 static struct irq_chip mpuio_irq_chip = {
1403 .ack = mpuio_ack_irq,
1404 .mask = mpuio_mask_irq,
1405 .unmask = mpuio_unmask_irq,
1406 .set_type = gpio_irq_type,
1407 #ifdef CONFIG_ARCH_OMAP16XX
1408 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1409 .set_wake = gpio_wake_enable,
1414 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1417 #ifdef CONFIG_ARCH_OMAP16XX
1419 #include <linux/platform_device.h>
1421 static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t mesg)
1423 struct gpio_bank *bank = platform_get_drvdata(pdev);
1424 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1425 unsigned long flags;
1427 spin_lock_irqsave(&bank->lock, flags);
1428 bank->saved_wakeup = __raw_readl(mask_reg);
1429 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
1430 spin_unlock_irqrestore(&bank->lock, flags);
1435 static int omap_mpuio_resume_early(struct platform_device *pdev)
1437 struct gpio_bank *bank = platform_get_drvdata(pdev);
1438 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1439 unsigned long flags;
1441 spin_lock_irqsave(&bank->lock, flags);
1442 __raw_writel(bank->saved_wakeup, mask_reg);
1443 spin_unlock_irqrestore(&bank->lock, flags);
1448 /* use platform_driver for this, now that there's no longer any
1449 * point to sys_device (other than not disturbing old code).
1451 static struct platform_driver omap_mpuio_driver = {
1452 .suspend_late = omap_mpuio_suspend_late,
1453 .resume_early = omap_mpuio_resume_early,
1459 static struct platform_device omap_mpuio_device = {
1463 .driver = &omap_mpuio_driver.driver,
1465 /* could list the /proc/iomem resources */
1468 static inline void mpuio_init(void)
1470 platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]);
1472 if (platform_driver_register(&omap_mpuio_driver) == 0)
1473 (void) platform_device_register(&omap_mpuio_device);
1477 static inline void mpuio_init(void) {}
1482 extern struct irq_chip mpuio_irq_chip;
1484 #define bank_is_mpuio(bank) 0
1485 static inline void mpuio_init(void) {}
1489 /*---------------------------------------------------------------------*/
1491 /* REVISIT these are stupid implementations! replace by ones that
1492 * don't switch on METHOD_* and which mostly avoid spinlocks
1495 static int gpio_input(struct gpio_chip *chip, unsigned offset)
1497 struct gpio_bank *bank;
1498 unsigned long flags;
1500 bank = container_of(chip, struct gpio_bank, chip);
1501 spin_lock_irqsave(&bank->lock, flags);
1502 _set_gpio_direction(bank, offset, 1);
1503 spin_unlock_irqrestore(&bank->lock, flags);
1507 static int gpio_is_input(struct gpio_bank *bank, int mask)
1509 void __iomem *reg = bank->base;
1511 switch (bank->method) {
1513 reg += OMAP_MPUIO_IO_CNTL;
1515 case METHOD_GPIO_1510:
1516 reg += OMAP1510_GPIO_DIR_CONTROL;
1518 case METHOD_GPIO_1610:
1519 reg += OMAP1610_GPIO_DIRECTION;
1521 case METHOD_GPIO_730:
1522 reg += OMAP730_GPIO_DIR_CONTROL;
1524 case METHOD_GPIO_850:
1525 reg += OMAP850_GPIO_DIR_CONTROL;
1527 case METHOD_GPIO_24XX:
1528 reg += OMAP24XX_GPIO_OE;
1531 return __raw_readl(reg) & mask;
1534 static int gpio_get(struct gpio_chip *chip, unsigned offset)
1536 struct gpio_bank *bank;
1541 gpio = chip->base + offset;
1542 bank = get_gpio_bank(gpio);
1544 mask = 1 << get_gpio_index(gpio);
1546 if (gpio_is_input(bank, mask))
1547 return _get_gpio_datain(bank, gpio);
1549 return _get_gpio_dataout(bank, gpio);
1552 static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1554 struct gpio_bank *bank;
1555 unsigned long flags;
1557 bank = container_of(chip, struct gpio_bank, chip);
1558 spin_lock_irqsave(&bank->lock, flags);
1559 _set_gpio_dataout(bank, offset, value);
1560 _set_gpio_direction(bank, offset, 0);
1561 spin_unlock_irqrestore(&bank->lock, flags);
1565 static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1567 struct gpio_bank *bank;
1568 unsigned long flags;
1570 bank = container_of(chip, struct gpio_bank, chip);
1571 spin_lock_irqsave(&bank->lock, flags);
1572 _set_gpio_dataout(bank, offset, value);
1573 spin_unlock_irqrestore(&bank->lock, flags);
1576 static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1578 struct gpio_bank *bank;
1580 bank = container_of(chip, struct gpio_bank, chip);
1581 return bank->virtual_irq_start + offset;
1584 /*---------------------------------------------------------------------*/
1586 static int initialized;
1587 #if !(defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4))
1588 static struct clk * gpio_ick;
1591 #if defined(CONFIG_ARCH_OMAP2)
1592 static struct clk * gpio_fck;
1595 #if defined(CONFIG_ARCH_OMAP2430)
1596 static struct clk * gpio5_ick;
1597 static struct clk * gpio5_fck;
1600 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1601 static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
1604 /* This lock class tells lockdep that GPIO irqs are in a different
1605 * category than their parents, so it won't report false recursion.
1607 static struct lock_class_key gpio_lock_class;
1609 static int __init _omap_gpio_init(void)
1613 struct gpio_bank *bank;
1618 #if defined(CONFIG_ARCH_OMAP1)
1619 if (cpu_is_omap15xx()) {
1620 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1621 if (IS_ERR(gpio_ick))
1622 printk("Could not get arm_gpio_ck\n");
1624 clk_enable(gpio_ick);
1627 #if defined(CONFIG_ARCH_OMAP2)
1628 if (cpu_class_is_omap2()) {
1629 gpio_ick = clk_get(NULL, "gpios_ick");
1630 if (IS_ERR(gpio_ick))
1631 printk("Could not get gpios_ick\n");
1633 clk_enable(gpio_ick);
1634 gpio_fck = clk_get(NULL, "gpios_fck");
1635 if (IS_ERR(gpio_fck))
1636 printk("Could not get gpios_fck\n");
1638 clk_enable(gpio_fck);
1641 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
1643 #if defined(CONFIG_ARCH_OMAP2430)
1644 if (cpu_is_omap2430()) {
1645 gpio5_ick = clk_get(NULL, "gpio5_ick");
1646 if (IS_ERR(gpio5_ick))
1647 printk("Could not get gpio5_ick\n");
1649 clk_enable(gpio5_ick);
1650 gpio5_fck = clk_get(NULL, "gpio5_fck");
1651 if (IS_ERR(gpio5_fck))
1652 printk("Could not get gpio5_fck\n");
1654 clk_enable(gpio5_fck);
1660 #if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1661 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
1662 for (i = 0; i < OMAP34XX_NR_GPIOS; i++) {
1663 sprintf(clk_name, "gpio%d_ick", i + 1);
1664 gpio_iclks[i] = clk_get(NULL, clk_name);
1665 if (IS_ERR(gpio_iclks[i]))
1666 printk(KERN_ERR "Could not get %s\n", clk_name);
1668 clk_enable(gpio_iclks[i]);
1674 #ifdef CONFIG_ARCH_OMAP15XX
1675 if (cpu_is_omap15xx()) {
1676 printk(KERN_INFO "OMAP1510 GPIO hardware\n");
1677 gpio_bank_count = 2;
1678 gpio_bank = gpio_bank_1510;
1681 #if defined(CONFIG_ARCH_OMAP16XX)
1682 if (cpu_is_omap16xx()) {
1685 gpio_bank_count = 5;
1686 gpio_bank = gpio_bank_1610;
1687 rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1688 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1689 (rev >> 4) & 0x0f, rev & 0x0f);
1692 #ifdef CONFIG_ARCH_OMAP730
1693 if (cpu_is_omap730()) {
1694 printk(KERN_INFO "OMAP730 GPIO hardware\n");
1695 gpio_bank_count = 7;
1696 gpio_bank = gpio_bank_730;
1699 #ifdef CONFIG_ARCH_OMAP850
1700 if (cpu_is_omap850()) {
1701 printk(KERN_INFO "OMAP850 GPIO hardware\n");
1702 gpio_bank_count = 7;
1703 gpio_bank = gpio_bank_850;
1707 #ifdef CONFIG_ARCH_OMAP24XX
1708 if (cpu_is_omap242x()) {
1711 gpio_bank_count = 4;
1712 gpio_bank = gpio_bank_242x;
1713 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1714 printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n",
1715 (rev >> 4) & 0x0f, rev & 0x0f);
1717 if (cpu_is_omap243x()) {
1720 gpio_bank_count = 5;
1721 gpio_bank = gpio_bank_243x;
1722 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1723 printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n",
1724 (rev >> 4) & 0x0f, rev & 0x0f);
1727 #ifdef CONFIG_ARCH_OMAP34XX
1728 if (cpu_is_omap34xx()) {
1731 gpio_bank_count = OMAP34XX_NR_GPIOS;
1732 gpio_bank = gpio_bank_34xx;
1733 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1734 printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n",
1735 (rev >> 4) & 0x0f, rev & 0x0f);
1738 #ifdef CONFIG_ARCH_OMAP4
1739 if (cpu_is_omap44xx()) {
1742 gpio_bank_count = OMAP34XX_NR_GPIOS;
1743 gpio_bank = gpio_bank_44xx;
1744 rev = __raw_readl(gpio_bank[0].base + OMAP4_GPIO_REVISION);
1745 printk(KERN_INFO "OMAP44xx GPIO hardware version %d.%d\n",
1746 (rev >> 4) & 0x0f, rev & 0x0f);
1749 for (i = 0; i < gpio_bank_count; i++) {
1750 int j, gpio_count = 16;
1752 bank = &gpio_bank[i];
1753 spin_lock_init(&bank->lock);
1754 if (bank_is_mpuio(bank))
1755 __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT);
1756 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1757 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1758 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1760 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1761 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1762 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1763 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1765 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_730) {
1766 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
1767 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
1769 gpio_count = 32; /* 730 has 32-bit GPIOs */
1772 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1773 defined(CONFIG_ARCH_OMAP4)
1774 if (bank->method == METHOD_GPIO_24XX) {
1775 static const u32 non_wakeup_gpios[] = {
1776 0xe203ffc0, 0x08700040
1778 if (cpu_is_omap44xx()) {
1779 __raw_writel(0xffffffff, bank->base +
1780 OMAP4_GPIO_IRQSTATUSCLR0);
1781 __raw_writew(0x0015, bank->base +
1782 OMAP4_GPIO_SYSCONFIG);
1783 __raw_writel(0x00000000, bank->base +
1784 OMAP4_GPIO_DEBOUNCENABLE);
1785 /* Initialize interface clock ungated, module enabled */
1786 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
1788 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1789 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
1790 __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
1791 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_DEBOUNCE_EN);
1793 /* Initialize interface clock ungated, module enabled */
1794 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1796 if (i < ARRAY_SIZE(non_wakeup_gpios))
1797 bank->non_wakeup_gpios = non_wakeup_gpios[i];
1801 /* REVISIT eventually switch from OMAP-specific gpio structs
1802 * over to the generic ones
1804 bank->chip.request = omap_gpio_request;
1805 bank->chip.free = omap_gpio_free;
1806 bank->chip.direction_input = gpio_input;
1807 bank->chip.get = gpio_get;
1808 bank->chip.direction_output = gpio_output;
1809 bank->chip.set = gpio_set;
1810 bank->chip.to_irq = gpio_2irq;
1811 if (bank_is_mpuio(bank)) {
1812 bank->chip.label = "mpuio";
1813 #ifdef CONFIG_ARCH_OMAP16XX
1814 bank->chip.dev = &omap_mpuio_device.dev;
1816 bank->chip.base = OMAP_MPUIO(0);
1818 bank->chip.label = "gpio";
1819 bank->chip.base = gpio;
1822 bank->chip.ngpio = gpio_count;
1824 gpiochip_add(&bank->chip);
1826 for (j = bank->virtual_irq_start;
1827 j < bank->virtual_irq_start + gpio_count; j++) {
1828 lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
1829 set_irq_chip_data(j, bank);
1830 if (bank_is_mpuio(bank))
1831 set_irq_chip(j, &mpuio_irq_chip);
1833 set_irq_chip(j, &gpio_irq_chip);
1834 set_irq_handler(j, handle_simple_irq);
1835 set_irq_flags(j, IRQF_VALID);
1837 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1838 set_irq_data(bank->irq, bank);
1840 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
1841 sprintf(clk_name, "gpio%d_dbck", i + 1);
1842 bank->dbck = clk_get(NULL, clk_name);
1843 if (IS_ERR(bank->dbck))
1844 printk(KERN_ERR "Could not get %s\n", clk_name);
1848 /* Enable system clock for GPIO module.
1849 * The CAM_CLK_CTRL *is* really the right place. */
1850 if (cpu_is_omap16xx())
1851 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1853 /* Enable autoidle for the OCP interface */
1854 if (cpu_is_omap24xx())
1855 omap_writel(1 << 0, 0x48019010);
1856 if (cpu_is_omap34xx())
1857 omap_writel(1 << 0, 0x48306814);
1862 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
1863 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
1864 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1868 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1871 for (i = 0; i < gpio_bank_count; i++) {
1872 struct gpio_bank *bank = &gpio_bank[i];
1873 void __iomem *wake_status;
1874 void __iomem *wake_clear;
1875 void __iomem *wake_set;
1876 unsigned long flags;
1878 switch (bank->method) {
1879 #ifdef CONFIG_ARCH_OMAP16XX
1880 case METHOD_GPIO_1610:
1881 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1882 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1883 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1886 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1887 case METHOD_GPIO_24XX:
1888 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
1889 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1890 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1893 #ifdef CONFIG_ARCH_OMAP4
1894 case METHOD_GPIO_24XX:
1895 wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
1896 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1897 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1904 spin_lock_irqsave(&bank->lock, flags);
1905 bank->saved_wakeup = __raw_readl(wake_status);
1906 __raw_writel(0xffffffff, wake_clear);
1907 __raw_writel(bank->suspend_wakeup, wake_set);
1908 spin_unlock_irqrestore(&bank->lock, flags);
1914 static int omap_gpio_resume(struct sys_device *dev)
1918 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1921 for (i = 0; i < gpio_bank_count; i++) {
1922 struct gpio_bank *bank = &gpio_bank[i];
1923 void __iomem *wake_clear;
1924 void __iomem *wake_set;
1925 unsigned long flags;
1927 switch (bank->method) {
1928 #ifdef CONFIG_ARCH_OMAP16XX
1929 case METHOD_GPIO_1610:
1930 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1931 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1934 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1935 case METHOD_GPIO_24XX:
1936 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1937 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1940 #ifdef CONFIG_ARCH_OMAP4
1941 case METHOD_GPIO_24XX:
1942 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1943 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1950 spin_lock_irqsave(&bank->lock, flags);
1951 __raw_writel(0xffffffff, wake_clear);
1952 __raw_writel(bank->saved_wakeup, wake_set);
1953 spin_unlock_irqrestore(&bank->lock, flags);
1959 static struct sysdev_class omap_gpio_sysclass = {
1961 .suspend = omap_gpio_suspend,
1962 .resume = omap_gpio_resume,
1965 static struct sys_device omap_gpio_device = {
1967 .cls = &omap_gpio_sysclass,
1972 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1973 defined(CONFIG_ARCH_OMAP4)
1975 static int workaround_enabled;
1977 void omap2_gpio_prepare_for_retention(void)
1981 /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious
1982 * IRQs will be generated. See OMAP2420 Errata item 1.101. */
1983 for (i = 0; i < gpio_bank_count; i++) {
1984 struct gpio_bank *bank = &gpio_bank[i];
1987 if (!(bank->enabled_non_wakeup_gpios))
1989 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1990 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1991 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1992 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1994 #ifdef CONFIG_ARCH_OMAP4
1995 bank->saved_datain = __raw_readl(bank->base +
1997 l1 = __raw_readl(bank->base + OMAP4_GPIO_FALLINGDETECT);
1998 l2 = __raw_readl(bank->base + OMAP4_GPIO_RISINGDETECT);
2000 bank->saved_fallingdetect = l1;
2001 bank->saved_risingdetect = l2;
2002 l1 &= ~bank->enabled_non_wakeup_gpios;
2003 l2 &= ~bank->enabled_non_wakeup_gpios;
2004 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
2005 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2006 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
2008 #ifdef CONFIG_ARCH_OMAP4
2009 __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
2010 __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
2015 workaround_enabled = 0;
2018 workaround_enabled = 1;
2021 void omap2_gpio_resume_after_retention(void)
2025 if (!workaround_enabled)
2027 for (i = 0; i < gpio_bank_count; i++) {
2028 struct gpio_bank *bank = &gpio_bank[i];
2031 if (!(bank->enabled_non_wakeup_gpios))
2033 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
2034 __raw_writel(bank->saved_fallingdetect,
2035 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2036 __raw_writel(bank->saved_risingdetect,
2037 bank->base + OMAP24XX_GPIO_RISINGDETECT);
2038 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
2040 #ifdef CONFIG_ARCH_OMAP4
2041 __raw_writel(bank->saved_fallingdetect,
2042 bank->base + OMAP4_GPIO_FALLINGDETECT);
2043 __raw_writel(bank->saved_risingdetect,
2044 bank->base + OMAP4_GPIO_RISINGDETECT);
2045 l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
2047 /* Check if any of the non-wakeup interrupt GPIOs have changed
2048 * state. If so, generate an IRQ by software. This is
2049 * horribly racy, but it's the best we can do to work around
2050 * this silicon bug. */
2051 l ^= bank->saved_datain;
2052 l &= bank->non_wakeup_gpios;
2055 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
2056 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2057 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2058 __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2059 __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2060 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2061 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2063 #ifdef CONFIG_ARCH_OMAP4
2064 old0 = __raw_readl(bank->base +
2065 OMAP4_GPIO_LEVELDETECT0);
2066 old1 = __raw_readl(bank->base +
2067 OMAP4_GPIO_LEVELDETECT1);
2068 __raw_writel(old0 | l, bank->base +
2069 OMAP4_GPIO_LEVELDETECT0);
2070 __raw_writel(old1 | l, bank->base +
2071 OMAP4_GPIO_LEVELDETECT1);
2072 __raw_writel(old0, bank->base +
2073 OMAP4_GPIO_LEVELDETECT0);
2074 __raw_writel(old1, bank->base +
2075 OMAP4_GPIO_LEVELDETECT1);
2085 * This may get called early from board specific init
2086 * for boards that have interrupts routed via FPGA.
2088 int __init omap_gpio_init(void)
2091 return _omap_gpio_init();
2096 static int __init omap_gpio_sysinit(void)
2101 ret = _omap_gpio_init();
2105 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
2106 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
2107 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
2109 ret = sysdev_class_register(&omap_gpio_sysclass);
2111 ret = sysdev_register(&omap_gpio_device);
2119 arch_initcall(omap_gpio_sysinit);
2122 #ifdef CONFIG_DEBUG_FS
2124 #include <linux/debugfs.h>
2125 #include <linux/seq_file.h>
2127 static int dbg_gpio_show(struct seq_file *s, void *unused)
2129 unsigned i, j, gpio;
2131 for (i = 0, gpio = 0; i < gpio_bank_count; i++) {
2132 struct gpio_bank *bank = gpio_bank + i;
2133 unsigned bankwidth = 16;
2136 if (bank_is_mpuio(bank))
2137 gpio = OMAP_MPUIO(0);
2138 else if (cpu_class_is_omap2() || cpu_is_omap730() ||
2142 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
2143 unsigned irq, value, is_in, irqstat;
2146 label = gpiochip_is_requested(&bank->chip, j);
2150 irq = bank->virtual_irq_start + j;
2151 value = gpio_get_value(gpio);
2152 is_in = gpio_is_input(bank, mask);
2154 if (bank_is_mpuio(bank))
2155 seq_printf(s, "MPUIO %2d ", j);
2157 seq_printf(s, "GPIO %3d ", gpio);
2158 seq_printf(s, "(%-20.20s): %s %s",
2160 is_in ? "in " : "out",
2161 value ? "hi" : "lo");
2163 /* FIXME for at least omap2, show pullup/pulldown state */
2165 irqstat = irq_desc[irq].status;
2166 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
2167 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
2168 if (is_in && ((bank->suspend_wakeup & mask)
2169 || irqstat & IRQ_TYPE_SENSE_MASK)) {
2170 char *trigger = NULL;
2172 switch (irqstat & IRQ_TYPE_SENSE_MASK) {
2173 case IRQ_TYPE_EDGE_FALLING:
2174 trigger = "falling";
2176 case IRQ_TYPE_EDGE_RISING:
2179 case IRQ_TYPE_EDGE_BOTH:
2180 trigger = "bothedge";
2182 case IRQ_TYPE_LEVEL_LOW:
2185 case IRQ_TYPE_LEVEL_HIGH:
2192 seq_printf(s, ", irq-%d %-8s%s",
2194 (bank->suspend_wakeup & mask)
2198 seq_printf(s, "\n");
2201 if (bank_is_mpuio(bank)) {
2202 seq_printf(s, "\n");
2209 static int dbg_gpio_open(struct inode *inode, struct file *file)
2211 return single_open(file, dbg_gpio_show, &inode->i_private);
2214 static const struct file_operations debug_fops = {
2215 .open = dbg_gpio_open,
2217 .llseek = seq_lseek,
2218 .release = single_release,
2221 static int __init omap_gpio_debuginit(void)
2223 (void) debugfs_create_file("omap_gpio", S_IRUGO,
2224 NULL, NULL, &debug_fops);
2227 late_initcall(omap_gpio_debuginit);