2 * linux/arch/arm/plat-omap/dma.c
4 * Copyright (C) 2003 - 2008 Nokia Corporation
5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7 * Graphics DMA and LCD DMA graphics tranformations
8 * by Imre Deak <imre.deak@nokia.com>
9 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
10 * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
11 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
13 * Copyright (C) 2009 Texas Instruments
14 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
16 * Support functions for the OMAP internal DMA channels.
18 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
19 * Converted DMA library into DMA platform driver.
20 * - G, Manjunath Kondaiah <manjugk@ti.com>
22 * This program is free software; you can redistribute it and/or modify
23 * it under the terms of the GNU General Public License version 2 as
24 * published by the Free Software Foundation.
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/sched.h>
31 #include <linux/spinlock.h>
32 #include <linux/errno.h>
33 #include <linux/interrupt.h>
34 #include <linux/irq.h>
36 #include <linux/slab.h>
37 #include <linux/delay.h>
39 #include <asm/system.h>
40 #include <mach/hardware.h>
47 #ifndef CONFIG_ARCH_OMAP1
48 enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
49 DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
52 enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
55 #define OMAP_DMA_ACTIVE 0x01
56 #define OMAP2_DMA_CSR_CLEAR_MASK 0xffffffff
58 #define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
60 static struct omap_system_dma_plat_info *p;
61 static struct omap_dma_dev_attr *d;
63 static int enable_1510_mode;
66 static struct omap_dma_global_context_registers {
68 u32 dma_ocp_sysconfig;
70 } omap_dma_global_context;
72 struct dma_link_info {
74 int no_of_lchs_linked;
85 static struct dma_link_info *dma_linked_lch;
87 #ifndef CONFIG_ARCH_OMAP1
89 /* Chain handling macros */
90 #define OMAP_DMA_CHAIN_QINIT(chain_id) \
92 dma_linked_lch[chain_id].q_head = \
93 dma_linked_lch[chain_id].q_tail = \
94 dma_linked_lch[chain_id].q_count = 0; \
96 #define OMAP_DMA_CHAIN_QFULL(chain_id) \
97 (dma_linked_lch[chain_id].no_of_lchs_linked == \
98 dma_linked_lch[chain_id].q_count)
99 #define OMAP_DMA_CHAIN_QLAST(chain_id) \
101 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) == \
102 dma_linked_lch[chain_id].q_count) \
104 #define OMAP_DMA_CHAIN_QEMPTY(chain_id) \
105 (0 == dma_linked_lch[chain_id].q_count)
106 #define __OMAP_DMA_CHAIN_INCQ(end) \
107 ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
108 #define OMAP_DMA_CHAIN_INCQHEAD(chain_id) \
110 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
111 dma_linked_lch[chain_id].q_count--; \
114 #define OMAP_DMA_CHAIN_INCQTAIL(chain_id) \
116 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
117 dma_linked_lch[chain_id].q_count++; \
121 static int dma_lch_count;
122 static int dma_chan_count;
123 static int omap_dma_reserve_channels;
125 static spinlock_t dma_chan_lock;
126 static struct omap_dma_lch *dma_chan;
128 static inline void disable_lnk(int lch);
129 static void omap_disable_channel_irq(int lch);
130 static inline void omap_enable_channel_irq(int lch);
132 #define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \
135 #ifdef CONFIG_ARCH_OMAP15XX
136 /* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
137 static int omap_dma_in_1510_mode(void)
139 return enable_1510_mode;
142 #define omap_dma_in_1510_mode() 0
145 #ifdef CONFIG_ARCH_OMAP1
146 static inline int get_gdma_dev(int req)
148 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
149 int shift = ((req - 1) % 5) * 6;
151 return ((omap_readl(reg) >> shift) & 0x3f) + 1;
154 static inline void set_gdma_dev(int req, int dev)
156 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
157 int shift = ((req - 1) % 5) * 6;
161 l &= ~(0x3f << shift);
162 l |= (dev - 1) << shift;
166 #define set_gdma_dev(req, dev) do {} while (0)
169 void omap_set_dma_priority(int lch, int dst_port, int priority)
174 if (cpu_class_is_omap1()) {
176 case OMAP_DMA_PORT_OCP_T1: /* FFFECC00 */
177 reg = OMAP_TC_OCPT1_PRIOR;
179 case OMAP_DMA_PORT_OCP_T2: /* FFFECCD0 */
180 reg = OMAP_TC_OCPT2_PRIOR;
182 case OMAP_DMA_PORT_EMIFF: /* FFFECC08 */
183 reg = OMAP_TC_EMIFF_PRIOR;
185 case OMAP_DMA_PORT_EMIFS: /* FFFECC04 */
186 reg = OMAP_TC_EMIFS_PRIOR;
194 l |= (priority & 0xf) << 8;
198 if (cpu_class_is_omap2()) {
201 ccr = p->dma_read(CCR, lch);
206 p->dma_write(ccr, CCR, lch);
209 EXPORT_SYMBOL(omap_set_dma_priority);
211 void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
212 int frame_count, int sync_mode,
213 int dma_trigger, int src_or_dst_synch)
217 l = p->dma_read(CSDP, lch);
220 p->dma_write(l, CSDP, lch);
222 if (cpu_class_is_omap1()) {
225 ccr = p->dma_read(CCR, lch);
227 if (sync_mode == OMAP_DMA_SYNC_FRAME)
229 p->dma_write(ccr, CCR, lch);
231 ccr = p->dma_read(CCR2, lch);
233 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
235 p->dma_write(ccr, CCR2, lch);
238 if (cpu_class_is_omap2() && dma_trigger) {
241 val = p->dma_read(CCR, lch);
243 /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
244 val &= ~((1 << 23) | (3 << 19) | 0x1f);
245 val |= (dma_trigger & ~0x1f) << 14;
246 val |= dma_trigger & 0x1f;
248 if (sync_mode & OMAP_DMA_SYNC_FRAME)
253 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
258 if (src_or_dst_synch == OMAP_DMA_DST_SYNC_PREFETCH) {
259 val &= ~(1 << 24); /* dest synch */
260 val |= (1 << 23); /* Prefetch */
261 } else if (src_or_dst_synch) {
262 val |= 1 << 24; /* source synch */
264 val &= ~(1 << 24); /* dest synch */
266 p->dma_write(val, CCR, lch);
269 p->dma_write(elem_count, CEN, lch);
270 p->dma_write(frame_count, CFN, lch);
272 EXPORT_SYMBOL(omap_set_dma_transfer_params);
274 void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
276 BUG_ON(omap_dma_in_1510_mode());
278 if (cpu_class_is_omap1()) {
281 w = p->dma_read(CCR2, lch);
285 case OMAP_DMA_CONSTANT_FILL:
288 case OMAP_DMA_TRANSPARENT_COPY:
291 case OMAP_DMA_COLOR_DIS:
296 p->dma_write(w, CCR2, lch);
298 w = p->dma_read(LCH_CTRL, lch);
300 /* Default is channel type 2D */
302 p->dma_write(color, COLOR, lch);
303 w |= 1; /* Channel type G */
305 p->dma_write(w, LCH_CTRL, lch);
308 if (cpu_class_is_omap2()) {
311 val = p->dma_read(CCR, lch);
312 val &= ~((1 << 17) | (1 << 16));
315 case OMAP_DMA_CONSTANT_FILL:
318 case OMAP_DMA_TRANSPARENT_COPY:
321 case OMAP_DMA_COLOR_DIS:
326 p->dma_write(val, CCR, lch);
329 p->dma_write(color, COLOR, lch);
332 EXPORT_SYMBOL(omap_set_dma_color_mode);
334 void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
336 if (cpu_class_is_omap2()) {
339 csdp = p->dma_read(CSDP, lch);
340 csdp &= ~(0x3 << 16);
341 csdp |= (mode << 16);
342 p->dma_write(csdp, CSDP, lch);
345 EXPORT_SYMBOL(omap_set_dma_write_mode);
347 void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
349 if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
352 l = p->dma_read(LCH_CTRL, lch);
355 p->dma_write(l, LCH_CTRL, lch);
358 EXPORT_SYMBOL(omap_set_dma_channel_mode);
360 /* Note that src_port is only for omap1 */
361 void omap_set_dma_src_params(int lch, int src_port, int src_amode,
362 unsigned long src_start,
363 int src_ei, int src_fi)
367 if (cpu_class_is_omap1()) {
370 w = p->dma_read(CSDP, lch);
373 p->dma_write(w, CSDP, lch);
376 l = p->dma_read(CCR, lch);
378 l |= src_amode << 12;
379 p->dma_write(l, CCR, lch);
381 p->dma_write(src_start, CSSA, lch);
383 p->dma_write(src_ei, CSEI, lch);
384 p->dma_write(src_fi, CSFI, lch);
386 EXPORT_SYMBOL(omap_set_dma_src_params);
388 void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
390 omap_set_dma_transfer_params(lch, params->data_type,
391 params->elem_count, params->frame_count,
392 params->sync_mode, params->trigger,
393 params->src_or_dst_synch);
394 omap_set_dma_src_params(lch, params->src_port,
395 params->src_amode, params->src_start,
396 params->src_ei, params->src_fi);
398 omap_set_dma_dest_params(lch, params->dst_port,
399 params->dst_amode, params->dst_start,
400 params->dst_ei, params->dst_fi);
401 if (params->read_prio || params->write_prio)
402 omap_dma_set_prio_lch(lch, params->read_prio,
405 EXPORT_SYMBOL(omap_set_dma_params);
407 void omap_set_dma_src_index(int lch, int eidx, int fidx)
409 if (cpu_class_is_omap2())
412 p->dma_write(eidx, CSEI, lch);
413 p->dma_write(fidx, CSFI, lch);
415 EXPORT_SYMBOL(omap_set_dma_src_index);
417 void omap_set_dma_src_data_pack(int lch, int enable)
421 l = p->dma_read(CSDP, lch);
425 p->dma_write(l, CSDP, lch);
427 EXPORT_SYMBOL(omap_set_dma_src_data_pack);
429 void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
431 unsigned int burst = 0;
434 l = p->dma_read(CSDP, lch);
437 switch (burst_mode) {
438 case OMAP_DMA_DATA_BURST_DIS:
440 case OMAP_DMA_DATA_BURST_4:
441 if (cpu_class_is_omap2())
446 case OMAP_DMA_DATA_BURST_8:
447 if (cpu_class_is_omap2()) {
452 * not supported by current hardware on OMAP1
456 case OMAP_DMA_DATA_BURST_16:
457 if (cpu_class_is_omap2()) {
462 * OMAP1 don't support burst 16
470 p->dma_write(l, CSDP, lch);
472 EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
474 /* Note that dest_port is only for OMAP1 */
475 void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
476 unsigned long dest_start,
477 int dst_ei, int dst_fi)
481 if (cpu_class_is_omap1()) {
482 l = p->dma_read(CSDP, lch);
485 p->dma_write(l, CSDP, lch);
488 l = p->dma_read(CCR, lch);
490 l |= dest_amode << 14;
491 p->dma_write(l, CCR, lch);
493 p->dma_write(dest_start, CDSA, lch);
495 p->dma_write(dst_ei, CDEI, lch);
496 p->dma_write(dst_fi, CDFI, lch);
498 EXPORT_SYMBOL(omap_set_dma_dest_params);
500 void omap_set_dma_dest_index(int lch, int eidx, int fidx)
502 if (cpu_class_is_omap2())
505 p->dma_write(eidx, CDEI, lch);
506 p->dma_write(fidx, CDFI, lch);
508 EXPORT_SYMBOL(omap_set_dma_dest_index);
510 void omap_set_dma_dest_data_pack(int lch, int enable)
514 l = p->dma_read(CSDP, lch);
518 p->dma_write(l, CSDP, lch);
520 EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
522 void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
524 unsigned int burst = 0;
527 l = p->dma_read(CSDP, lch);
530 switch (burst_mode) {
531 case OMAP_DMA_DATA_BURST_DIS:
533 case OMAP_DMA_DATA_BURST_4:
534 if (cpu_class_is_omap2())
539 case OMAP_DMA_DATA_BURST_8:
540 if (cpu_class_is_omap2())
545 case OMAP_DMA_DATA_BURST_16:
546 if (cpu_class_is_omap2()) {
551 * OMAP1 don't support burst 16
555 printk(KERN_ERR "Invalid DMA burst mode\n");
560 p->dma_write(l, CSDP, lch);
562 EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
564 static inline void omap_enable_channel_irq(int lch)
569 if (cpu_class_is_omap1())
570 status = p->dma_read(CSR, lch);
571 else if (cpu_class_is_omap2())
572 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
574 /* Enable some nice interrupts. */
575 p->dma_write(dma_chan[lch].enabled_irqs, CICR, lch);
578 static void omap_disable_channel_irq(int lch)
580 if (cpu_class_is_omap2())
581 p->dma_write(0, CICR, lch);
584 void omap_enable_dma_irq(int lch, u16 bits)
586 dma_chan[lch].enabled_irqs |= bits;
588 EXPORT_SYMBOL(omap_enable_dma_irq);
590 void omap_disable_dma_irq(int lch, u16 bits)
592 dma_chan[lch].enabled_irqs &= ~bits;
594 EXPORT_SYMBOL(omap_disable_dma_irq);
596 static inline void enable_lnk(int lch)
600 l = p->dma_read(CLNK_CTRL, lch);
602 if (cpu_class_is_omap1())
605 /* Set the ENABLE_LNK bits */
606 if (dma_chan[lch].next_lch != -1)
607 l = dma_chan[lch].next_lch | (1 << 15);
609 #ifndef CONFIG_ARCH_OMAP1
610 if (cpu_class_is_omap2())
611 if (dma_chan[lch].next_linked_ch != -1)
612 l = dma_chan[lch].next_linked_ch | (1 << 15);
615 p->dma_write(l, CLNK_CTRL, lch);
618 static inline void disable_lnk(int lch)
622 l = p->dma_read(CLNK_CTRL, lch);
624 /* Disable interrupts */
625 if (cpu_class_is_omap1()) {
626 p->dma_write(0, CICR, lch);
627 /* Set the STOP_LNK bit */
631 if (cpu_class_is_omap2()) {
632 omap_disable_channel_irq(lch);
633 /* Clear the ENABLE_LNK bit */
637 p->dma_write(l, CLNK_CTRL, lch);
638 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
641 static inline void omap2_enable_irq_lch(int lch)
646 if (!cpu_class_is_omap2())
649 spin_lock_irqsave(&dma_chan_lock, flags);
650 val = p->dma_read(IRQENABLE_L0, lch);
652 p->dma_write(val, IRQENABLE_L0, lch);
653 spin_unlock_irqrestore(&dma_chan_lock, flags);
656 static inline void omap2_disable_irq_lch(int lch)
661 if (!cpu_class_is_omap2())
664 spin_lock_irqsave(&dma_chan_lock, flags);
665 val = p->dma_read(IRQENABLE_L0, lch);
667 p->dma_write(val, IRQENABLE_L0, lch);
668 spin_unlock_irqrestore(&dma_chan_lock, flags);
671 int omap_request_dma(int dev_id, const char *dev_name,
672 void (*callback)(int lch, u16 ch_status, void *data),
673 void *data, int *dma_ch_out)
675 int ch, free_ch = -1;
677 struct omap_dma_lch *chan;
679 spin_lock_irqsave(&dma_chan_lock, flags);
680 for (ch = 0; ch < dma_chan_count; ch++) {
681 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
688 spin_unlock_irqrestore(&dma_chan_lock, flags);
691 chan = dma_chan + free_ch;
692 chan->dev_id = dev_id;
694 if (p->clear_lch_regs)
695 p->clear_lch_regs(free_ch);
697 if (cpu_class_is_omap2())
698 omap_clear_dma(free_ch);
700 spin_unlock_irqrestore(&dma_chan_lock, flags);
702 chan->dev_name = dev_name;
703 chan->callback = callback;
707 #ifndef CONFIG_ARCH_OMAP1
708 if (cpu_class_is_omap2()) {
710 chan->next_linked_ch = -1;
714 chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
716 if (cpu_class_is_omap1())
717 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
718 else if (cpu_class_is_omap2())
719 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
720 OMAP2_DMA_TRANS_ERR_IRQ;
722 if (cpu_is_omap16xx()) {
723 /* If the sync device is set, configure it dynamically. */
725 set_gdma_dev(free_ch + 1, dev_id);
726 dev_id = free_ch + 1;
729 * Disable the 1510 compatibility mode and set the sync device
732 p->dma_write(dev_id | (1 << 10), CCR, free_ch);
733 } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) {
734 p->dma_write(dev_id, CCR, free_ch);
737 if (cpu_class_is_omap2()) {
738 omap2_enable_irq_lch(free_ch);
739 omap_enable_channel_irq(free_ch);
740 /* Clear the CSR register and IRQ status register */
741 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, free_ch);
742 p->dma_write(1 << free_ch, IRQSTATUS_L0, 0);
745 *dma_ch_out = free_ch;
749 EXPORT_SYMBOL(omap_request_dma);
751 void omap_free_dma(int lch)
755 if (dma_chan[lch].dev_id == -1) {
756 pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
761 if (cpu_class_is_omap1()) {
762 /* Disable all DMA interrupts for the channel. */
763 p->dma_write(0, CICR, lch);
764 /* Make sure the DMA transfer is stopped. */
765 p->dma_write(0, CCR, lch);
768 if (cpu_class_is_omap2()) {
769 omap2_disable_irq_lch(lch);
771 /* Clear the CSR register and IRQ status register */
772 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
773 p->dma_write(1 << lch, IRQSTATUS_L0, lch);
775 /* Disable all DMA interrupts for the channel. */
776 p->dma_write(0, CICR, lch);
778 /* Make sure the DMA transfer is stopped. */
779 p->dma_write(0, CCR, lch);
783 spin_lock_irqsave(&dma_chan_lock, flags);
784 dma_chan[lch].dev_id = -1;
785 dma_chan[lch].next_lch = -1;
786 dma_chan[lch].callback = NULL;
787 spin_unlock_irqrestore(&dma_chan_lock, flags);
789 EXPORT_SYMBOL(omap_free_dma);
792 * @brief omap_dma_set_global_params : Set global priority settings for dma
795 * @param max_fifo_depth
796 * @param tparams - Number of threads to reserve : DMA_THREAD_RESERVE_NORM
797 * DMA_THREAD_RESERVE_ONET
798 * DMA_THREAD_RESERVE_TWOT
799 * DMA_THREAD_RESERVE_THREET
802 omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
806 if (!cpu_class_is_omap2()) {
807 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
811 if (max_fifo_depth == 0)
816 reg = 0xff & max_fifo_depth;
817 reg |= (0x3 & tparams) << 12;
818 reg |= (arb_rate & 0xff) << 16;
820 p->dma_write(reg, GCR, 0);
822 EXPORT_SYMBOL(omap_dma_set_global_params);
825 * @brief omap_dma_set_prio_lch : Set channel wise priority settings
828 * @param read_prio - Read priority
829 * @param write_prio - Write priority
830 * Both of the above can be set with one of the following values :
831 * DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
834 omap_dma_set_prio_lch(int lch, unsigned char read_prio,
835 unsigned char write_prio)
839 if (unlikely((lch < 0 || lch >= dma_lch_count))) {
840 printk(KERN_ERR "Invalid channel id\n");
843 l = p->dma_read(CCR, lch);
844 l &= ~((1 << 6) | (1 << 26));
845 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx())
846 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
848 l |= ((read_prio & 0x1) << 6);
850 p->dma_write(l, CCR, lch);
854 EXPORT_SYMBOL(omap_dma_set_prio_lch);
857 * Clears any DMA state so the DMA engine is ready to restart with new buffers
858 * through omap_start_dma(). Any buffers in flight are discarded.
860 void omap_clear_dma(int lch)
864 local_irq_save(flags);
866 local_irq_restore(flags);
868 EXPORT_SYMBOL(omap_clear_dma);
870 void omap_start_dma(int lch)
875 * The CPC/CDAC register needs to be initialized to zero
876 * before starting dma transfer.
878 if (cpu_is_omap15xx())
879 p->dma_write(0, CPC, lch);
881 p->dma_write(0, CDAC, lch);
883 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
884 int next_lch, cur_lch;
885 char dma_chan_link_map[dma_lch_count];
887 dma_chan_link_map[lch] = 1;
888 /* Set the link register of the first channel */
891 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
892 cur_lch = dma_chan[lch].next_lch;
894 next_lch = dma_chan[cur_lch].next_lch;
896 /* The loop case: we've been here already */
897 if (dma_chan_link_map[cur_lch])
899 /* Mark the current channel */
900 dma_chan_link_map[cur_lch] = 1;
903 omap_enable_channel_irq(cur_lch);
906 } while (next_lch != -1);
907 } else if (IS_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS))
908 p->dma_write(lch, CLNK_CTRL, lch);
910 omap_enable_channel_irq(lch);
912 l = p->dma_read(CCR, lch);
914 if (IS_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING))
915 l |= OMAP_DMA_CCR_BUFFERING_DISABLE;
916 l |= OMAP_DMA_CCR_EN;
918 p->dma_write(l, CCR, lch);
920 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
922 EXPORT_SYMBOL(omap_start_dma);
924 void omap_stop_dma(int lch)
928 /* Disable all interrupts on the channel */
929 if (cpu_class_is_omap1())
930 p->dma_write(0, CICR, lch);
932 l = p->dma_read(CCR, lch);
933 if (IS_DMA_ERRATA(DMA_ERRATA_i541) &&
934 (l & OMAP_DMA_CCR_SEL_SRC_DST_SYNC)) {
938 /* Configure No-Standby */
939 l = p->dma_read(OCP_SYSCONFIG, lch);
941 l &= ~DMA_SYSCONFIG_MIDLEMODE_MASK;
942 l |= DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_NO_IDLE);
943 p->dma_write(l , OCP_SYSCONFIG, 0);
945 l = p->dma_read(CCR, lch);
946 l &= ~OMAP_DMA_CCR_EN;
947 p->dma_write(l, CCR, lch);
949 /* Wait for sDMA FIFO drain */
950 l = p->dma_read(CCR, lch);
951 while (i < 100 && (l & (OMAP_DMA_CCR_RD_ACTIVE |
952 OMAP_DMA_CCR_WR_ACTIVE))) {
955 l = p->dma_read(CCR, lch);
958 printk(KERN_ERR "DMA drain did not complete on "
960 /* Restore OCP_SYSCONFIG */
961 p->dma_write(sys_cf, OCP_SYSCONFIG, lch);
963 l &= ~OMAP_DMA_CCR_EN;
964 p->dma_write(l, CCR, lch);
967 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
968 int next_lch, cur_lch = lch;
969 char dma_chan_link_map[dma_lch_count];
971 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
973 /* The loop case: we've been here already */
974 if (dma_chan_link_map[cur_lch])
976 /* Mark the current channel */
977 dma_chan_link_map[cur_lch] = 1;
979 disable_lnk(cur_lch);
981 next_lch = dma_chan[cur_lch].next_lch;
983 } while (next_lch != -1);
986 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
988 EXPORT_SYMBOL(omap_stop_dma);
991 * Allows changing the DMA callback function or data. This may be needed if
992 * the driver shares a single DMA channel for multiple dma triggers.
994 int omap_set_dma_callback(int lch,
995 void (*callback)(int lch, u16 ch_status, void *data),
1003 spin_lock_irqsave(&dma_chan_lock, flags);
1004 if (dma_chan[lch].dev_id == -1) {
1005 printk(KERN_ERR "DMA callback for not set for free channel\n");
1006 spin_unlock_irqrestore(&dma_chan_lock, flags);
1009 dma_chan[lch].callback = callback;
1010 dma_chan[lch].data = data;
1011 spin_unlock_irqrestore(&dma_chan_lock, flags);
1015 EXPORT_SYMBOL(omap_set_dma_callback);
1018 * Returns current physical source address for the given DMA channel.
1019 * If the channel is running the caller must disable interrupts prior calling
1020 * this function and process the returned value before re-enabling interrupt to
1021 * prevent races with the interrupt handler. Note that in continuous mode there
1022 * is a chance for CSSA_L register overflow between the two reads resulting
1023 * in incorrect return value.
1025 dma_addr_t omap_get_dma_src_pos(int lch)
1027 dma_addr_t offset = 0;
1029 if (cpu_is_omap15xx())
1030 offset = p->dma_read(CPC, lch);
1032 offset = p->dma_read(CSAC, lch);
1034 if (IS_DMA_ERRATA(DMA_ERRATA_3_3) && offset == 0)
1035 offset = p->dma_read(CSAC, lch);
1037 if (!cpu_is_omap15xx()) {
1039 * CDAC == 0 indicates that the DMA transfer on the channel has
1040 * not been started (no data has been transferred so far).
1041 * Return the programmed source start address in this case.
1043 if (likely(p->dma_read(CDAC, lch)))
1044 offset = p->dma_read(CSAC, lch);
1046 offset = p->dma_read(CSSA, lch);
1049 if (cpu_class_is_omap1())
1050 offset |= (p->dma_read(CSSA, lch) & 0xFFFF0000);
1054 EXPORT_SYMBOL(omap_get_dma_src_pos);
1057 * Returns current physical destination address for the given DMA channel.
1058 * If the channel is running the caller must disable interrupts prior calling
1059 * this function and process the returned value before re-enabling interrupt to
1060 * prevent races with the interrupt handler. Note that in continuous mode there
1061 * is a chance for CDSA_L register overflow between the two reads resulting
1062 * in incorrect return value.
1064 dma_addr_t omap_get_dma_dst_pos(int lch)
1066 dma_addr_t offset = 0;
1068 if (cpu_is_omap15xx())
1069 offset = p->dma_read(CPC, lch);
1071 offset = p->dma_read(CDAC, lch);
1074 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1075 * read before the DMA controller finished disabling the channel.
1077 if (!cpu_is_omap15xx() && offset == 0) {
1078 offset = p->dma_read(CDAC, lch);
1080 * CDAC == 0 indicates that the DMA transfer on the channel has
1081 * not been started (no data has been transferred so far).
1082 * Return the programmed destination start address in this case.
1084 if (unlikely(!offset))
1085 offset = p->dma_read(CDSA, lch);
1088 if (cpu_class_is_omap1())
1089 offset |= (p->dma_read(CDSA, lch) & 0xFFFF0000);
1093 EXPORT_SYMBOL(omap_get_dma_dst_pos);
1095 int omap_get_dma_active_status(int lch)
1097 return (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN) != 0;
1099 EXPORT_SYMBOL(omap_get_dma_active_status);
1101 int omap_dma_running(void)
1105 if (cpu_class_is_omap1())
1106 if (omap_lcd_dma_running())
1109 for (lch = 0; lch < dma_chan_count; lch++)
1110 if (p->dma_read(CCR, lch) & OMAP_DMA_CCR_EN)
1117 * lch_queue DMA will start right after lch_head one is finished.
1118 * For this DMA link to start, you still need to start (see omap_start_dma)
1119 * the first one. That will fire up the entire queue.
1121 void omap_dma_link_lch(int lch_head, int lch_queue)
1123 if (omap_dma_in_1510_mode()) {
1124 if (lch_head == lch_queue) {
1125 p->dma_write(p->dma_read(CCR, lch_head) | (3 << 8),
1129 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1134 if ((dma_chan[lch_head].dev_id == -1) ||
1135 (dma_chan[lch_queue].dev_id == -1)) {
1136 printk(KERN_ERR "omap_dma: trying to link "
1137 "non requested channels\n");
1141 dma_chan[lch_head].next_lch = lch_queue;
1143 EXPORT_SYMBOL(omap_dma_link_lch);
1146 * Once the DMA queue is stopped, we can destroy it.
1148 void omap_dma_unlink_lch(int lch_head, int lch_queue)
1150 if (omap_dma_in_1510_mode()) {
1151 if (lch_head == lch_queue) {
1152 p->dma_write(p->dma_read(CCR, lch_head) & ~(3 << 8),
1156 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1161 if (dma_chan[lch_head].next_lch != lch_queue ||
1162 dma_chan[lch_head].next_lch == -1) {
1163 printk(KERN_ERR "omap_dma: trying to unlink "
1164 "non linked channels\n");
1168 if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
1169 (dma_chan[lch_queue].flags & OMAP_DMA_ACTIVE)) {
1170 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
1171 "before unlinking\n");
1175 dma_chan[lch_head].next_lch = -1;
1177 EXPORT_SYMBOL(omap_dma_unlink_lch);
1179 #ifndef CONFIG_ARCH_OMAP1
1180 /* Create chain of DMA channesls */
1181 static void create_dma_lch_chain(int lch_head, int lch_queue)
1185 /* Check if this is the first link in chain */
1186 if (dma_chan[lch_head].next_linked_ch == -1) {
1187 dma_chan[lch_head].next_linked_ch = lch_queue;
1188 dma_chan[lch_head].prev_linked_ch = lch_queue;
1189 dma_chan[lch_queue].next_linked_ch = lch_head;
1190 dma_chan[lch_queue].prev_linked_ch = lch_head;
1193 /* a link exists, link the new channel in circular chain */
1195 dma_chan[lch_queue].next_linked_ch =
1196 dma_chan[lch_head].next_linked_ch;
1197 dma_chan[lch_queue].prev_linked_ch = lch_head;
1198 dma_chan[lch_head].next_linked_ch = lch_queue;
1199 dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch =
1203 l = p->dma_read(CLNK_CTRL, lch_head);
1206 p->dma_write(l, CLNK_CTRL, lch_head);
1208 l = p->dma_read(CLNK_CTRL, lch_queue);
1210 l |= (dma_chan[lch_queue].next_linked_ch);
1211 p->dma_write(l, CLNK_CTRL, lch_queue);
1215 * @brief omap_request_dma_chain : Request a chain of DMA channels
1217 * @param dev_id - Device id using the dma channel
1218 * @param dev_name - Device name
1219 * @param callback - Call back function
1221 * @no_of_chans - Number of channels requested
1222 * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
1223 * OMAP_DMA_DYNAMIC_CHAIN
1224 * @params - Channel parameters
1226 * @return - Success : 0
1227 * Failure: -EINVAL/-ENOMEM
1229 int omap_request_dma_chain(int dev_id, const char *dev_name,
1230 void (*callback) (int lch, u16 ch_status,
1232 int *chain_id, int no_of_chans, int chain_mode,
1233 struct omap_dma_channel_params params)
1238 /* Is the chain mode valid ? */
1239 if (chain_mode != OMAP_DMA_STATIC_CHAIN
1240 && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) {
1241 printk(KERN_ERR "Invalid chain mode requested\n");
1245 if (unlikely((no_of_chans < 1
1246 || no_of_chans > dma_lch_count))) {
1247 printk(KERN_ERR "Invalid Number of channels requested\n");
1252 * Allocate a queue to maintain the status of the channels
1255 channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL);
1256 if (channels == NULL) {
1257 printk(KERN_ERR "omap_dma: No memory for channel queue\n");
1261 /* request and reserve DMA channels for the chain */
1262 for (i = 0; i < no_of_chans; i++) {
1263 err = omap_request_dma(dev_id, dev_name,
1264 callback, NULL, &channels[i]);
1267 for (j = 0; j < i; j++)
1268 omap_free_dma(channels[j]);
1270 printk(KERN_ERR "omap_dma: Request failed %d\n", err);
1273 dma_chan[channels[i]].prev_linked_ch = -1;
1274 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1277 * Allowing client drivers to set common parameters now,
1278 * so that later only relevant (src_start, dest_start
1279 * and element count) can be set
1281 omap_set_dma_params(channels[i], ¶ms);
1284 *chain_id = channels[0];
1285 dma_linked_lch[*chain_id].linked_dmach_q = channels;
1286 dma_linked_lch[*chain_id].chain_mode = chain_mode;
1287 dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1288 dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans;
1290 for (i = 0; i < no_of_chans; i++)
1291 dma_chan[channels[i]].chain_id = *chain_id;
1293 /* Reset the Queue pointers */
1294 OMAP_DMA_CHAIN_QINIT(*chain_id);
1296 /* Set up the chain */
1297 if (no_of_chans == 1)
1298 create_dma_lch_chain(channels[0], channels[0]);
1300 for (i = 0; i < (no_of_chans - 1); i++)
1301 create_dma_lch_chain(channels[i], channels[i + 1]);
1306 EXPORT_SYMBOL(omap_request_dma_chain);
1309 * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
1310 * params after setting it. Dont do this while dma is running!!
1312 * @param chain_id - Chained logical channel id.
1315 * @return - Success : 0
1318 int omap_modify_dma_chain_params(int chain_id,
1319 struct omap_dma_channel_params params)
1324 /* Check for input params */
1325 if (unlikely((chain_id < 0
1326 || chain_id >= dma_lch_count))) {
1327 printk(KERN_ERR "Invalid chain id\n");
1331 /* Check if the chain exists */
1332 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1333 printk(KERN_ERR "Chain doesn't exists\n");
1336 channels = dma_linked_lch[chain_id].linked_dmach_q;
1338 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1340 * Allowing client drivers to set common parameters now,
1341 * so that later only relevant (src_start, dest_start
1342 * and element count) can be set
1344 omap_set_dma_params(channels[i], ¶ms);
1349 EXPORT_SYMBOL(omap_modify_dma_chain_params);
1352 * @brief omap_free_dma_chain - Free all the logical channels in a chain.
1356 * @return - Success : 0
1359 int omap_free_dma_chain(int chain_id)
1364 /* Check for input params */
1365 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1366 printk(KERN_ERR "Invalid chain id\n");
1370 /* Check if the chain exists */
1371 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1372 printk(KERN_ERR "Chain doesn't exists\n");
1376 channels = dma_linked_lch[chain_id].linked_dmach_q;
1377 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1378 dma_chan[channels[i]].next_linked_ch = -1;
1379 dma_chan[channels[i]].prev_linked_ch = -1;
1380 dma_chan[channels[i]].chain_id = -1;
1381 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1382 omap_free_dma(channels[i]);
1387 dma_linked_lch[chain_id].linked_dmach_q = NULL;
1388 dma_linked_lch[chain_id].chain_mode = -1;
1389 dma_linked_lch[chain_id].chain_state = -1;
1393 EXPORT_SYMBOL(omap_free_dma_chain);
1396 * @brief omap_dma_chain_status - Check if the chain is in
1397 * active / inactive state.
1400 * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
1403 int omap_dma_chain_status(int chain_id)
1405 /* Check for input params */
1406 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1407 printk(KERN_ERR "Invalid chain id\n");
1411 /* Check if the chain exists */
1412 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1413 printk(KERN_ERR "Chain doesn't exists\n");
1416 pr_debug("CHAINID=%d, qcnt=%d\n", chain_id,
1417 dma_linked_lch[chain_id].q_count);
1419 if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
1420 return OMAP_DMA_CHAIN_INACTIVE;
1422 return OMAP_DMA_CHAIN_ACTIVE;
1424 EXPORT_SYMBOL(omap_dma_chain_status);
1427 * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
1428 * set the params and start the transfer.
1431 * @param src_start - buffer start address
1432 * @param dest_start - Dest address
1434 * @param frame_count
1435 * @param callbk_data - channel callback parameter data.
1437 * @return - Success : 0
1438 * Failure: -EINVAL/-EBUSY
1440 int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1441 int elem_count, int frame_count, void *callbk_data)
1448 * if buffer size is less than 1 then there is
1449 * no use of starting the chain
1451 if (elem_count < 1) {
1452 printk(KERN_ERR "Invalid buffer size\n");
1456 /* Check for input params */
1457 if (unlikely((chain_id < 0
1458 || chain_id >= dma_lch_count))) {
1459 printk(KERN_ERR "Invalid chain id\n");
1463 /* Check if the chain exists */
1464 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1465 printk(KERN_ERR "Chain doesn't exist\n");
1469 /* Check if all the channels in chain are in use */
1470 if (OMAP_DMA_CHAIN_QFULL(chain_id))
1473 /* Frame count may be negative in case of indexed transfers */
1474 channels = dma_linked_lch[chain_id].linked_dmach_q;
1476 /* Get a free channel */
1477 lch = channels[dma_linked_lch[chain_id].q_tail];
1479 /* Store the callback data */
1480 dma_chan[lch].data = callbk_data;
1482 /* Increment the q_tail */
1483 OMAP_DMA_CHAIN_INCQTAIL(chain_id);
1485 /* Set the params to the free channel */
1487 p->dma_write(src_start, CSSA, lch);
1488 if (dest_start != 0)
1489 p->dma_write(dest_start, CDSA, lch);
1491 /* Write the buffer size */
1492 p->dma_write(elem_count, CEN, lch);
1493 p->dma_write(frame_count, CFN, lch);
1496 * If the chain is dynamically linked,
1497 * then we may have to start the chain if its not active
1499 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
1502 * In Dynamic chain, if the chain is not started,
1505 if (dma_linked_lch[chain_id].chain_state ==
1506 DMA_CHAIN_NOTSTARTED) {
1507 /* Enable the link in previous channel */
1508 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1510 enable_lnk(dma_chan[lch].prev_linked_ch);
1511 dma_chan[lch].state = DMA_CH_QUEUED;
1515 * Chain is already started, make sure its active,
1516 * if not then start the chain
1521 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1523 enable_lnk(dma_chan[lch].prev_linked_ch);
1524 dma_chan[lch].state = DMA_CH_QUEUED;
1526 if (0 == ((1 << 7) & p->dma_read(
1527 CCR, dma_chan[lch].prev_linked_ch))) {
1528 disable_lnk(dma_chan[lch].
1530 pr_debug("\n prev ch is stopped\n");
1535 else if (dma_chan[dma_chan[lch].prev_linked_ch].state
1537 enable_lnk(dma_chan[lch].prev_linked_ch);
1538 dma_chan[lch].state = DMA_CH_QUEUED;
1541 omap_enable_channel_irq(lch);
1543 l = p->dma_read(CCR, lch);
1545 if ((0 == (l & (1 << 24))))
1549 if (start_dma == 1) {
1550 if (0 == (l & (1 << 7))) {
1552 dma_chan[lch].state = DMA_CH_STARTED;
1553 pr_debug("starting %d\n", lch);
1554 p->dma_write(l, CCR, lch);
1558 if (0 == (l & (1 << 7)))
1559 p->dma_write(l, CCR, lch);
1561 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1567 EXPORT_SYMBOL(omap_dma_chain_a_transfer);
1570 * @brief omap_start_dma_chain_transfers - Start the chain
1574 * @return - Success : 0
1575 * Failure : -EINVAL/-EBUSY
1577 int omap_start_dma_chain_transfers(int chain_id)
1582 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1583 printk(KERN_ERR "Invalid chain id\n");
1587 channels = dma_linked_lch[chain_id].linked_dmach_q;
1589 if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) {
1590 printk(KERN_ERR "Chain is already started\n");
1594 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) {
1595 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked;
1597 enable_lnk(channels[i]);
1598 omap_enable_channel_irq(channels[i]);
1601 omap_enable_channel_irq(channels[0]);
1604 l = p->dma_read(CCR, channels[0]);
1606 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
1607 dma_chan[channels[0]].state = DMA_CH_STARTED;
1609 if ((0 == (l & (1 << 24))))
1613 p->dma_write(l, CCR, channels[0]);
1615 dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
1619 EXPORT_SYMBOL(omap_start_dma_chain_transfers);
1622 * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
1626 * @return - Success : 0
1629 int omap_stop_dma_chain_transfers(int chain_id)
1635 /* Check for input params */
1636 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1637 printk(KERN_ERR "Invalid chain id\n");
1641 /* Check if the chain exists */
1642 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1643 printk(KERN_ERR "Chain doesn't exists\n");
1646 channels = dma_linked_lch[chain_id].linked_dmach_q;
1648 if (IS_DMA_ERRATA(DMA_ERRATA_i88)) {
1649 sys_cf = p->dma_read(OCP_SYSCONFIG, 0);
1651 /* Middle mode reg set no Standby */
1652 l &= ~((1 << 12)|(1 << 13));
1653 p->dma_write(l, OCP_SYSCONFIG, 0);
1656 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1658 /* Stop the Channel transmission */
1659 l = p->dma_read(CCR, channels[i]);
1661 p->dma_write(l, CCR, channels[i]);
1663 /* Disable the link in all the channels */
1664 disable_lnk(channels[i]);
1665 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1668 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1670 /* Reset the Queue pointers */
1671 OMAP_DMA_CHAIN_QINIT(chain_id);
1673 if (IS_DMA_ERRATA(DMA_ERRATA_i88))
1674 p->dma_write(sys_cf, OCP_SYSCONFIG, 0);
1678 EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
1680 /* Get the index of the ongoing DMA in chain */
1682 * @brief omap_get_dma_chain_index - Get the element and frame index
1683 * of the ongoing DMA in chain
1686 * @param ei - Element index
1687 * @param fi - Frame index
1689 * @return - Success : 0
1692 int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
1697 /* Check for input params */
1698 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1699 printk(KERN_ERR "Invalid chain id\n");
1703 /* Check if the chain exists */
1704 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1705 printk(KERN_ERR "Chain doesn't exists\n");
1711 channels = dma_linked_lch[chain_id].linked_dmach_q;
1713 /* Get the current channel */
1714 lch = channels[dma_linked_lch[chain_id].q_head];
1716 *ei = p->dma_read(CCEN, lch);
1717 *fi = p->dma_read(CCFN, lch);
1721 EXPORT_SYMBOL(omap_get_dma_chain_index);
1724 * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
1725 * ongoing DMA in chain
1729 * @return - Success : Destination position
1732 int omap_get_dma_chain_dst_pos(int chain_id)
1737 /* Check for input params */
1738 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1739 printk(KERN_ERR "Invalid chain id\n");
1743 /* Check if the chain exists */
1744 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1745 printk(KERN_ERR "Chain doesn't exists\n");
1749 channels = dma_linked_lch[chain_id].linked_dmach_q;
1751 /* Get the current channel */
1752 lch = channels[dma_linked_lch[chain_id].q_head];
1754 return p->dma_read(CDAC, lch);
1756 EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
1759 * @brief omap_get_dma_chain_src_pos - Get the source position
1760 * of the ongoing DMA in chain
1763 * @return - Success : Destination position
1766 int omap_get_dma_chain_src_pos(int chain_id)
1771 /* Check for input params */
1772 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1773 printk(KERN_ERR "Invalid chain id\n");
1777 /* Check if the chain exists */
1778 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1779 printk(KERN_ERR "Chain doesn't exists\n");
1783 channels = dma_linked_lch[chain_id].linked_dmach_q;
1785 /* Get the current channel */
1786 lch = channels[dma_linked_lch[chain_id].q_head];
1788 return p->dma_read(CSAC, lch);
1790 EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
1791 #endif /* ifndef CONFIG_ARCH_OMAP1 */
1793 /*----------------------------------------------------------------------------*/
1795 #ifdef CONFIG_ARCH_OMAP1
1797 static int omap1_dma_handle_ch(int ch)
1801 if (enable_1510_mode && ch >= 6) {
1802 csr = dma_chan[ch].saved_csr;
1803 dma_chan[ch].saved_csr = 0;
1805 csr = p->dma_read(CSR, ch);
1806 if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
1807 dma_chan[ch + 6].saved_csr = csr >> 7;
1810 if ((csr & 0x3f) == 0)
1812 if (unlikely(dma_chan[ch].dev_id == -1)) {
1813 printk(KERN_WARNING "Spurious interrupt from DMA channel "
1814 "%d (CSR %04x)\n", ch, csr);
1817 if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
1818 printk(KERN_WARNING "DMA timeout with device %d\n",
1819 dma_chan[ch].dev_id);
1820 if (unlikely(csr & OMAP_DMA_DROP_IRQ))
1821 printk(KERN_WARNING "DMA synchronization event drop occurred "
1822 "with device %d\n", dma_chan[ch].dev_id);
1823 if (likely(csr & OMAP_DMA_BLOCK_IRQ))
1824 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1825 if (likely(dma_chan[ch].callback != NULL))
1826 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
1831 static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
1833 int ch = ((int) dev_id) - 1;
1837 int handled_now = 0;
1839 handled_now += omap1_dma_handle_ch(ch);
1840 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
1841 handled_now += omap1_dma_handle_ch(ch + 6);
1844 handled += handled_now;
1847 return handled ? IRQ_HANDLED : IRQ_NONE;
1851 #define omap1_dma_irq_handler NULL
1854 #ifdef CONFIG_ARCH_OMAP2PLUS
1856 static int omap2_dma_handle_ch(int ch)
1858 u32 status = p->dma_read(CSR, ch);
1861 if (printk_ratelimit())
1862 printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",
1864 p->dma_write(1 << ch, IRQSTATUS_L0, ch);
1867 if (unlikely(dma_chan[ch].dev_id == -1)) {
1868 if (printk_ratelimit())
1869 printk(KERN_WARNING "IRQ %04x for non-allocated DMA"
1870 "channel %d\n", status, ch);
1873 if (unlikely(status & OMAP_DMA_DROP_IRQ))
1875 "DMA synchronization event drop occurred with device "
1876 "%d\n", dma_chan[ch].dev_id);
1877 if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
1878 printk(KERN_INFO "DMA transaction error with device %d\n",
1879 dma_chan[ch].dev_id);
1880 if (IS_DMA_ERRATA(DMA_ERRATA_i378)) {
1883 ccr = p->dma_read(CCR, ch);
1884 ccr &= ~OMAP_DMA_CCR_EN;
1885 p->dma_write(ccr, CCR, ch);
1886 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1889 if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
1890 printk(KERN_INFO "DMA secure error with device %d\n",
1891 dma_chan[ch].dev_id);
1892 if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
1893 printk(KERN_INFO "DMA misaligned error with device %d\n",
1894 dma_chan[ch].dev_id);
1896 p->dma_write(status, CSR, ch);
1897 p->dma_write(1 << ch, IRQSTATUS_L0, ch);
1898 /* read back the register to flush the write */
1899 p->dma_read(IRQSTATUS_L0, ch);
1901 /* If the ch is not chained then chain_id will be -1 */
1902 if (dma_chan[ch].chain_id != -1) {
1903 int chain_id = dma_chan[ch].chain_id;
1904 dma_chan[ch].state = DMA_CH_NOTSTARTED;
1905 if (p->dma_read(CLNK_CTRL, ch) & (1 << 15))
1906 dma_chan[dma_chan[ch].next_linked_ch].state =
1908 if (dma_linked_lch[chain_id].chain_mode ==
1909 OMAP_DMA_DYNAMIC_CHAIN)
1912 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1913 OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1915 status = p->dma_read(CSR, ch);
1916 p->dma_write(status, CSR, ch);
1919 if (likely(dma_chan[ch].callback != NULL))
1920 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
1925 /* STATUS register count is from 1-32 while our is 0-31 */
1926 static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
1928 u32 val, enable_reg;
1931 val = p->dma_read(IRQSTATUS_L0, 0);
1933 if (printk_ratelimit())
1934 printk(KERN_WARNING "Spurious DMA IRQ\n");
1937 enable_reg = p->dma_read(IRQENABLE_L0, 0);
1938 val &= enable_reg; /* Dispatch only relevant interrupts */
1939 for (i = 0; i < dma_lch_count && val != 0; i++) {
1941 omap2_dma_handle_ch(i);
1948 static struct irqaction omap24xx_dma_irq = {
1950 .handler = omap2_dma_irq_handler,
1951 .flags = IRQF_DISABLED
1955 static struct irqaction omap24xx_dma_irq;
1958 /*----------------------------------------------------------------------------*/
1960 void omap_dma_global_context_save(void)
1962 omap_dma_global_context.dma_irqenable_l0 =
1963 p->dma_read(IRQENABLE_L0, 0);
1964 omap_dma_global_context.dma_ocp_sysconfig =
1965 p->dma_read(OCP_SYSCONFIG, 0);
1966 omap_dma_global_context.dma_gcr = p->dma_read(GCR, 0);
1969 void omap_dma_global_context_restore(void)
1973 p->dma_write(omap_dma_global_context.dma_gcr, GCR, 0);
1974 p->dma_write(omap_dma_global_context.dma_ocp_sysconfig,
1976 p->dma_write(omap_dma_global_context.dma_irqenable_l0,
1979 if (IS_DMA_ERRATA(DMA_ROMCODE_BUG))
1980 p->dma_write(0x3 , IRQSTATUS_L0, 0);
1982 for (ch = 0; ch < dma_chan_count; ch++)
1983 if (dma_chan[ch].dev_id != -1)
1987 static int __devinit omap_system_dma_probe(struct platform_device *pdev)
1994 p = pdev->dev.platform_data;
1996 dev_err(&pdev->dev, "%s: System DMA initialized without"
1997 "platform data\n", __func__);
2004 if ((d->dev_caps & RESERVE_CHANNEL) && omap_dma_reserve_channels
2005 && (omap_dma_reserve_channels <= dma_lch_count))
2006 d->lch_count = omap_dma_reserve_channels;
2008 dma_lch_count = d->lch_count;
2009 dma_chan_count = dma_lch_count;
2011 enable_1510_mode = d->dev_caps & ENABLE_1510_MODE;
2013 if (cpu_class_is_omap2()) {
2014 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
2015 dma_lch_count, GFP_KERNEL);
2016 if (!dma_linked_lch) {
2018 goto exit_dma_lch_fail;
2022 spin_lock_init(&dma_chan_lock);
2023 for (ch = 0; ch < dma_chan_count; ch++) {
2025 if (cpu_class_is_omap2())
2026 omap2_disable_irq_lch(ch);
2028 dma_chan[ch].dev_id = -1;
2029 dma_chan[ch].next_lch = -1;
2031 if (ch >= 6 && enable_1510_mode)
2034 if (cpu_class_is_omap1()) {
2036 * request_irq() doesn't like dev_id (ie. ch) being
2037 * zero, so we have to kludge around this.
2039 sprintf(&irq_name[0], "%d", ch);
2040 dma_irq = platform_get_irq_byname(pdev, irq_name);
2044 goto exit_dma_irq_fail;
2047 /* INT_DMA_LCD is handled in lcd_dma.c */
2048 if (dma_irq == INT_DMA_LCD)
2051 ret = request_irq(dma_irq,
2052 omap1_dma_irq_handler, 0, "DMA",
2055 goto exit_dma_irq_fail;
2059 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx())
2060 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
2061 DMA_DEFAULT_FIFO_DEPTH, 0);
2063 if (cpu_class_is_omap2()) {
2064 strcpy(irq_name, "0");
2065 dma_irq = platform_get_irq_byname(pdev, irq_name);
2067 dev_err(&pdev->dev, "failed: request IRQ %d", dma_irq);
2068 goto exit_dma_lch_fail;
2070 ret = setup_irq(dma_irq, &omap24xx_dma_irq);
2072 dev_err(&pdev->dev, "set_up failed for IRQ %d"
2073 "for DMA (error %d)\n", dma_irq, ret);
2074 goto exit_dma_lch_fail;
2078 /* reserve dma channels 0 and 1 in high security devices */
2079 if (cpu_is_omap34xx() &&
2080 (omap_type() != OMAP2_DEVICE_TYPE_GP)) {
2081 printk(KERN_INFO "Reserving DMA channels 0 and 1 for "
2083 dma_chan[0].dev_id = 0;
2084 dma_chan[1].dev_id = 1;
2090 dev_err(&pdev->dev, "unable to request IRQ %d"
2091 "for DMA (error %d)\n", dma_irq, ret);
2092 for (irq_rel = 0; irq_rel < ch; irq_rel++) {
2093 dma_irq = platform_get_irq(pdev, irq_rel);
2094 free_irq(dma_irq, (void *)(irq_rel + 1));
2104 static int __devexit omap_system_dma_remove(struct platform_device *pdev)
2108 if (cpu_class_is_omap2()) {
2110 strcpy(irq_name, "0");
2111 dma_irq = platform_get_irq_byname(pdev, irq_name);
2112 remove_irq(dma_irq, &omap24xx_dma_irq);
2115 for ( ; irq_rel < dma_chan_count; irq_rel++) {
2116 dma_irq = platform_get_irq(pdev, irq_rel);
2117 free_irq(dma_irq, (void *)(irq_rel + 1));
2126 static struct platform_driver omap_system_dma_driver = {
2127 .probe = omap_system_dma_probe,
2128 .remove = omap_system_dma_remove,
2130 .name = "omap_dma_system"
2134 static int __init omap_system_dma_init(void)
2136 return platform_driver_register(&omap_system_dma_driver);
2138 arch_initcall(omap_system_dma_init);
2140 static void __exit omap_system_dma_exit(void)
2142 platform_driver_unregister(&omap_system_dma_driver);
2145 MODULE_DESCRIPTION("OMAP SYSTEM DMA DRIVER");
2146 MODULE_LICENSE("GPL");
2147 MODULE_ALIAS("platform:" DRIVER_NAME);
2148 MODULE_AUTHOR("Texas Instruments Inc");
2151 * Reserve the omap SDMA channels using cmdline bootarg
2152 * "omap_dma_reserve_ch=". The valid range is 1 to 32
2154 static int __init omap_dma_cmdline_reserve_ch(char *str)
2156 if (get_option(&str, &omap_dma_reserve_channels) != 1)
2157 omap_dma_reserve_channels = 0;
2161 __setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch);