2 * Copyright (C) ST-Ericsson SA 2007-2010
3 * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
4 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
5 * License terms: GNU General Public License (GPL) version 2
12 #include <linux/dmaengine.h>
13 #include <linux/workqueue.h>
14 #include <linux/interrupt.h>
15 #include <linux/dmaengine.h>
17 /* dev types for memcpy */
18 #define STEDMA40_DEV_DST_MEMORY (-1)
19 #define STEDMA40_DEV_SRC_MEMORY (-1)
22 * Description of bitfields of channel_type variable is available in
27 STEDMA40_MODE_LOGICAL = 0,
28 STEDMA40_MODE_PHYSICAL,
29 STEDMA40_MODE_OPERATION,
32 enum stedma40_mode_opt {
33 STEDMA40_PCHAN_BASIC_MODE = 0,
34 STEDMA40_LCHAN_SRC_LOG_DST_LOG = 0,
35 STEDMA40_PCHAN_MODULO_MODE,
36 STEDMA40_PCHAN_DOUBLE_DST_MODE,
37 STEDMA40_LCHAN_SRC_PHY_DST_LOG,
38 STEDMA40_LCHAN_SRC_LOG_DST_PHY,
41 /* End of channel_type configuration */
43 #define STEDMA40_ESIZE_8_BIT 0x0
44 #define STEDMA40_ESIZE_16_BIT 0x1
45 #define STEDMA40_ESIZE_32_BIT 0x2
46 #define STEDMA40_ESIZE_64_BIT 0x3
48 /* The value 4 indicates that PEN-reg shall be set to 0 */
49 #define STEDMA40_PSIZE_PHY_1 0x4
50 #define STEDMA40_PSIZE_PHY_2 0x0
51 #define STEDMA40_PSIZE_PHY_4 0x1
52 #define STEDMA40_PSIZE_PHY_8 0x2
53 #define STEDMA40_PSIZE_PHY_16 0x3
56 * The number of elements differ in logical and
59 #define STEDMA40_PSIZE_LOG_1 STEDMA40_PSIZE_PHY_2
60 #define STEDMA40_PSIZE_LOG_4 STEDMA40_PSIZE_PHY_4
61 #define STEDMA40_PSIZE_LOG_8 STEDMA40_PSIZE_PHY_8
62 #define STEDMA40_PSIZE_LOG_16 STEDMA40_PSIZE_PHY_16
64 /* Maximum number of possible physical channels */
65 #define STEDMA40_MAX_PHYS 32
67 enum stedma40_flow_ctrl {
68 STEDMA40_NO_FLOW_CTRL,
72 enum stedma40_endianess {
73 STEDMA40_LITTLE_ENDIAN,
77 enum stedma40_periph_data_width {
78 STEDMA40_BYTE_WIDTH = STEDMA40_ESIZE_8_BIT,
79 STEDMA40_HALFWORD_WIDTH = STEDMA40_ESIZE_16_BIT,
80 STEDMA40_WORD_WIDTH = STEDMA40_ESIZE_32_BIT,
81 STEDMA40_DOUBLEWORD_WIDTH = STEDMA40_ESIZE_64_BIT
84 enum stedma40_xfer_dir {
85 STEDMA40_MEM_TO_MEM = 1,
86 STEDMA40_MEM_TO_PERIPH,
87 STEDMA40_PERIPH_TO_MEM,
88 STEDMA40_PERIPH_TO_PERIPH
93 * struct stedma40_chan_cfg - dst/src channel configuration
95 * @endianess: Endianess of the src/dst hardware
96 * @data_width: Data width of the src/dst hardware
98 * @flow_ctrl: Flow control on/off.
100 struct stedma40_half_channel_info {
101 enum stedma40_endianess endianess;
102 enum stedma40_periph_data_width data_width;
104 enum stedma40_flow_ctrl flow_ctrl;
108 * struct stedma40_chan_cfg - Structure to be filled by client drivers.
110 * @dir: MEM 2 MEM, PERIPH 2 MEM , MEM 2 PERIPH, PERIPH 2 PERIPH
111 * @channel_type: priority, mode, mode options and interrupt configuration.
112 * @high_priority: true if high-priority
113 * @mode: channel mode: physical, logical, or operation
114 * @mode_opt: options for the chosen channel mode
115 * @src_dev_type: Src device type
116 * @dst_dev_type: Dst device type
117 * @src_info: Parameters for dst half channel
118 * @dst_info: Parameters for dst half channel
121 * This structure has to be filled by the client drivers.
122 * It is recommended to do all dma configurations for clients in the machine.
125 struct stedma40_chan_cfg {
126 enum stedma40_xfer_dir dir;
127 unsigned int channel_type;
129 enum stedma40_mode mode;
130 enum stedma40_mode_opt mode_opt;
133 struct stedma40_half_channel_info src_info;
134 struct stedma40_half_channel_info dst_info;
138 * struct stedma40_platform_data - Configuration struct for the dma device.
140 * @dev_len: length of dev_tx and dev_rx
141 * @dev_tx: mapping between destination event line and io address
142 * @dev_rx: mapping between source event line and io address
143 * @memcpy: list of memcpy event lines
144 * @memcpy_len: length of memcpy
145 * @memcpy_conf_phy: default configuration of physical channel memcpy
146 * @memcpy_conf_log: default configuration of logical channel memcpy
147 * @disabled_channels: A vector, ending with -1, that marks physical channels
148 * that are for different reasons not available for the driver.
150 struct stedma40_platform_data {
152 const dma_addr_t *dev_tx;
153 const dma_addr_t *dev_rx;
156 struct stedma40_chan_cfg *memcpy_conf_phy;
157 struct stedma40_chan_cfg *memcpy_conf_log;
158 int disabled_channels[STEDMA40_MAX_PHYS];
161 #ifdef CONFIG_STE_DMA40
164 * stedma40_filter() - Provides stedma40_chan_cfg to the
165 * ste_dma40 dma driver via the dmaengine framework.
166 * does some checking of what's provided.
168 * Never directly called by client. It used by dmaengine.
169 * @chan: dmaengine handle.
170 * @data: Must be of type: struct stedma40_chan_cfg and is
171 * the configuration of the framework.
176 bool stedma40_filter(struct dma_chan *chan, void *data);
179 * stedma40_memcpy_sg() - extension of the dma framework, memcpy to/from
180 * scattergatter lists.
182 * @chan: dmaengine handle
183 * @sgl_dst: Destination scatter list
184 * @sgl_src: Source scatter list
185 * @sgl_len: The length of each scatterlist. Both lists must be of equal length
186 * and each element must match the corresponding element in the other scatter
188 * @flags: is actually enum dma_ctrl_flags. See dmaengine.h
191 struct dma_async_tx_descriptor *stedma40_memcpy_sg(struct dma_chan *chan,
192 struct scatterlist *sgl_dst,
193 struct scatterlist *sgl_src,
194 unsigned int sgl_len,
195 unsigned long flags);
198 * stedma40_slave_mem() - Transfers a raw data buffer to or from a slave
201 * @chan: dmaengine handle
202 * @addr: source or destination physicall address.
203 * @size: bytes to transfer
204 * @direction: direction of transfer
205 * @flags: is actually enum dma_ctrl_flags. See dmaengine.h
209 dma_async_tx_descriptor *stedma40_slave_mem(struct dma_chan *chan,
212 enum dma_data_direction direction,
215 struct scatterlist sg;
216 sg_init_table(&sg, 1);
217 sg.dma_address = addr;
220 return chan->device->device_prep_slave_sg(chan, &sg, 1,
225 static inline bool stedma40_filter(struct dma_chan *chan, void *data)
231 dma_async_tx_descriptor *stedma40_slave_mem(struct dma_chan *chan,
234 enum dma_data_direction direction,