2 * Copyright (C)2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/init.h>
15 #include <linux/device.h>
16 #include <linux/errno.h>
19 #include <asm/mach/irq.h>
21 #include <mach/hardware.h>
22 #include <mach/common.h>
24 #include "irq-common.h"
27 *****************************************
29 *****************************************
32 #define TZIC_INTCNTL 0x0000 /* Control register */
33 #define TZIC_INTTYPE 0x0004 /* Controller Type register */
34 #define TZIC_IMPID 0x0008 /* Distributor Implementer Identification */
35 #define TZIC_PRIOMASK 0x000C /* Priority Mask Reg */
36 #define TZIC_SYNCCTRL 0x0010 /* Synchronizer Control register */
37 #define TZIC_DSMINT 0x0014 /* DSM interrupt Holdoffregister */
38 #define TZIC_INTSEC0(i) (0x0080 + ((i) << 2)) /* Interrupt Security Reg 0 */
39 #define TZIC_ENSET0(i) (0x0100 + ((i) << 2)) /* Enable Set Reg 0 */
40 #define TZIC_ENCLEAR0(i) (0x0180 + ((i) << 2)) /* Enable Clear Reg 0 */
41 #define TZIC_SRCSET0 0x0200 /* Source Set Register 0 */
42 #define TZIC_SRCCLAR0 0x0280 /* Source Clear Register 0 */
43 #define TZIC_PRIORITY0 0x0400 /* Priority Register 0 */
44 #define TZIC_PND0 0x0D00 /* Pending Register 0 */
45 #define TZIC_HIPND0 0x0D80 /* High Priority Pending Register */
46 #define TZIC_WAKEUP0(i) (0x0E00 + ((i) << 2)) /* Wakeup Config Register */
47 #define TZIC_SWINT 0x0F00 /* Software Interrupt Rigger Register */
48 #define TZIC_ID0 0x0FD0 /* Indentification Register 0 */
50 void __iomem *tzic_base; /* Used as irq controller base in entry-macro.S */
52 #define TZIC_NUM_IRQS 128
55 static int tzic_set_irq_fiq(unsigned int irq, unsigned int type)
57 unsigned int index, mask, value;
60 if (unlikely(index >= 4))
62 mask = 1U << (irq & 0x1F);
64 value = __raw_readl(tzic_base + TZIC_INTSEC0(index)) | mask;
67 __raw_writel(value, tzic_base + TZIC_INTSEC0(index));
74 * tzic_mask_irq() - Disable interrupt source "d" in the TZIC
76 * @param d interrupt source
78 static void tzic_mask_irq(struct irq_data *d)
84 __raw_writel(1 << off, tzic_base + TZIC_ENCLEAR0(index));
88 * tzic_unmask_irq() - Enable interrupt source "d" in the TZIC
90 * @param d interrupt source
92 static void tzic_unmask_irq(struct irq_data *d)
98 __raw_writel(1 << off, tzic_base + TZIC_ENSET0(index));
101 static unsigned int wakeup_intr[4];
104 * tzic_set_wake_irq() - Set interrupt source "d" in the TZIC as a wake-up source.
106 * @param d interrupt source
107 * @param enable enable as wake-up if equal to non-zero
108 * disble as wake-up if equal to zero
110 * @return This function returns 0 on success.
112 static int tzic_set_wake_irq(struct irq_data *d, unsigned int enable)
114 unsigned int index, off;
123 wakeup_intr[index] |= (1 << off);
125 wakeup_intr[index] &= ~(1 << off);
130 static struct mxc_irq_chip mxc_tzic_chip = {
133 .irq_ack = tzic_mask_irq,
134 .irq_mask = tzic_mask_irq,
135 .irq_unmask = tzic_unmask_irq,
136 .irq_set_wake = tzic_set_wake_irq,
139 .set_irq_fiq = tzic_set_irq_fiq,
144 * This function initializes the TZIC hardware and disables all the
145 * interrupts. It registers the interrupt enable and disable functions
146 * to the kernel for each interrupt source.
148 void __init tzic_init_irq(void __iomem *irqbase)
153 /* put the TZIC into the reset value with
154 * all interrupts disabled
156 i = __raw_readl(tzic_base + TZIC_INTCNTL);
158 __raw_writel(0x80010001, tzic_base + TZIC_INTCNTL);
159 __raw_writel(0x1f, tzic_base + TZIC_PRIOMASK);
160 __raw_writel(0x02, tzic_base + TZIC_SYNCCTRL);
162 for (i = 0; i < 4; i++)
163 __raw_writel(0xFFFFFFFF, tzic_base + TZIC_INTSEC0(i));
165 /* disable all interrupts */
166 for (i = 0; i < 4; i++)
167 __raw_writel(0xFFFFFFFF, tzic_base + TZIC_ENCLEAR0(i));
169 /* all IRQ no FIQ Warning :: No selection */
171 for (i = 0; i < TZIC_NUM_IRQS; i++) {
172 irq_set_chip_and_handler(i, &mxc_tzic_chip.base,
174 set_irq_flags(i, IRQF_VALID);
182 pr_info("TrustZone Interrupt Controller (TZIC) initialized\n");
186 * tzic_enable_wake() - enable wakeup interrupt
188 * @param is_idle 1 if called in idle loop (ENSET0 register);
189 * 0 to be used when called from low power entry
190 * @return 0 if successful; non-zero otherwise
192 int tzic_enable_wake(int is_idle)
196 __raw_writel(1, tzic_base + TZIC_DSMINT);
197 if (unlikely(__raw_readl(tzic_base + TZIC_DSMINT) == 0))
200 for (i = 0; i < 4; i++) {
201 v = is_idle ? __raw_readl(tzic_base + TZIC_ENSET0(i)) :
203 __raw_writel(v, tzic_base + TZIC_WAKEUP0(i));