2 * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
3 * - Platform specific register memory map
5 * Copyright 2005-2007 Motorola, Inc.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 #ifndef __MACH_MXC91231_H__
18 #define __MACH_MXC91231_H__
23 #define MXC91231_L2CC_BASE_ADDR 0x30000000
24 #define MXC91231_L2CC_SIZE SZ_64K
29 #define MXC91231_AIPS1_BASE_ADDR 0x43F00000
30 #define MXC91231_AIPS1_SIZE SZ_1M
32 #define MXC91231_AIPS1_CTRL_BASE_ADDR MXC91231_AIPS1_BASE_ADDR
33 #define MXC91231_MAX_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x04000)
34 #define MXC91231_EVTMON_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x08000)
35 #define MXC91231_CLKCTL_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x0C000)
36 #define MXC91231_ETB_SLOT4_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x10000)
37 #define MXC91231_ETB_SLOT5_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x14000)
38 #define MXC91231_ECT_CTIO_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x18000)
39 #define MXC91231_I2C_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x80000)
40 #define MXC91231_MU_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x88000)
41 #define MXC91231_UART1_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x90000)
42 #define MXC91231_UART2_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x94000)
43 #define MXC91231_DSM_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x98000)
44 #define MXC91231_OWIRE_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x9C000)
45 #define MXC91231_SSI1_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0xA0000)
46 #define MXC91231_KPP_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0xA8000)
47 #define MXC91231_IOMUX_AP_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0xAC000)
48 #define MXC91231_CTI_AP_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0xB8000)
53 #define MXC91231_AIPS2_BASE_ADDR 0x53F00000
54 #define MXC91231_AIPS2_SIZE SZ_1M
56 #define MXC91231_GEMK_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0x8C000)
57 #define MXC91231_GPT1_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0x90000)
58 #define MXC91231_EPIT1_AP_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0x94000)
59 #define MXC91231_SCC_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xAC000)
60 #define MXC91231_RNGA_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xB0000)
61 #define MXC91231_IPU_CTRL_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xC0000)
62 #define MXC91231_AUDMUX_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xC4000)
63 #define MXC91231_EDIO_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xC8000)
64 #define MXC91231_GPIO1_AP_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xCC000)
65 #define MXC91231_GPIO2_AP_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xD0000)
66 #define MXC91231_SDMA_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xD4000)
67 #define MXC91231_RTC_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xD8000)
68 #define MXC91231_WDOG1_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xDC000)
69 #define MXC91231_PWM_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xE0000)
70 #define MXC91231_GPIO3_AP_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xE4000)
71 #define MXC91231_WDOG2_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xE8000)
72 #define MXC91231_RTIC_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xEC000)
73 #define MXC91231_LPMC_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xF0000)
76 * SPBA global module 0
78 #define MXC91231_SPBA0_BASE_ADDR 0x50000000
79 #define MXC91231_SPBA0_SIZE SZ_1M
81 #define MXC91231_MMC_SDHC1_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x04000)
82 #define MXC91231_MMC_SDHC2_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x08000)
83 #define MXC91231_UART3_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x0C000)
84 #define MXC91231_CSPI2_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x10000)
85 #define MXC91231_SSI2_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x14000)
86 #define MXC91231_SIM_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x18000)
87 #define MXC91231_IIM_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x1C000)
88 #define MXC91231_CTI_SDMA_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x20000)
89 #define MXC91231_USBOTG_CTRL_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x24000)
90 #define MXC91231_USBOTG_DATA_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x28000)
91 #define MXC91231_CSPI1_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x30000)
92 #define MXC91231_SPBA_CTRL_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x3C000)
93 #define MXC91231_IOMUX_COM_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x40000)
94 #define MXC91231_CRM_COM_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x44000)
95 #define MXC91231_CRM_AP_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x48000)
96 #define MXC91231_PLL0_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x4C000)
97 #define MXC91231_PLL1_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x50000)
98 #define MXC91231_PLL2_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x54000)
99 #define MXC91231_GPIO4_SH_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x58000)
100 #define MXC91231_HAC_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x5C000)
101 #define MXC91231_SAHARA_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x5C000)
102 #define MXC91231_PLL3_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x60000)
105 * SPBA global module 1
107 #define MXC91231_SPBA1_BASE_ADDR 0x52000000
108 #define MXC91231_SPBA1_SIZE SZ_1M
110 #define MXC91231_MQSPI_BASE_ADDR (MXC91231_SPBA1_BASE_ADDR + 0x34000)
111 #define MXC91231_EL1T_BASE_ADDR (MXC91231_SPBA1_BASE_ADDR + 0x38000)
114 * Defines for SPBA modules
116 #define MXC91231_SPBA_SDHC1 0x04
117 #define MXC91231_SPBA_SDHC2 0x08
118 #define MXC91231_SPBA_UART3 0x0C
119 #define MXC91231_SPBA_CSPI2 0x10
120 #define MXC91231_SPBA_SSI2 0x14
121 #define MXC91231_SPBA_SIM 0x18
122 #define MXC91231_SPBA_IIM 0x1C
123 #define MXC91231_SPBA_CTI_SDMA 0x20
124 #define MXC91231_SPBA_USBOTG_CTRL_REGS 0x24
125 #define MXC91231_SPBA_USBOTG_DATA_REGS 0x28
126 #define MXC91231_SPBA_CSPI1 0x30
127 #define MXC91231_SPBA_MQSPI 0x34
128 #define MXC91231_SPBA_EL1T 0x38
129 #define MXC91231_SPBA_IOMUX 0x40
130 #define MXC91231_SPBA_CRM_COM 0x44
131 #define MXC91231_SPBA_CRM_AP 0x48
132 #define MXC91231_SPBA_PLL0 0x4C
133 #define MXC91231_SPBA_PLL1 0x50
134 #define MXC91231_SPBA_PLL2 0x54
135 #define MXC91231_SPBA_GPIO4 0x58
136 #define MXC91231_SPBA_SAHARA 0x5C
141 #define MXC91231_ROMP_BASE_ADDR 0x60000000
142 #define MXC91231_ROMP_SIZE SZ_64K
144 #define MXC91231_AVIC_BASE_ADDR 0x68000000
145 #define MXC91231_AVIC_SIZE SZ_64K
148 * NAND, SDRAM, WEIM, M3IF, EMI controllers
150 #define MXC91231_X_MEMC_BASE_ADDR 0xB8000000
151 #define MXC91231_X_MEMC_SIZE SZ_64K
153 #define MXC91231_NFC_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x0000)
154 #define MXC91231_ESDCTL_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x1000)
155 #define MXC91231_WEIM_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x2000)
156 #define MXC91231_M3IF_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x3000)
157 #define MXC91231_EMI_CTL_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x4000)
160 * Memory regions and CS
161 * CPLD is connected on CS4
162 * CS5 is TP1021 or it is not connected
164 #define MXC91231_FB_RAM_BASE_ADDR 0x78000000
165 #define MXC91231_FB_RAM_SIZE SZ_256K
166 #define MXC91231_CSD0_BASE_ADDR 0x80000000
167 #define MXC91231_CSD1_BASE_ADDR 0x90000000
168 #define MXC91231_CS0_BASE_ADDR 0xA0000000
169 #define MXC91231_CS1_BASE_ADDR 0xA8000000
170 #define MXC91231_CS2_BASE_ADDR 0xB0000000
171 #define MXC91231_CS3_BASE_ADDR 0xB2000000
172 #define MXC91231_CS4_BASE_ADDR 0xB4000000
173 #define MXC91231_CS5_BASE_ADDR 0xB6000000
176 * This macro defines the physical to virtual address mapping for all the
177 * peripheral modules. It is used by passing in the physical address as x
178 * and returning the virtual address.
180 #define MXC91231_IO_P2V(x) IMX_IO_P2V(x)
181 #define MXC91231_IO_ADDRESS(x) IOMEM(MXC91231_IO_P2V(x))
186 #define MXC91231_INT_GPIO3 0
187 #define MXC91231_INT_EL1T_CI 1
188 #define MXC91231_INT_EL1T_RFCI 2
189 #define MXC91231_INT_EL1T_RFI 3
190 #define MXC91231_INT_EL1T_MCU 4
191 #define MXC91231_INT_EL1T_IPI 5
192 #define MXC91231_INT_MU_GEN 6
193 #define MXC91231_INT_GPIO4 7
194 #define MXC91231_INT_MMC_SDHC2 8
195 #define MXC91231_INT_MMC_SDHC1 9
196 #define MXC91231_INT_I2C 10
197 #define MXC91231_INT_SSI2 11
198 #define MXC91231_INT_SSI1 12
199 #define MXC91231_INT_CSPI2 13
200 #define MXC91231_INT_CSPI1 14
201 #define MXC91231_INT_RTIC 15
202 #define MXC91231_INT_SAHARA 15
203 #define MXC91231_INT_HAC 15
204 #define MXC91231_INT_UART3_RX 16
205 #define MXC91231_INT_UART3_TX 17
206 #define MXC91231_INT_UART3_MINT 18
207 #define MXC91231_INT_ECT 19
208 #define MXC91231_INT_SIM_IPB 20
209 #define MXC91231_INT_SIM_DATA 21
210 #define MXC91231_INT_RNGA 22
211 #define MXC91231_INT_DSM_AP 23
212 #define MXC91231_INT_KPP 24
213 #define MXC91231_INT_RTC 25
214 #define MXC91231_INT_PWM 26
215 #define MXC91231_INT_GEMK_AP 27
216 #define MXC91231_INT_EPIT 28
217 #define MXC91231_INT_GPT 29
218 #define MXC91231_INT_UART2_RX 30
219 #define MXC91231_INT_UART2_TX 31
220 #define MXC91231_INT_UART2_MINT 32
221 #define MXC91231_INT_NANDFC 33
222 #define MXC91231_INT_SDMA 34
223 #define MXC91231_INT_USB_WAKEUP 35
224 #define MXC91231_INT_USB_SOF 36
225 #define MXC91231_INT_PMU_EVTMON 37
226 #define MXC91231_INT_USB_FUNC 38
227 #define MXC91231_INT_USB_DMA 39
228 #define MXC91231_INT_USB_CTRL 40
229 #define MXC91231_INT_IPU_ERR 41
230 #define MXC91231_INT_IPU_SYN 42
231 #define MXC91231_INT_UART1_RX 43
232 #define MXC91231_INT_UART1_TX 44
233 #define MXC91231_INT_UART1_MINT 45
234 #define MXC91231_INT_IIM 46
235 #define MXC91231_INT_MU_RX_OR 47
236 #define MXC91231_INT_MU_TX_OR 48
237 #define MXC91231_INT_SCC_SCM 49
238 #define MXC91231_INT_SCC_SMN 50
239 #define MXC91231_INT_GPIO2 51
240 #define MXC91231_INT_GPIO1 52
241 #define MXC91231_INT_MQSPI1 53
242 #define MXC91231_INT_MQSPI2 54
243 #define MXC91231_INT_WDOG2 55
244 #define MXC91231_INT_EXT_INT7 56
245 #define MXC91231_INT_EXT_INT6 57
246 #define MXC91231_INT_EXT_INT5 58
247 #define MXC91231_INT_EXT_INT4 59
248 #define MXC91231_INT_EXT_INT3 60
249 #define MXC91231_INT_EXT_INT2 61
250 #define MXC91231_INT_EXT_INT1 62
251 #define MXC91231_INT_EXT_INT0 63
253 #define MXC91231_MAX_INT_LINES 63
254 #define MXC91231_MAX_EXT_LINES 8
256 #endif /* __MACH_MXC91231_H__ */