2 * linux/arch/arm/mm/proc-v7.S
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This is the "shell" of the ARMv7 processor support.
12 #include <linux/init.h>
13 #include <linux/linkage.h>
14 #include <asm/assembler.h>
15 #include <asm/asm-offsets.h>
16 #include <asm/hwcap.h>
17 #include <asm/pgtable-hwdef.h>
18 #include <asm/pgtable.h>
20 #include "proc-macros.S"
22 #ifdef CONFIG_ARM_LPAE
23 #include "proc-v7-3level.S"
25 #include "proc-v7-2level.S"
28 ENTRY(cpu_v7_proc_init)
30 ENDPROC(cpu_v7_proc_init)
32 ENTRY(cpu_v7_proc_fin)
33 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
34 bic r0, r0, #0x1000 @ ...i............
35 bic r0, r0, #0x0006 @ .............ca.
36 mcr p15, 0, r0, c1, c0, 0 @ disable caches
38 ENDPROC(cpu_v7_proc_fin)
43 * Perform a soft reset of the system. Put the CPU into the
44 * same state as it would be if it had been reset, and branch
45 * to what would be the reset vector.
47 * - loc - location to jump to for soft reset
49 * This code must be executed using a flat identity mapping with
53 .pushsection .idmap.text, "ax"
55 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
56 bic r1, r1, #0x1 @ ...............m
57 THUMB( bic r1, r1, #1 << 30 ) @ SCTLR.TE (Thumb exceptions)
58 mcr p15, 0, r1, c1, c0, 0 @ disable MMU
67 * Idle the processor (eg, wait for interrupt).
69 * IRQs are already disabled.
72 dsb @ WFI may enter a low-power mode
75 ENDPROC(cpu_v7_do_idle)
77 ENTRY(cpu_v7_dcache_clean_area)
78 #ifndef TLB_CAN_READ_FROM_L1_CACHE
79 dcache_line_size r2, r3
80 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
87 ENDPROC(cpu_v7_dcache_clean_area)
89 string cpu_v7_name, "ARMv7 Processor"
92 /* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
93 .globl cpu_v7_suspend_size
94 .equ cpu_v7_suspend_size, 4 * 8
95 #ifdef CONFIG_ARM_CPU_SUSPEND
96 ENTRY(cpu_v7_do_suspend)
97 stmfd sp!, {r4 - r10, lr}
98 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
99 mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID
101 mrc p15, 0, r6, c3, c0, 0 @ Domain ID
102 mrc p15, 0, r7, c2, c0, 1 @ TTB 1
103 mrc p15, 0, r11, c2, c0, 2 @ TTB control register
104 mrc p15, 0, r8, c1, c0, 0 @ Control register
105 mrc p15, 0, r9, c1, c0, 1 @ Auxiliary control register
106 mrc p15, 0, r10, c1, c0, 2 @ Co-processor access control
108 ldmfd sp!, {r4 - r10, pc}
109 ENDPROC(cpu_v7_do_suspend)
111 ENTRY(cpu_v7_do_resume)
113 mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs
114 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
115 mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID
117 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
118 mcr p15, 0, r5, c13, c0, 3 @ User r/o thread ID
120 mcr p15, 0, r6, c3, c0, 0 @ Domain ID
121 #ifndef CONFIG_ARM_LPAE
122 ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP)
123 ALT_UP(orr r1, r1, #TTB_FLAGS_UP)
125 mcr p15, 0, r1, c2, c0, 0 @ TTB 0
126 mcr p15, 0, r7, c2, c0, 1 @ TTB 1
127 mcr p15, 0, r11, c2, c0, 2 @ TTB control register
128 mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register
129 teq r4, r9 @ Is it already set?
130 mcrne p15, 0, r9, c1, c0, 1 @ No, so write it
131 mcr p15, 0, r10, c1, c0, 2 @ Co-processor access control
134 mcr p15, 0, r4, c10, c2, 0 @ write PRRR
135 mcr p15, 0, r5, c10, c2, 1 @ write NMRR
138 mov r0, r8 @ control register
140 ENDPROC(cpu_v7_do_resume)
148 * Initialise TLB, Caches, and MMU state ready to switch the MMU
149 * on. Return in r0 the new CP15 C1 control register setting.
151 * This should be able to cover all ARMv7 cores.
153 * It is assumed that:
154 * - cache type register is implemented
158 mov r10, #(1 << 0) @ TLB ops broadcasting
164 ALT_SMP(mrc p15, 0, r0, c1, c0, 1)
165 ALT_UP(mov r0, #(1 << 6)) @ fake it for UP
166 tst r0, #(1 << 6) @ SMP/nAMP mode enabled?
167 orreq r0, r0, #(1 << 6) @ Enable SMP/nAMP mode
168 orreq r0, r0, r10 @ Enable CPU-specific SMP bits
169 mcreq p15, 0, r0, c1, c0, 1
172 adr r12, __v7_setup_stack @ the local stack
173 stmia r12, {r0-r5, r7, r9, r11, lr}
174 bl v7_flush_dcache_all
175 ldmia r12, {r0-r5, r7, r9, r11, lr}
177 mrc p15, 0, r0, c0, c0, 0 @ read main ID register
178 and r10, r0, #0xff000000 @ ARM?
181 and r5, r0, #0x00f00000 @ variant
182 and r6, r0, #0x0000000f @ revision
183 orr r6, r6, r5, lsr #20-4 @ combine variant and revision
184 ubfx r0, r0, #4, #12 @ primary part number
186 /* Cortex-A8 Errata */
187 ldr r10, =0x00000c08 @ Cortex-A8 primary part number
190 #ifdef CONFIG_ARM_ERRATA_430973
191 teq r5, #0x00100000 @ only present in r1p*
192 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
193 orreq r10, r10, #(1 << 6) @ set IBE to 1
194 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
196 #ifdef CONFIG_ARM_ERRATA_458693
197 teq r6, #0x20 @ only present in r2p0
198 mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
199 orreq r10, r10, #(1 << 5) @ set L1NEON to 1
200 orreq r10, r10, #(1 << 9) @ set PLDNOP to 1
201 mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
203 #ifdef CONFIG_ARM_ERRATA_460075
204 teq r6, #0x20 @ only present in r2p0
205 mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register
207 orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit
208 mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register
212 /* Cortex-A9 Errata */
213 2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number
216 #ifdef CONFIG_ARM_ERRATA_742230
217 cmp r6, #0x22 @ only present up to r2p2
218 mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register
219 orrle r10, r10, #1 << 4 @ set bit #4
220 mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register
222 #ifdef CONFIG_ARM_ERRATA_742231
223 teq r6, #0x20 @ present in r2p0
224 teqne r6, #0x21 @ present in r2p1
225 teqne r6, #0x22 @ present in r2p2
226 mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
227 orreq r10, r10, #1 << 12 @ set bit #12
228 orreq r10, r10, #1 << 22 @ set bit #22
229 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
231 #ifdef CONFIG_ARM_ERRATA_743622
232 teq r5, #0x00200000 @ only present in r2p*
233 mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
234 orreq r10, r10, #1 << 6 @ set bit #6
235 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
237 #if defined(CONFIG_ARM_ERRATA_751472) && defined(CONFIG_SMP)
238 ALT_SMP(cmp r6, #0x30) @ present prior to r3p0
240 mrclt p15, 0, r10, c15, c0, 1 @ read diagnostic register
241 orrlt r10, r10, #1 << 11 @ set bit #11
242 mcrlt p15, 0, r10, c15, c0, 1 @ write diagnostic register
247 mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
249 mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
250 v7_ttb_setup r10, r4, r8, r5 @ TTBCR, TTBRx setup
253 mcr p15, 0, r5, c10, c2, 0 @ write PRRR
254 mcr p15, 0, r6, c10, c2, 1 @ write NMRR
256 dsb @ Complete invalidations
258 #ifdef CONFIG_USER_PMON
260 mcr p15, 0, r0, c9, c14, 0
263 #ifndef CONFIG_ARM_THUMBEE
264 mrc p15, 0, r0, c0, c1, 0 @ read ID_PFR0 for ThumbEE
265 and r0, r0, #(0xf << 12) @ ThumbEE enabled field
266 teq r0, #(1 << 12) @ check if ThumbEE is present
269 mcr p14, 6, r5, c1, c0, 0 @ Initialize TEEHBR to 0
270 mrc p14, 6, r0, c0, c0, 0 @ load TEECR
271 orr r0, r0, #1 @ set the 1st bit in order to
272 mcr p14, 6, r0, c0, c0, 0 @ stop userspace TEEHBR access
277 #ifdef CONFIG_CPU_ENDIAN_BE8
278 orr r6, r6, #1 << 25 @ big-endian page tables
280 #ifdef CONFIG_SWP_EMULATE
281 orr r5, r5, #(1 << 10) @ set SW bit in "clear"
282 bic r6, r6, #(1 << 10) @ clear it in "mmuset"
284 mrc p15, 0, r0, c1, c0, 0 @ read control register
285 bic r0, r0, r5 @ clear bits them
286 orr r0, r0, r6 @ set them
287 THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions
288 mov pc, lr @ return to head.S:__ret
293 .space 4 * 11 @ 11 registers
297 @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
298 define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
302 string cpu_arch_name, "armv7"
303 string cpu_elf_name, "v7"
306 .section ".proc.info.init", #alloc, #execinstr
309 * Standard v7 proc info content
311 .macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0
312 ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
313 PMD_SECT_AF | PMD_FLAGS_SMP | \mm_mmuflags)
314 ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
315 PMD_SECT_AF | PMD_FLAGS_UP | \mm_mmuflags)
316 .long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | \
317 PMD_SECT_AP_READ | PMD_SECT_AF | \io_mmuflags
321 .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \
322 HWCAP_EDSP | HWCAP_TLS | \hwcaps
324 .long v7_processor_functions
330 #ifndef CONFIG_ARM_LPAE
332 * ARM Ltd. Cortex A5 processor.
334 .type __v7_ca5mp_proc_info, #object
335 __v7_ca5mp_proc_info:
338 __v7_proc __v7_ca5mp_setup
339 .size __v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info
342 * ARM Ltd. Cortex A9 processor.
344 .type __v7_ca9mp_proc_info, #object
345 __v7_ca9mp_proc_info:
348 __v7_proc __v7_ca9mp_setup
349 .size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
350 #endif /* CONFIG_ARM_LPAE */
353 * ARM Ltd. Cortex A15 processor.
355 .type __v7_ca15mp_proc_info, #object
356 __v7_ca15mp_proc_info:
359 __v7_proc __v7_ca15mp_setup, hwcaps = HWCAP_IDIV
360 .size __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
363 * Match any ARMv7 processor core.
365 .type __v7_proc_info, #object
367 .long 0x000f0000 @ Required ID value
368 .long 0x000f0000 @ Mask for ID
370 .size __v7_proc_info, . - __v7_proc_info