arch/arm/mm/mmu.c

   1 /*
   2  *  linux/arch/arm/mm/mmu.c
   3  *
   4  *  Copyright (C) 1995-2005 Russell King
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 #include <linux/module.h>
  11 #include <linux/kernel.h>
  12 #include <linux/errno.h>
  13 #include <linux/init.h>
  14 #include <linux/bootmem.h>
  15 #include <linux/mman.h>
  16 #include <linux/nodemask.h>
  17 #include <linux/sort.h>
  18
  19 #include <asm/cputype.h>
  20 #include <asm/mach-types.h>
  21 #include <asm/sections.h>
  22 #include <asm/cachetype.h>
  23 #include <asm/setup.h>
  24 #include <asm/sizes.h>
  25 #include <asm/smp_plat.h>
  26 #include <asm/tlb.h>
  27 #include <asm/highmem.h>
  28
  29 #include <asm/mach/arch.h>
  30 #include <asm/mach/map.h>
  31
  32 #include "mm.h"
  33
  34 DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
  35
  36 /*
  37  * empty_zero_page is a special page that is used for
  38  * zero-initialized data and COW.
  39  */
  40 struct page *empty_zero_page;
  41 EXPORT_SYMBOL(empty_zero_page);
  42
  43 /*
  44  * The pmd table for the upper-most set of pages.
  45  */
  46 pmd_t *top_pmd;
  47
  48 #define CPOLICY_UNCACHED        0
  49 #define CPOLICY_BUFFERED        1
  50 #define CPOLICY_WRITETHROUGH    2
  51 #define CPOLICY_WRITEBACK       3
  52 #define CPOLICY_WRITEALLOC      4
  53
  54 static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
  55 static unsigned int ecc_mask __initdata = 0;
  56 pgprot_t pgprot_user;
  57 pgprot_t pgprot_kernel;
  58
  59 EXPORT_SYMBOL(pgprot_user);
  60 EXPORT_SYMBOL(pgprot_kernel);
  61
  62 struct cachepolicy {
  63         const char      policy[16];
  64         unsigned int    cr_mask;
  65         unsigned int    pmd;
  66         unsigned int    pte;
  67 };
  68
  69 static struct cachepolicy cache_policies[] __initdata = {
  70         {
  71                 .policy         = "uncached",
  72                 .cr_mask        = CR_W|CR_C,
  73                 .pmd            = PMD_SECT_UNCACHED,
  74                 .pte            = L_PTE_MT_UNCACHED,
  75         }, {
  76                 .policy         = "buffered",
  77                 .cr_mask        = CR_C,
  78                 .pmd            = PMD_SECT_BUFFERED,
  79                 .pte            = L_PTE_MT_BUFFERABLE,
  80         }, {
  81                 .policy         = "writethrough",
  82                 .cr_mask        = 0,
  83                 .pmd            = PMD_SECT_WT,
  84                 .pte            = L_PTE_MT_WRITETHROUGH,
  85         }, {
  86                 .policy         = "writeback",
  87                 .cr_mask        = 0,
  88                 .pmd            = PMD_SECT_WB,
  89                 .pte            = L_PTE_MT_WRITEBACK,
  90         }, {
  91                 .policy         = "writealloc",
  92                 .cr_mask        = 0,
  93                 .pmd            = PMD_SECT_WBWA,
  94                 .pte            = L_PTE_MT_WRITEALLOC,
  95         }
  96 };
  97
  98 /*
  99  * These are useful for identifying cache coherency
 100  * problems by allowing the cache or the cache and
 101  * writebuffer to be turned off.  (Note: the write
 102  * buffer should not be on and the cache off).
 103  */
 104 static int __init early_cachepolicy(char *p)
 105 {
 106         int i;
 107
 108         for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
 109                 int len = strlen(cache_policies[i].policy);
 110
 111                 if (memcmp(p, cache_policies[i].policy, len) == 0) {
 112                         cachepolicy = i;
 113                         cr_alignment &= ~cache_policies[i].cr_mask;
 114                         cr_no_alignment &= ~cache_policies[i].cr_mask;
 115                         break;
 116                 }
 117         }
 118         if (i == ARRAY_SIZE(cache_policies))
 119                 printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
 120         /*
 121          * This restriction is partly to do with the way we boot; it is
 122          * unpredictable to have memory mapped using two different sets of
 123          * memory attributes (shared, type, and cache attribs).  We can not
 124          * change these attributes once the initial assembly has setup the
 125          * page tables.
 126          */
 127         if (cpu_architecture() >= CPU_ARCH_ARMv6) {
 128                 printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n");
 129                 cachepolicy = CPOLICY_WRITEBACK;
 130         }
 131         flush_cache_all();
 132         set_cr(cr_alignment);
 133         return 0;
 134 }
 135 early_param("cachepolicy", early_cachepolicy);
 136
 137 static int __init early_nocache(char *__unused)
 138 {
 139         char *p = "buffered";
 140         printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p);
 141         early_cachepolicy(p);
 142         return 0;
 143 }
 144 early_param("nocache", early_nocache);
 145
 146 static int __init early_nowrite(char *__unused)
 147 {
 148         char *p = "uncached";
 149         printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p);
 150         early_cachepolicy(p);
 151         return 0;
 152 }
 153 early_param("nowb", early_nowrite);
 154
 155 static int __init early_ecc(char *p)
 156 {
 157         if (memcmp(p, "on", 2) == 0)
 158                 ecc_mask = PMD_PROTECTION;
 159         else if (memcmp(p, "off", 3) == 0)
 160                 ecc_mask = 0;
 161         return 0;
 162 }
 163 early_param("ecc", early_ecc);
 164
 165 static int __init noalign_setup(char *__unused)
 166 {
 167         cr_alignment &= ~CR_A;
 168         cr_no_alignment &= ~CR_A;
 169         set_cr(cr_alignment);
 170         return 1;
 171 }
 172 __setup("noalign", noalign_setup);
 173
 174 #ifndef CONFIG_SMP
 175 void adjust_cr(unsigned long mask, unsigned long set)
 176 {
 177         unsigned long flags;
 178
 179         mask &= ~CR_A;
 180
 181         set &= mask;
 182
 183         local_irq_save(flags);
 184
 185         cr_no_alignment = (cr_no_alignment & ~mask) | set;
 186         cr_alignment = (cr_alignment & ~mask) | set;
 187
 188         set_cr((get_cr() & ~mask) | set);
 189
 190         local_irq_restore(flags);
 191 }
 192 #endif
 193
 194 #define PROT_PTE_DEVICE         L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_WRITE
 195 #define PROT_SECT_DEVICE        PMD_TYPE_SECT|PMD_SECT_AP_WRITE
 196
 197 static struct mem_type mem_types[] = {
 198         [MT_DEVICE] = {           /* Strongly ordered / ARMv6 shared device */
 199                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
 200                                   L_PTE_SHARED,
 201                 .prot_l1        = PMD_TYPE_TABLE,
 202                 .prot_sect      = PROT_SECT_DEVICE | PMD_SECT_S,
 203                 .domain         = DOMAIN_IO,
 204         },
 205         [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */
 206                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
 207                 .prot_l1        = PMD_TYPE_TABLE,
 208                 .prot_sect      = PROT_SECT_DEVICE,
 209                 .domain         = DOMAIN_IO,
 210         },
 211         [MT_DEVICE_CACHED] = {    /* ioremap_cached */
 212                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
 213                 .prot_l1        = PMD_TYPE_TABLE,
 214                 .prot_sect      = PROT_SECT_DEVICE | PMD_SECT_WB,
 215                 .domain         = DOMAIN_IO,
 216         },
 217         [MT_DEVICE_WC] = {      /* ioremap_wc */
 218                 .prot_pte       = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
 219                 .prot_l1        = PMD_TYPE_TABLE,
 220                 .prot_sect      = PROT_SECT_DEVICE,
 221                 .domain         = DOMAIN_IO,
 222         },
 223         [MT_UNCACHED] = {
 224                 .prot_pte       = PROT_PTE_DEVICE,
 225                 .prot_l1        = PMD_TYPE_TABLE,
 226                 .prot_sect      = PMD_TYPE_SECT | PMD_SECT_XN,
 227                 .domain         = DOMAIN_IO,
 228         },
 229         [MT_CACHECLEAN] = {
 230                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
 231                 .domain    = DOMAIN_KERNEL,
 232         },
 233         [MT_MINICLEAN] = {
 234                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
 235                 .domain    = DOMAIN_KERNEL,
 236         },
 237         [MT_LOW_VECTORS] = {
 238                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 239                                 L_PTE_EXEC,
 240                 .prot_l1   = PMD_TYPE_TABLE,
 241                 .domain    = DOMAIN_USER,
 242         },
 243         [MT_HIGH_VECTORS] = {
 244                 .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
 245                                 L_PTE_USER | L_PTE_EXEC,
 246                 .prot_l1   = PMD_TYPE_TABLE,
 247                 .domain    = DOMAIN_USER,
 248         },
 249         [MT_MEMORY] = {
 250                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
 251                 .domain    = DOMAIN_KERNEL,
 252         },
 253         [MT_ROM] = {
 254                 .prot_sect = PMD_TYPE_SECT,
 255                 .domain    = DOMAIN_KERNEL,
 256         },
 257         [MT_MEMORY_NONCACHED] = {
 258                 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
 259                 .domain    = DOMAIN_KERNEL,
 260         },
 261 };
 262
 263 const struct mem_type *get_mem_type(unsigned int type)
 264 {
 265         return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
 266 }
 267 EXPORT_SYMBOL(get_mem_type);
 268
 269 /*
 270  * Adjust the PMD section entries according to the CPU in use.
 271  */
 272 static void __init build_mem_type_table(void)
 273 {
 274         struct cachepolicy *cp;
 275         unsigned int cr = get_cr();
 276         unsigned int user_pgprot, kern_pgprot, vecs_pgprot;
 277         int cpu_arch = cpu_architecture();
 278         int i;
 279
 280         if (cpu_arch < CPU_ARCH_ARMv6) {
 281 #if defined(CONFIG_CPU_DCACHE_DISABLE)
 282                 if (cachepolicy > CPOLICY_BUFFERED)
 283                         cachepolicy = CPOLICY_BUFFERED;
 284 #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
 285                 if (cachepolicy > CPOLICY_WRITETHROUGH)
 286                         cachepolicy = CPOLICY_WRITETHROUGH;
 287 #endif
 288         }
 289         if (cpu_arch < CPU_ARCH_ARMv5) {
 290                 if (cachepolicy >= CPOLICY_WRITEALLOC)
 291                         cachepolicy = CPOLICY_WRITEBACK;
 292                 ecc_mask = 0;
 293         }
 294 #ifdef CONFIG_SMP
 295         cachepolicy = CPOLICY_WRITEALLOC;
 296 #endif
 297
 298         /*
 299          * Strip out features not present on earlier architectures.
 300          * Pre-ARMv5 CPUs don't have TEX bits.  Pre-ARMv6 CPUs or those
 301          * without extended page tables don't have the 'Shared' bit.
 302          */
 303         if (cpu_arch < CPU_ARCH_ARMv5)
 304                 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
 305                         mem_types[i].prot_sect &= ~PMD_SECT_TEX(7);
 306         if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3())
 307                 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
 308                         mem_types[i].prot_sect &= ~PMD_SECT_S;
 309
 310         /*
 311          * ARMv5 and lower, bit 4 must be set for page tables (was: cache
 312          * "update-able on write" bit on ARM610).  However, Xscale and
 313          * Xscale3 require this bit to be cleared.
 314          */
 315         if (cpu_is_xscale() || cpu_is_xsc3()) {
 316                 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
 317                         mem_types[i].prot_sect &= ~PMD_BIT4;
 318                         mem_types[i].prot_l1 &= ~PMD_BIT4;
 319                 }
 320         } else if (cpu_arch < CPU_ARCH_ARMv6) {
 321                 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
 322                         if (mem_types[i].prot_l1)
 323                                 mem_types[i].prot_l1 |= PMD_BIT4;
 324                         if (mem_types[i].prot_sect)
 325                                 mem_types[i].prot_sect |= PMD_BIT4;
 326                 }
 327         }
 328
 329         /*
 330          * Mark the device areas according to the CPU/architecture.
 331          */
 332         if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) {
 333                 if (!cpu_is_xsc3()) {
 334                         /*
 335                          * Mark device regions on ARMv6+ as execute-never
 336                          * to prevent speculative instruction fetches.
 337                          */
 338                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;
 339                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
 340                         mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
 341                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
 342                 }
 343                 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
 344                         /*
 345                          * For ARMv7 with TEX remapping,
 346                          * - shared device is SXCB=1100
 347                          * - nonshared device is SXCB=0100
 348                          * - write combine device mem is SXCB=0001
 349                          * (Uncached Normal memory)
 350                          */
 351                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1);
 352                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1);
 353                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
 354                 } else if (cpu_is_xsc3()) {
 355                         /*
 356                          * For Xscale3,
 357                          * - shared device is TEXCB=00101
 358                          * - nonshared device is TEXCB=01000
 359                          * - write combine device mem is TEXCB=00100
 360                          * (Inner/Outer Uncacheable in xsc3 parlance)
 361                          */
 362                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED;
 363                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
 364                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
 365                 } else {
 366                         /*
 367                          * For ARMv6 and ARMv7 without TEX remapping,
 368                          * - shared device is TEXCB=00001
 369                          * - nonshared device is TEXCB=01000
 370                          * - write combine device mem is TEXCB=00100
 371                          * (Uncached Normal in ARMv6 parlance).
 372                          */
 373                         mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
 374                         mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
 375                         mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
 376                 }
 377         } else {
 378                 /*
 379                  * On others, write combining is "Uncached/Buffered"
 380                  */
 381                 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
 382         }
 383
 384         /*
 385          * Now deal with the memory-type mappings
 386          */
 387         cp = &cache_policies[cachepolicy];
 388         vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
 389
 390 #ifndef CONFIG_SMP
 391         /*
 392          * Only use write-through for non-SMP systems
 393          */
 394         if (cpu_arch >= CPU_ARCH_ARMv5 && cachepolicy > CPOLICY_WRITETHROUGH)
 395                 vecs_pgprot = cache_policies[CPOLICY_WRITETHROUGH].pte;
 396 #endif
 397
 398         /*
 399          * Enable CPU-specific coherency if supported.
 400          * (Only available on XSC3 at the moment.)
 401          */
 402         if (arch_is_coherent() && cpu_is_xsc3())
 403                 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
 404
 405         /*
 406          * ARMv6 and above have extended page tables.
 407          */
 408         if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
 409                 /*
 410                  * Mark cache clean areas and XIP ROM read only
 411                  * from SVC mode and no access from userspace.
 412                  */
 413                 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 414                 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 415                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 416
 417 #ifdef CONFIG_SMP
 418                 /*
 419                  * Mark memory with the "shared" attribute for SMP systems
 420                  */
 421                 user_pgprot |= L_PTE_SHARED;
 422                 kern_pgprot |= L_PTE_SHARED;
 423                 vecs_pgprot |= L_PTE_SHARED;
 424                 mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S;
 425                 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S;
 426 #endif
 427         }
 428
 429         /*
 430          * Non-cacheable Normal - intended for memory areas that must
 431          * not cause dirty cache line writebacks when used
 432          */
 433         if (cpu_arch >= CPU_ARCH_ARMv6) {
 434                 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
 435                         /* Non-cacheable Normal is XCB = 001 */
 436                         mem_types[MT_MEMORY_NONCACHED].prot_sect |=
 437                                 PMD_SECT_BUFFERED;
 438                 } else {
 439                         /* For both ARMv6 and non-TEX-remapping ARMv7 */
 440                         mem_types[MT_MEMORY_NONCACHED].prot_sect |=
 441                                 PMD_SECT_TEX(1);
 442                 }
 443         } else {
 444                 mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
 445         }
 446
 447         for (i = 0; i < 16; i++) {
 448                 unsigned long v = pgprot_val(protection_map[i]);
 449                 protection_map[i] = __pgprot(v | user_pgprot);
 450         }
 451
 452         mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
 453         mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
 454
 455         pgprot_user   = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
 456         pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
 457                                  L_PTE_DIRTY | L_PTE_WRITE | kern_pgprot);
 458
 459         mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
 460         mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
 461         mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd;
 462         mem_types[MT_ROM].prot_sect |= cp->pmd;
 463
 464         switch (cp->pmd) {
 465         case PMD_SECT_WT:
 466                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
 467                 break;
 468         case PMD_SECT_WB:
 469         case PMD_SECT_WBWA:
 470                 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
 471                 break;
 472         }
 473         printk("Memory policy: ECC %sabled, Data cache %s\n",
 474                 ecc_mask ? "en" : "dis", cp->policy);
 475
 476         for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
 477                 struct mem_type *t = &mem_types[i];
 478                 if (t->prot_l1)
 479                         t->prot_l1 |= PMD_DOMAIN(t->domain);
 480                 if (t->prot_sect)
 481                         t->prot_sect |= PMD_DOMAIN(t->domain);
 482         }
 483 }
 484
 485 #define vectors_base()  (vectors_high() ? 0xffff0000 : 0)
 486
 487 static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
 488                                   unsigned long end, unsigned long pfn,
 489                                   const struct mem_type *type)
 490 {
 491         pte_t *pte;
 492
 493         if (pmd_none(*pmd)) {
 494                 pte = alloc_bootmem_low_pages(2 * PTRS_PER_PTE * sizeof(pte_t));
 495                 __pmd_populate(pmd, __pa(pte) | type->prot_l1);
 496         }
 497
 498         pte = pte_offset_kernel(pmd, addr);
 499         do {
 500                 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0);
 501                 pfn++;
 502         } while (pte++, addr += PAGE_SIZE, addr != end);
 503 }
 504
 505 static void __init alloc_init_section(pgd_t *pgd, unsigned long addr,
 506                                       unsigned long end, unsigned long phys,
 507                                       const struct mem_type *type)
 508 {
 509         pmd_t *pmd = pmd_offset(pgd, addr);
 510
 511         /*
 512          * Try a section mapping - end, addr and phys must all be aligned
 513          * to a section boundary.  Note that PMDs refer to the individual
 514          * L1 entries, whereas PGDs refer to a group of L1 entries making
 515          * up one logical pointer to an L2 table.
 516          */
 517         if (((addr | end | phys) & ~SECTION_MASK) == 0) {
 518                 pmd_t *p = pmd;
 519
 520                 if (addr & SECTION_SIZE)
 521                         pmd++;
 522
 523                 do {
 524                         *pmd = __pmd(phys | type->prot_sect);
 525                         phys += SECTION_SIZE;
 526                 } while (pmd++, addr += SECTION_SIZE, addr != end);
 527
 528                 flush_pmd_entry(p);
 529         } else {
 530                 /*
 531                  * No need to loop; pte's aren't interested in the
 532                  * individual L1 entries.
 533                  */
 534                 alloc_init_pte(pmd, addr, end, __phys_to_pfn(phys), type);
 535         }
 536 }
 537
 538 static void __init create_36bit_mapping(struct map_desc *md,
 539                                         const struct mem_type *type)
 540 {
 541         unsigned long phys, addr, length, end;
 542         pgd_t *pgd;
 543
 544         addr = md->virtual;
 545         phys = (unsigned long)__pfn_to_phys(md->pfn);
 546         length = PAGE_ALIGN(md->length);
 547
 548         if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
 549                 printk(KERN_ERR "MM: CPU does not support supersection "
 550                        "mapping for 0x%08llx at 0x%08lx\n",
 551                        __pfn_to_phys((u64)md->pfn), addr);
 552                 return;
 553         }
 554
 555         /* N.B. ARMv6 supersections are only defined to work with domain 0.
 556          *      Since domain assignments can in fact be arbitrary, the
 557          *      'domain == 0' check below is required to insure that ARMv6
 558          *      supersections are only allocated for domain 0 regardless
 559          *      of the actual domain assignments in use.
 560          */
 561         if (type->domain) {
 562                 printk(KERN_ERR "MM: invalid domain in supersection "
 563                        "mapping for 0x%08llx at 0x%08lx\n",
 564                        __pfn_to_phys((u64)md->pfn), addr);
 565                 return;
 566         }
 567
 568         if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
 569                 printk(KERN_ERR "MM: cannot create mapping for "
 570                        "0x%08llx at 0x%08lx invalid alignment\n",
 571                        __pfn_to_phys((u64)md->pfn), addr);
 572                 return;
 573         }
 574
 575         /*
 576          * Shift bits [35:32] of address into bits [23:20] of PMD
 577          * (See ARMv6 spec).
 578          */
 579         phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
 580
 581         pgd = pgd_offset_k(addr);
 582         end = addr + length;
 583         do {
 584                 pmd_t *pmd = pmd_offset(pgd, addr);
 585                 int i;
 586
 587                 for (i = 0; i < 16; i++)
 588                         *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER);
 589
 590                 addr += SUPERSECTION_SIZE;
 591                 phys += SUPERSECTION_SIZE;
 592                 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
 593         } while (addr != end);
 594 }
 595
 596 /*
 597  * Create the page directory entries and any necessary
 598  * page tables for the mapping specified by `md'.  We
 599  * are able to cope here with varying sizes and address
 600  * offsets, and we take full advantage of sections and
 601  * supersections.
 602  */
 603 static void __init create_mapping(struct map_desc *md)
 604 {
 605         unsigned long phys, addr, length, end;
 606         const struct mem_type *type;
 607         pgd_t *pgd;
 608
 609         if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
 610                 printk(KERN_WARNING "BUG: not creating mapping for "
 611                        "0x%08llx at 0x%08lx in user region\n",
 612                        __pfn_to_phys((u64)md->pfn), md->virtual);
 613                 return;
 614         }
 615
 616         if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
 617             md->virtual >= PAGE_OFFSET && md->virtual < VMALLOC_END) {
 618                 printk(KERN_WARNING "BUG: mapping for 0x%08llx at 0x%08lx "
 619                        "overlaps vmalloc space\n",
 620                        __pfn_to_phys((u64)md->pfn), md->virtual);
 621         }
 622
 623         type = &mem_types[md->type];
 624
 625         /*
 626          * Catch 36-bit addresses
 627          */
 628         if (md->pfn >= 0x100000) {
 629                 create_36bit_mapping(md, type);
 630                 return;
 631         }
 632
 633         addr = md->virtual & PAGE_MASK;
 634         phys = (unsigned long)__pfn_to_phys(md->pfn);
 635         length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
 636
 637         if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
 638                 printk(KERN_WARNING "BUG: map for 0x%08lx at 0x%08lx can not "
 639                        "be mapped using pages, ignoring.\n",
 640                        __pfn_to_phys(md->pfn), addr);
 641                 return;
 642         }
 643
 644         pgd = pgd_offset_k(addr);
 645         end = addr + length;
 646         do {
 647                 unsigned long next = pgd_addr_end(addr, end);
 648
 649                 alloc_init_section(pgd, addr, next, phys, type);
 650
 651                 phys += next - addr;
 652                 addr = next;
 653         } while (pgd++, addr != end);
 654 }
 655
 656 /*
 657  * Create the architecture specific mappings
 658  */
 659 void __init iotable_init(struct map_desc *io_desc, int nr)
 660 {
 661         int i;
 662
 663         for (i = 0; i < nr; i++)
 664                 create_mapping(io_desc + i);
 665 }
 666
 667 static unsigned long __initdata vmalloc_reserve = SZ_128M;
 668
 669 /*
 670  * vmalloc=size forces the vmalloc area to be exactly 'size'
 671  * bytes. This can be used to increase (or decrease) the vmalloc
 672  * area - the default is 128m.
 673  */
 674 static int __init early_vmalloc(char *arg)
 675 {
 676         vmalloc_reserve = memparse(arg, NULL);
 677
 678         if (vmalloc_reserve < SZ_16M) {
 679                 vmalloc_reserve = SZ_16M;
 680                 printk(KERN_WARNING
 681                         "vmalloc area too small, limiting to %luMB\n",
 682                         vmalloc_reserve >> 20);
 683         }
 684
 685         if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) {
 686                 vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M);
 687                 printk(KERN_WARNING
 688                         "vmalloc area is too big, limiting to %luMB\n",
 689                         vmalloc_reserve >> 20);
 690         }
 691         return 0;
 692 }
 693 early_param("vmalloc", early_vmalloc);
 694
 695 #define VMALLOC_MIN     (void *)(VMALLOC_END - vmalloc_reserve)
 696
 697 static void __init sanity_check_meminfo(void)
 698 {
 699         int i, j, highmem = 0;
 700
 701         for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
 702                 struct membank *bank = &meminfo.bank[j];
 703                 *bank = meminfo.bank[i];
 704
 705 #ifdef CONFIG_HIGHMEM
 706                 if (__va(bank->start) > VMALLOC_MIN ||
 707                     __va(bank->start) < (void *)PAGE_OFFSET)
 708                         highmem = 1;
 709
 710                 bank->highmem = highmem;
 711
 712                 /*
 713                  * Split those memory banks which are partially overlapping
 714                  * the vmalloc area greatly simplifying things later.
 715                  */
 716                 if (__va(bank->start) < VMALLOC_MIN &&
 717                     bank->size > VMALLOC_MIN - __va(bank->start)) {
 718                         if (meminfo.nr_banks >= NR_BANKS) {
 719                                 printk(KERN_CRIT "NR_BANKS too low, "
 720                                                  "ignoring high memory\n");
 721                         } else {
 722                                 memmove(bank + 1, bank,
 723                                         (meminfo.nr_banks - i) * sizeof(*bank));
 724                                 meminfo.nr_banks++;
 725                                 i++;
 726                                 bank[1].size -= VMALLOC_MIN - __va(bank->start);
 727                                 bank[1].start = __pa(VMALLOC_MIN - 1) + 1;
 728                                 bank[1].highmem = highmem = 1;
 729                                 j++;
 730                         }
 731                         bank->size = VMALLOC_MIN - __va(bank->start);
 732                 }
 733 #else
 734                 bank->highmem = highmem;
 735
 736                 /*
 737                  * Check whether this memory bank would entirely overlap
 738                  * the vmalloc area.
 739                  */
 740                 if (__va(bank->start) >= VMALLOC_MIN ||
 741                     __va(bank->start) < (void *)PAGE_OFFSET) {
 742                         printk(KERN_NOTICE "Ignoring RAM at %.8lx-%.8lx "
 743                                "(vmalloc region overlap).\n",
 744                                bank->start, bank->start + bank->size - 1);
 745                         continue;
 746                 }
 747
 748                 /*
 749                  * Check whether this memory bank would partially overlap
 750                  * the vmalloc area.
 751                  */
 752                 if (__va(bank->start + bank->size) > VMALLOC_MIN ||
 753                     __va(bank->start + bank->size) < __va(bank->start)) {
 754                         unsigned long newsize = VMALLOC_MIN - __va(bank->start);
 755                         printk(KERN_NOTICE "Truncating RAM at %.8lx-%.8lx "
 756                                "to -%.8lx (vmalloc region overlap).\n",
 757                                bank->start, bank->start + bank->size - 1,
 758                                bank->start + newsize - 1);
 759                         bank->size = newsize;
 760                 }
 761 #endif
 762                 j++;
 763         }
 764 #ifdef CONFIG_HIGHMEM
 765         if (highmem) {
 766                 const char *reason = NULL;
 767
 768                 if (cache_is_vipt_aliasing()) {
 769                         /*
 770                          * Interactions between kmap and other mappings
 771                          * make highmem support with aliasing VIPT caches
 772                          * rather difficult.
 773                          */
 774                         reason = "with VIPT aliasing cache";
 775 #ifdef CONFIG_SMP
 776                 } else if (tlb_ops_need_broadcast()) {
 777                         /*
 778                          * kmap_high needs to occasionally flush TLB entries,
 779                          * however, if the TLB entries need to be broadcast
 780                          * we may deadlock:
 781                          *  kmap_high(irqs off)->flush_all_zero_pkmaps->
 782                          *  flush_tlb_kernel_range->smp_call_function_many
 783                          *   (must not be called with irqs off)
 784                          */
 785                         reason = "without hardware TLB ops broadcasting";
 786 #endif
 787                 }
 788                 if (reason) {
 789                         printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n",
 790                                 reason);
 791                         while (j > 0 && meminfo.bank[j - 1].highmem)
 792                                 j--;
 793                 }
 794         }
 795 #endif
 796         meminfo.nr_banks = j;
 797 }
 798
 799 static inline void prepare_page_table(void)
 800 {
 801         unsigned long addr;
 802
 803         /*
 804          * Clear out all the mappings below the kernel image.
 805          */
 806         for (addr = 0; addr < MODULES_VADDR; addr += PGDIR_SIZE)
 807                 pmd_clear(pmd_off_k(addr));
 808
 809 #ifdef CONFIG_XIP_KERNEL
 810         /* The XIP kernel is mapped in the module area -- skip over it */
 811         addr = ((unsigned long)_etext + PGDIR_SIZE - 1) & PGDIR_MASK;
 812 #endif
 813         for ( ; addr < PAGE_OFFSET; addr += PGDIR_SIZE)
 814                 pmd_clear(pmd_off_k(addr));
 815
 816         /*
 817          * Clear out all the kernel space mappings, except for the first
 818          * memory bank, up to the end of the vmalloc region.
 819          */
 820         for (addr = __phys_to_virt(bank_phys_end(&meminfo.bank[0]));
 821              addr < VMALLOC_END; addr += PGDIR_SIZE)
 822                 pmd_clear(pmd_off_k(addr));
 823 }
 824
 825 /*
 826  * Reserve the various regions of node 0
 827  */
 828 void __init reserve_node_zero(pg_data_t *pgdat)
 829 {
 830         unsigned long res_size = 0;
 831
 832         /*
 833          * Register the kernel text and data with bootmem.
 834          * Note that this can only be in node 0.
 835          */
 836 #ifdef CONFIG_XIP_KERNEL
 837         reserve_bootmem_node(pgdat, __pa(_data), _end - _data,
 838                         BOOTMEM_DEFAULT);
 839 #else
 840         reserve_bootmem_node(pgdat, __pa(_stext), _end - _stext,
 841                         BOOTMEM_DEFAULT);
 842 #endif
 843
 844         /*
 845          * Reserve the page tables.  These are already in use,
 846          * and can only be in node 0.
 847          */
 848         reserve_bootmem_node(pgdat, __pa(swapper_pg_dir),
 849                              PTRS_PER_PGD * sizeof(pgd_t), BOOTMEM_DEFAULT);
 850
 851         /*
 852          * Hmm... This should go elsewhere, but we really really need to
 853          * stop things allocating the low memory; ideally we need a better
 854          * implementation of GFP_DMA which does not assume that DMA-able
 855          * memory starts at zero.
 856          */
 857         if (machine_is_integrator() || machine_is_cintegrator())
 858                 res_size = __pa(swapper_pg_dir) - PHYS_OFFSET;
 859
 860         /*
 861          * These should likewise go elsewhere.  They pre-reserve the
 862          * screen memory region at the start of main system memory.
 863          */
 864         if (machine_is_edb7211())
 865                 res_size = 0x00020000;
 866         if (machine_is_p720t())
 867                 res_size = 0x00014000;
 868
 869         /* H1940 and RX3715 need to reserve this for suspend */
 870
 871         if (machine_is_h1940() || machine_is_rx3715()) {
 872                 reserve_bootmem_node(pgdat, 0x30003000, 0x1000,
 873                                 BOOTMEM_DEFAULT);
 874                 reserve_bootmem_node(pgdat, 0x30081000, 0x1000,
 875                                 BOOTMEM_DEFAULT);
 876         }
 877
 878         if (machine_is_palmld() || machine_is_palmtx()) {
 879                 reserve_bootmem_node(pgdat, 0xa0000000, 0x1000,
 880                                 BOOTMEM_EXCLUSIVE);
 881                 reserve_bootmem_node(pgdat, 0xa0200000, 0x1000,
 882                                 BOOTMEM_EXCLUSIVE);
 883         }
 884
 885         if (machine_is_treo680() || machine_is_centro()) {
 886                 reserve_bootmem_node(pgdat, 0xa0000000, 0x1000,
 887                                 BOOTMEM_EXCLUSIVE);
 888                 reserve_bootmem_node(pgdat, 0xa2000000, 0x1000,
 889                                 BOOTMEM_EXCLUSIVE);
 890         }
 891
 892         if (machine_is_palmt5())
 893                 reserve_bootmem_node(pgdat, 0xa0200000, 0x1000,
 894                                 BOOTMEM_EXCLUSIVE);
 895
 896         /*
 897          * U300 - This platform family can share physical memory
 898          * between two ARM cpus, one running Linux and the other
 899          * running another OS.
 900          */
 901         if (machine_is_u300()) {
 902 #ifdef CONFIG_MACH_U300_SINGLE_RAM
 903 #if ((CONFIG_MACH_U300_ACCESS_MEM_SIZE & 1) == 1) &&    \
 904         CONFIG_MACH_U300_2MB_ALIGNMENT_FIX
 905                 res_size = 0x00100000;
 906 #endif
 907 #endif
 908         }
 909
 910 #ifdef CONFIG_SA1111
 911         /*
 912          * Because of the SA1111 DMA bug, we want to preserve our
 913          * precious DMA-able memory...
 914          */
 915         res_size = __pa(swapper_pg_dir) - PHYS_OFFSET;
 916 #endif
 917         if (res_size)
 918                 reserve_bootmem_node(pgdat, PHYS_OFFSET, res_size,
 919                                 BOOTMEM_DEFAULT);
 920 }
 921
 922 /*
 923  * Set up device the mappings.  Since we clear out the page tables for all
 924  * mappings above VMALLOC_END, we will remove any debug device mappings.
 925  * This means you have to be careful how you debug this function, or any
 926  * called function.  This means you can't use any function or debugging
 927  * method which may touch any device, otherwise the kernel _will_ crash.
 928  */
 929 static void __init devicemaps_init(struct machine_desc *mdesc)
 930 {
 931         struct map_desc map;
 932         unsigned long addr;
 933         void *vectors;
 934
 935         /*
 936          * Allocate the vector page early.
 937          */
 938         vectors = alloc_bootmem_low_pages(PAGE_SIZE);
 939
 940         for (addr = VMALLOC_END; addr; addr += PGDIR_SIZE)
 941                 pmd_clear(pmd_off_k(addr));
 942
 943         /*
 944          * Map the kernel if it is XIP.
 945          * It is always first in the modulearea.
 946          */
 947 #ifdef CONFIG_XIP_KERNEL
 948         map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
 949         map.virtual = MODULES_VADDR;
 950         map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK;
 951         map.type = MT_ROM;
 952         create_mapping(&map);
 953 #endif
 954
 955         /*
 956          * Map the cache flushing regions.
 957          */
 958 #ifdef FLUSH_BASE
 959         map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
 960         map.virtual = FLUSH_BASE;
 961         map.length = SZ_1M;
 962         map.type = MT_CACHECLEAN;
 963         create_mapping(&map);
 964 #endif
 965 #ifdef FLUSH_BASE_MINICACHE
 966         map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
 967         map.virtual = FLUSH_BASE_MINICACHE;
 968         map.length = SZ_1M;
 969         map.type = MT_MINICLEAN;
 970         create_mapping(&map);
 971 #endif
 972
 973         /*
 974          * Create a mapping for the machine vectors at the high-vectors
 975          * location (0xffff0000).  If we aren't using high-vectors, also
 976          * create a mapping at the low-vectors virtual address.
 977          */
 978         map.pfn = __phys_to_pfn(virt_to_phys(vectors));
 979         map.virtual = 0xffff0000;
 980         map.length = PAGE_SIZE;
 981         map.type = MT_HIGH_VECTORS;
 982         create_mapping(&map);
 983
 984         if (!vectors_high()) {
 985                 map.virtual = 0;
 986                 map.type = MT_LOW_VECTORS;
 987                 create_mapping(&map);
 988         }
 989
 990         /*
 991          * Ask the machine support to map in the statically mapped devices.
 992          */
 993         if (mdesc->map_io)
 994                 mdesc->map_io();
 995
 996         /*
 997          * Finally flush the caches and tlb to ensure that we're in a
 998          * consistent state wrt the writebuffer.  This also ensures that
 999          * any write-allocated cache lines in the vector page are written
1000          * back.  After this point, we can start to touch devices again.
1001          */
1002         local_flush_tlb_all();
1003         flush_cache_all();
1004 }
1005
1006 static void __init kmap_init(void)
1007 {
1008 #ifdef CONFIG_HIGHMEM
1009         pmd_t *pmd = pmd_off_k(PKMAP_BASE);
1010         pte_t *pte = alloc_bootmem_low_pages(2 * PTRS_PER_PTE * sizeof(pte_t));
1011         BUG_ON(!pmd_none(*pmd) || !pte);
1012         __pmd_populate(pmd, __pa(pte) | _PAGE_KERNEL_TABLE);
1013         pkmap_page_table = pte + PTRS_PER_PTE;
1014 #endif
1015 }
1016
1017 static inline void map_memory_bank(struct membank *bank)
1018 {
1019         struct map_desc map;
1020
1021         map.pfn = bank_pfn_start(bank);
1022         map.virtual = __phys_to_virt(bank_phys_start(bank));
1023         map.length = bank_phys_size(bank);
1024         map.type = MT_MEMORY;
1025
1026         create_mapping(&map);
1027 }
1028
1029 static void __init map_lowmem(void)
1030 {
1031         struct meminfo *mi = &meminfo;
1032         int i;
1033
1034         /* Map all the lowmem memory banks. */
1035         for (i = 0; i < mi->nr_banks; i++) {
1036                 struct membank *bank = &mi->bank[i];
1037
1038                 if (!bank->highmem)
1039                         map_memory_bank(bank);
1040         }
1041 }
1042
1043 static int __init meminfo_cmp(const void *_a, const void *_b)
1044 {
1045         const struct membank *a = _a, *b = _b;
1046         long cmp = bank_pfn_start(a) - bank_pfn_start(b);
1047         return cmp < 0 ? -1 : cmp > 0 ? 1 : 0;
1048 }
1049
1050 /*
1051  * paging_init() sets up the page tables, initialises the zone memory
1052  * maps, and sets up the zero page, bad page and bad page tables.
1053  */
1054 void __init paging_init(struct machine_desc *mdesc)
1055 {
1056         void *zero_page;
1057
1058         sort(&meminfo.bank, meminfo.nr_banks, sizeof(meminfo.bank[0]), meminfo_cmp, NULL);
1059
1060         build_mem_type_table();
1061         sanity_check_meminfo();
1062         prepare_page_table();
1063         map_lowmem();
1064         bootmem_init();
1065         devicemaps_init(mdesc);
1066         kmap_init();
1067
1068         top_pmd = pmd_off_k(0xffff0000);
1069
1070         /*
1071          * allocate the zero page.  Note that this always succeeds and
1072          * returns a zeroed result.
1073          */
1074         zero_page = alloc_bootmem_low_pages(PAGE_SIZE);
1075         empty_zero_page = virt_to_page(zero_page);
1076         __flush_dcache_page(NULL, empty_zero_page);
1077 }
1078
1079 /*
1080  * In order to soft-boot, we need to insert a 1:1 mapping in place of
1081  * the user-mode pages.  This will then ensure that we have predictable
1082  * results when turning the mmu off
1083  */
1084 void setup_mm_for_reboot(char mode)
1085 {
1086         unsigned long base_pmdval;
1087         pgd_t *pgd;
1088         int i;
1089
1090         if (current->mm && current->mm->pgd)
1091                 pgd = current->mm->pgd;
1092         else
1093                 pgd = init_mm.pgd;
1094
1095         base_pmdval = PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | PMD_TYPE_SECT;
1096         if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ && !cpu_is_xscale())
1097                 base_pmdval |= PMD_BIT4;
1098
1099         for (i = 0; i < FIRST_USER_PGD_NR + USER_PTRS_PER_PGD; i++, pgd++) {
1100                 unsigned long pmdval = (i << PGDIR_SHIFT) | base_pmdval;
1101                 pmd_t *pmd;
1102
1103                 pmd = pmd_off(pgd, i << PGDIR_SHIFT);
1104                 pmd[0] = __pmd(pmdval);
1105                 pmd[1] = __pmd(pmdval + (1 << (PGDIR_SHIFT - 1)));
1106                 flush_pmd_entry(pmd);
1107         }
1108
1109         local_flush_tlb_all();
1110 }