2 * linux/arch/arm/mm/dma-mapping.c
4 * Copyright (C) 2000-2004 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * DMA uncached mapping support.
12 #include <linux/module.h>
14 #include <linux/gfp.h>
15 #include <linux/errno.h>
16 #include <linux/list.h>
17 #include <linux/init.h>
18 #include <linux/device.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/dma-contiguous.h>
21 #include <linux/highmem.h>
22 #include <linux/memblock.h>
23 #include <linux/slab.h>
24 #include <linux/iommu.h>
25 #include <linux/vmalloc.h>
26 #include <linux/sizes.h>
28 #include <asm/memory.h>
29 #include <asm/highmem.h>
30 #include <asm/cacheflush.h>
31 #include <asm/tlbflush.h>
32 #include <asm/mach/arch.h>
33 #include <asm/dma-iommu.h>
34 #include <asm/mach/map.h>
35 #include <asm/system_info.h>
36 #include <asm/dma-contiguous.h>
41 * The DMA API is built upon the notion of "buffer ownership". A buffer
42 * is either exclusively owned by the CPU (and therefore may be accessed
43 * by it) or exclusively owned by the DMA device. These helper functions
44 * represent the transitions between these two ownership states.
46 * Note, however, that on later ARMs, this notion does not work due to
47 * speculative prefetches. We model our approach on the assumption that
48 * the CPU does do speculative prefetches, which means we clean caches
49 * before transfers and delay cache invalidation until transfer completion.
52 static void __dma_page_cpu_to_dev(struct page *, unsigned long,
53 size_t, enum dma_data_direction);
54 static void __dma_page_dev_to_cpu(struct page *, unsigned long,
55 size_t, enum dma_data_direction);
58 * arm_dma_map_page - map a portion of a page for streaming DMA
59 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
60 * @page: page that buffer resides in
61 * @offset: offset into page for start of buffer
62 * @size: size of buffer to map
63 * @dir: DMA transfer direction
65 * Ensure that any data held in the cache is appropriately discarded
68 * The device owns this memory once this call has completed. The CPU
69 * can regain ownership by calling dma_unmap_page().
71 static dma_addr_t arm_dma_map_page(struct device *dev, struct page *page,
72 unsigned long offset, size_t size, enum dma_data_direction dir,
73 struct dma_attrs *attrs)
75 if (!arch_is_coherent())
76 __dma_page_cpu_to_dev(page, offset, size, dir);
77 return pfn_to_dma(dev, page_to_pfn(page)) + offset;
81 * arm_dma_unmap_page - unmap a buffer previously mapped through dma_map_page()
82 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
83 * @handle: DMA address of buffer
84 * @size: size of buffer (same as passed to dma_map_page)
85 * @dir: DMA transfer direction (same as passed to dma_map_page)
87 * Unmap a page streaming mode DMA translation. The handle and size
88 * must match what was provided in the previous dma_map_page() call.
89 * All other usages are undefined.
91 * After this call, reads by the CPU to the buffer are guaranteed to see
92 * whatever the device wrote there.
94 static void arm_dma_unmap_page(struct device *dev, dma_addr_t handle,
95 size_t size, enum dma_data_direction dir,
96 struct dma_attrs *attrs)
98 if (!arch_is_coherent())
99 __dma_page_dev_to_cpu(pfn_to_page(dma_to_pfn(dev, handle)),
100 handle & ~PAGE_MASK, size, dir);
103 static void arm_dma_sync_single_for_cpu(struct device *dev,
104 dma_addr_t handle, size_t size, enum dma_data_direction dir)
106 unsigned int offset = handle & (PAGE_SIZE - 1);
107 struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset));
108 if (!arch_is_coherent())
109 __dma_page_dev_to_cpu(page, offset, size, dir);
112 static void arm_dma_sync_single_for_device(struct device *dev,
113 dma_addr_t handle, size_t size, enum dma_data_direction dir)
115 unsigned int offset = handle & (PAGE_SIZE - 1);
116 struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset));
117 if (!arch_is_coherent())
118 __dma_page_cpu_to_dev(page, offset, size, dir);
121 static int arm_dma_set_mask(struct device *dev, u64 dma_mask);
123 struct dma_map_ops arm_dma_ops = {
124 .alloc = arm_dma_alloc,
125 .free = arm_dma_free,
126 .mmap = arm_dma_mmap,
127 .map_page = arm_dma_map_page,
128 .unmap_page = arm_dma_unmap_page,
129 .map_sg = arm_dma_map_sg,
130 .unmap_sg = arm_dma_unmap_sg,
131 .sync_single_for_cpu = arm_dma_sync_single_for_cpu,
132 .sync_single_for_device = arm_dma_sync_single_for_device,
133 .sync_sg_for_cpu = arm_dma_sync_sg_for_cpu,
134 .sync_sg_for_device = arm_dma_sync_sg_for_device,
135 .set_dma_mask = arm_dma_set_mask,
137 EXPORT_SYMBOL(arm_dma_ops);
139 static u64 get_coherent_dma_mask(struct device *dev)
141 u64 mask = (u64)arm_dma_limit;
144 mask = dev->coherent_dma_mask;
147 * Sanity check the DMA mask - it must be non-zero, and
148 * must be able to be satisfied by a DMA allocation.
151 dev_warn(dev, "coherent DMA mask is unset\n");
155 if ((~mask) & (u64)arm_dma_limit) {
156 dev_warn(dev, "coherent DMA mask %#llx is smaller "
157 "than system GFP_DMA mask %#llx\n",
158 mask, (u64)arm_dma_limit);
166 static void __dma_clear_buffer(struct page *page, size_t size)
170 * Ensure that the allocated pages are zeroed, and that any data
171 * lurking in the kernel direct-mapped region is invalidated.
173 ptr = page_address(page);
175 memset(ptr, 0, size);
176 dmac_flush_range(ptr, ptr + size);
177 outer_flush_range(__pa(ptr), __pa(ptr) + size);
182 * Allocate a DMA buffer for 'dev' of size 'size' using the
183 * specified gfp mask. Note that 'size' must be page aligned.
185 static struct page *__dma_alloc_buffer(struct device *dev, size_t size, gfp_t gfp)
187 unsigned long order = get_order(size);
188 struct page *page, *p, *e;
190 page = alloc_pages(gfp, order);
195 * Now split the huge page and free the excess pages
197 split_page(page, order);
198 for (p = page + (size >> PAGE_SHIFT), e = page + (1 << order); p < e; p++)
201 __dma_clear_buffer(page, size);
207 * Free a DMA buffer. 'size' must be page aligned.
209 static void __dma_free_buffer(struct page *page, size_t size)
211 struct page *e = page + (size >> PAGE_SHIFT);
221 #define CONSISTENT_OFFSET(x) (((unsigned long)(x) - consistent_base) >> PAGE_SHIFT)
222 #define CONSISTENT_PTE_INDEX(x) (((unsigned long)(x) - consistent_base) >> PMD_SHIFT)
225 * These are the page tables (2MB each) covering uncached, DMA consistent allocations
227 static pte_t **consistent_pte;
229 #define DEFAULT_CONSISTENT_DMA_SIZE SZ_2M
231 unsigned long consistent_base = CONSISTENT_END - DEFAULT_CONSISTENT_DMA_SIZE;
233 void __init init_consistent_dma_size(unsigned long size)
235 unsigned long base = CONSISTENT_END - ALIGN(size, SZ_2M);
237 BUG_ON(consistent_pte); /* Check we're called before DMA region init */
238 BUG_ON(base < VMALLOC_END);
240 /* Grow region to accommodate specified size */
241 if (base < consistent_base)
242 consistent_base = base;
245 #include "vmregion.h"
247 static struct arm_vmregion_head consistent_head = {
248 .vm_lock = __SPIN_LOCK_UNLOCKED(&consistent_head.vm_lock),
249 .vm_list = LIST_HEAD_INIT(consistent_head.vm_list),
250 .vm_end = CONSISTENT_END,
253 #ifdef CONFIG_HUGETLB_PAGE
254 #error ARM Coherent DMA allocator does not (yet) support huge TLB
258 * Initialise the consistent memory allocation.
260 static int __init consistent_init(void)
268 unsigned long base = consistent_base;
269 unsigned long num_ptes = (CONSISTENT_END - base) >> PMD_SHIFT;
271 #ifndef CONFIG_ARM_DMA_USE_IOMMU
272 if (cpu_architecture() >= CPU_ARCH_ARMv6)
276 consistent_pte = kmalloc(num_ptes * sizeof(pte_t), GFP_KERNEL);
277 if (!consistent_pte) {
278 pr_err("%s: no memory\n", __func__);
282 pr_debug("DMA memory: 0x%08lx - 0x%08lx:\n", base, CONSISTENT_END);
283 consistent_head.vm_start = base;
286 pgd = pgd_offset(&init_mm, base);
288 pud = pud_alloc(&init_mm, pgd, base);
290 pr_err("%s: no pud tables\n", __func__);
295 pmd = pmd_alloc(&init_mm, pud, base);
297 pr_err("%s: no pmd tables\n", __func__);
301 WARN_ON(!pmd_none(*pmd));
303 pte = pte_alloc_kernel(pmd, base);
305 pr_err("%s: no pte tables\n", __func__);
310 consistent_pte[i++] = pte;
312 } while (base < CONSISTENT_END);
316 core_initcall(consistent_init);
318 static void *__alloc_from_contiguous(struct device *dev, size_t size,
319 pgprot_t prot, struct page **ret_page);
321 static struct arm_vmregion_head coherent_head = {
322 .vm_lock = __SPIN_LOCK_UNLOCKED(&coherent_head.vm_lock),
323 .vm_list = LIST_HEAD_INIT(coherent_head.vm_list),
326 size_t coherent_pool_size = DEFAULT_CONSISTENT_DMA_SIZE / 8;
328 static int __init early_coherent_pool(char *p)
330 coherent_pool_size = memparse(p, &p);
333 early_param("coherent_pool", early_coherent_pool);
336 * Initialise the coherent pool for atomic allocations.
338 static int __init coherent_init(void)
340 pgprot_t prot = pgprot_dmacoherent(pgprot_kernel);
341 size_t size = coherent_pool_size;
345 if (cpu_architecture() < CPU_ARCH_ARMv6)
348 ptr = __alloc_from_contiguous(NULL, size, prot, &page);
350 coherent_head.vm_start = (unsigned long) ptr;
351 coherent_head.vm_end = (unsigned long) ptr + size;
352 printk(KERN_INFO "DMA: preallocated %u KiB pool for atomic coherent allocations\n",
353 (unsigned)size / 1024);
356 printk(KERN_ERR "DMA: failed to allocate %u KiB pool for atomic coherent allocation\n",
357 (unsigned)size / 1024);
361 * CMA is activated by core_initcall, so we must be called after it.
363 postcore_initcall(coherent_init);
365 struct dma_contig_early_reserve {
370 static struct dma_contig_early_reserve dma_mmu_remap[MAX_CMA_AREAS] __initdata;
372 static int dma_mmu_remap_num __initdata;
374 void __init dma_contiguous_early_fixup(phys_addr_t base, unsigned long size)
376 dma_mmu_remap[dma_mmu_remap_num].base = base;
377 dma_mmu_remap[dma_mmu_remap_num].size = size;
381 void __init dma_contiguous_remap(void)
384 for (i = 0; i < dma_mmu_remap_num; i++) {
385 phys_addr_t start = dma_mmu_remap[i].base;
386 phys_addr_t end = start + dma_mmu_remap[i].size;
390 if (end > arm_lowmem_limit)
391 end = arm_lowmem_limit;
395 map.pfn = __phys_to_pfn(start);
396 map.virtual = __phys_to_virt(start);
397 map.length = end - start;
398 map.type = MT_MEMORY_DMA_READY;
401 * Clear previous low-memory mapping
403 for (addr = __phys_to_virt(start); addr < __phys_to_virt(end);
405 pmd_clear(pmd_off_k(addr));
407 iotable_init(&map, 1);
412 __dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot,
415 struct arm_vmregion *c;
419 if (!consistent_pte) {
420 pr_err("%s: not initialised\n", __func__);
426 * Align the virtual region allocation - maximum alignment is
427 * a section size, minimum is a page size. This helps reduce
428 * fragmentation of the DMA space, and also prevents allocations
429 * smaller than a section from crossing a section boundary.
432 if (bit > SECTION_SHIFT)
437 * Allocate a virtual address in the consistent mapping region.
439 c = arm_vmregion_alloc(&consistent_head, align, size,
440 gfp & ~(__GFP_DMA | __GFP_HIGHMEM), caller);
443 int idx = CONSISTENT_PTE_INDEX(c->vm_start);
444 u32 off = CONSISTENT_OFFSET(c->vm_start) & (PTRS_PER_PTE-1);
446 pte = consistent_pte[idx] + off;
450 BUG_ON(!pte_none(*pte));
452 set_pte_ext(pte, mk_pte(page, prot), 0);
456 if (off >= PTRS_PER_PTE) {
458 pte = consistent_pte[++idx];
460 } while (size -= PAGE_SIZE);
464 return (void *)c->vm_start;
469 static void __dma_free_remap(void *cpu_addr, size_t size)
471 struct arm_vmregion *c;
477 c = arm_vmregion_find_remove(&consistent_head, (unsigned long)cpu_addr);
479 pr_err("%s: trying to free invalid coherent area: %p\n",
485 if ((c->vm_end - c->vm_start) != size) {
486 pr_err("%s: freeing wrong coherent size (%ld != %d)\n",
487 __func__, c->vm_end - c->vm_start, size);
489 size = c->vm_end - c->vm_start;
492 idx = CONSISTENT_PTE_INDEX(c->vm_start);
493 off = CONSISTENT_OFFSET(c->vm_start) & (PTRS_PER_PTE-1);
494 ptep = consistent_pte[idx] + off;
497 pte_t pte = ptep_get_and_clear(&init_mm, addr, ptep);
502 if (off >= PTRS_PER_PTE) {
504 ptep = consistent_pte[++idx];
507 if (pte_none(pte) || !pte_present(pte))
508 pr_crit("%s: bad page in kernel page table\n",
510 } while (size -= PAGE_SIZE);
512 flush_tlb_kernel_range(c->vm_start, c->vm_end);
514 arm_vmregion_free(&consistent_head, c);
517 static int __dma_update_pte(pte_t *pte, pgtable_t token, unsigned long addr,
520 struct page *page = virt_to_page(addr);
521 pgprot_t prot = *(pgprot_t *)data;
523 set_pte_ext(pte, mk_pte(page, prot), 0);
527 static void __dma_remap(struct page *page, size_t size, pgprot_t prot)
529 unsigned long start = (unsigned long) page_address(page);
530 unsigned end = start + size;
532 apply_to_page_range(&init_mm, start, size, __dma_update_pte, &prot);
534 flush_tlb_kernel_range(start, end);
537 static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp,
538 pgprot_t prot, struct page **ret_page,
543 page = __dma_alloc_buffer(dev, size, gfp);
547 ptr = __dma_alloc_remap(page, size, gfp, prot, caller);
549 __dma_free_buffer(page, size);
557 static void *__alloc_from_pool(struct device *dev, size_t size,
558 struct page **ret_page, const void *caller)
560 struct arm_vmregion *c;
563 if (!coherent_head.vm_start) {
564 printk(KERN_ERR "%s: coherent pool not initialised!\n",
571 * Align the region allocation - allocations from pool are rather
572 * small, so align them to their order in pages, minimum is a page
573 * size. This helps reduce fragmentation of the DMA space.
575 align = PAGE_SIZE << get_order(size);
576 c = arm_vmregion_alloc(&coherent_head, align, size, 0, caller);
578 void *ptr = (void *)c->vm_start;
579 struct page *page = virt_to_page(ptr);
586 static int __free_from_pool(void *cpu_addr, size_t size)
588 unsigned long start = (unsigned long)cpu_addr;
589 unsigned long end = start + size;
590 struct arm_vmregion *c;
592 if (start < coherent_head.vm_start || end > coherent_head.vm_end)
595 c = arm_vmregion_find_remove(&coherent_head, (unsigned long)start);
597 if ((c->vm_end - c->vm_start) != size) {
598 printk(KERN_ERR "%s: freeing wrong coherent size (%ld != %d)\n",
599 __func__, c->vm_end - c->vm_start, size);
601 size = c->vm_end - c->vm_start;
604 arm_vmregion_free(&coherent_head, c);
608 static void *__alloc_from_contiguous(struct device *dev, size_t size,
609 pgprot_t prot, struct page **ret_page)
611 unsigned long order = get_order(size);
612 size_t count = size >> PAGE_SHIFT;
615 page = dma_alloc_from_contiguous(dev, count, order);
619 __dma_clear_buffer(page, size);
620 __dma_remap(page, size, prot);
623 return page_address(page);
626 static void __free_from_contiguous(struct device *dev, struct page *page,
629 __dma_remap(page, size, pgprot_kernel);
630 dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT);
633 static inline pgprot_t __get_dma_pgprot(struct dma_attrs *attrs, pgprot_t prot)
635 prot = dma_get_attr(DMA_ATTR_WRITE_COMBINE, attrs) ?
636 pgprot_writecombine(prot) :
637 pgprot_dmacoherent(prot);
643 #else /* !CONFIG_MMU */
647 #define __get_dma_pgprot(attrs, prot) __pgprot(0)
648 #define __alloc_remap_buffer(dev, size, gfp, prot, ret, c) NULL
649 #define __alloc_from_pool(dev, size, ret_page, c) NULL
650 #define __alloc_from_contiguous(dev, size, prot, ret) NULL
651 #define __free_from_pool(cpu_addr, size) 0
652 #define __free_from_contiguous(dev, page, size) do { } while (0)
653 #define __dma_free_remap(cpu_addr, size) do { } while (0)
655 #endif /* CONFIG_MMU */
657 static void *__alloc_simple_buffer(struct device *dev, size_t size, gfp_t gfp,
658 struct page **ret_page)
661 page = __dma_alloc_buffer(dev, size, gfp);
666 return page_address(page);
671 static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
672 gfp_t gfp, pgprot_t prot, const void *caller)
674 u64 mask = get_coherent_dma_mask(dev);
678 #ifdef CONFIG_DMA_API_DEBUG
679 u64 limit = (mask + 1) & ~mask;
680 if (limit && size >= limit) {
681 dev_warn(dev, "coherent allocation too big (requested %#x mask %#llx)\n",
690 if (mask < 0xffffffffULL)
694 * Following is a work-around (a.k.a. hack) to prevent pages
695 * with __GFP_COMP being passed to split_page() which cannot
696 * handle them. The real problem is that this flag probably
697 * should be 0 on ARM as it is not supported on this
698 * platform; see CONFIG_HUGETLBFS.
700 gfp &= ~(__GFP_COMP);
702 *handle = DMA_ERROR_CODE;
703 size = PAGE_ALIGN(size);
705 if (arch_is_coherent() || nommu())
706 addr = __alloc_simple_buffer(dev, size, gfp, &page);
707 else if (cpu_architecture() < CPU_ARCH_ARMv6)
708 addr = __alloc_remap_buffer(dev, size, gfp, prot, &page, caller);
709 else if (gfp & GFP_ATOMIC)
710 addr = __alloc_from_pool(dev, size, &page, caller);
712 addr = __alloc_from_contiguous(dev, size, prot, &page);
715 *handle = pfn_to_dma(dev, page_to_pfn(page));
721 * Allocate DMA-coherent memory space and return both the kernel remapped
722 * virtual and bus address for that space.
724 void *arm_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
725 gfp_t gfp, struct dma_attrs *attrs)
727 pgprot_t prot = __get_dma_pgprot(attrs, pgprot_kernel);
730 if (dma_alloc_from_coherent(dev, size, handle, &memory))
733 return __dma_alloc(dev, size, handle, gfp, prot,
734 __builtin_return_address(0));
738 * Create userspace mapping for the DMA-coherent memory.
740 int arm_dma_mmap(struct device *dev, struct vm_area_struct *vma,
741 void *cpu_addr, dma_addr_t dma_addr, size_t size,
742 struct dma_attrs *attrs)
746 unsigned long pfn = dma_to_pfn(dev, dma_addr);
747 vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot);
749 if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, &ret))
752 ret = remap_pfn_range(vma, vma->vm_start,
754 vma->vm_end - vma->vm_start,
756 #endif /* CONFIG_MMU */
762 * Free a buffer as defined by the above mapping.
764 void arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
765 dma_addr_t handle, struct dma_attrs *attrs)
767 struct page *page = pfn_to_page(dma_to_pfn(dev, handle));
769 if (dma_release_from_coherent(dev, get_order(size), cpu_addr))
772 size = PAGE_ALIGN(size);
774 if (arch_is_coherent() || nommu()) {
775 __dma_free_buffer(page, size);
776 } else if (cpu_architecture() < CPU_ARCH_ARMv6) {
777 __dma_free_remap(cpu_addr, size);
778 __dma_free_buffer(page, size);
780 if (__free_from_pool(cpu_addr, size))
783 * Non-atomic allocations cannot be freed with IRQs disabled
785 WARN_ON(irqs_disabled());
786 __free_from_contiguous(dev, page, size);
790 static void dma_cache_maint_page(struct page *page, unsigned long offset,
791 size_t size, enum dma_data_direction dir,
792 void (*op)(const void *, size_t, int))
795 * A single sg entry may refer to multiple physically contiguous
796 * pages. But we still need to process highmem pages individually.
797 * If highmem is not configured then the bulk of this loop gets
805 if (PageHighMem(page)) {
806 if (len + offset > PAGE_SIZE) {
807 if (offset >= PAGE_SIZE) {
808 page += offset / PAGE_SIZE;
811 len = PAGE_SIZE - offset;
813 vaddr = kmap_high_get(page);
818 } else if (cache_is_vipt()) {
819 /* unmapped pages might still be cached */
820 vaddr = kmap_atomic(page);
821 op(vaddr + offset, len, dir);
822 kunmap_atomic(vaddr);
825 vaddr = page_address(page) + offset;
835 * Make an area consistent for devices.
836 * Note: Drivers should NOT use this function directly, as it will break
837 * platforms with CONFIG_DMABOUNCE.
838 * Use the driver DMA support - see dma-mapping.h (dma_sync_*)
840 static void __dma_page_cpu_to_dev(struct page *page, unsigned long off,
841 size_t size, enum dma_data_direction dir)
845 dma_cache_maint_page(page, off, size, dir, dmac_map_area);
847 paddr = page_to_phys(page) + off;
848 if (dir == DMA_FROM_DEVICE) {
849 outer_inv_range(paddr, paddr + size);
851 outer_clean_range(paddr, paddr + size);
853 /* FIXME: non-speculating: flush on bidirectional mappings? */
856 static void __dma_page_dev_to_cpu(struct page *page, unsigned long off,
857 size_t size, enum dma_data_direction dir)
859 unsigned long paddr = page_to_phys(page) + off;
861 /* FIXME: non-speculating: not required */
862 /* don't bother invalidating if DMA to device */
863 if (dir != DMA_TO_DEVICE)
864 outer_inv_range(paddr, paddr + size);
866 dma_cache_maint_page(page, off, size, dir, dmac_unmap_area);
869 * Mark the D-cache clean for this page to avoid extra flushing.
871 if (dir != DMA_TO_DEVICE && off == 0 && size >= PAGE_SIZE)
872 set_bit(PG_dcache_clean, &page->flags);
876 * arm_dma_map_sg - map a set of SG buffers for streaming mode DMA
877 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
878 * @sg: list of buffers
879 * @nents: number of buffers to map
880 * @dir: DMA transfer direction
882 * Map a set of buffers described by scatterlist in streaming mode for DMA.
883 * This is the scatter-gather version of the dma_map_single interface.
884 * Here the scatter gather list elements are each tagged with the
885 * appropriate dma address and length. They are obtained via
886 * sg_dma_{address,length}.
888 * Device ownership issues as mentioned for dma_map_single are the same
891 int arm_dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
892 enum dma_data_direction dir, struct dma_attrs *attrs)
894 struct dma_map_ops *ops = get_dma_ops(dev);
895 struct scatterlist *s;
898 for_each_sg(sg, s, nents, i) {
899 #ifdef CONFIG_NEED_SG_DMA_LENGTH
900 s->dma_length = s->length;
902 s->dma_address = ops->map_page(dev, sg_page(s), s->offset,
903 s->length, dir, attrs);
904 if (dma_mapping_error(dev, s->dma_address))
910 for_each_sg(sg, s, i, j)
911 ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs);
916 * arm_dma_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
917 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
918 * @sg: list of buffers
919 * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
920 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
922 * Unmap a set of streaming mode DMA translations. Again, CPU access
923 * rules concerning calls here are the same as for dma_unmap_single().
925 void arm_dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
926 enum dma_data_direction dir, struct dma_attrs *attrs)
928 struct dma_map_ops *ops = get_dma_ops(dev);
929 struct scatterlist *s;
933 for_each_sg(sg, s, nents, i)
934 ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs);
938 * arm_dma_sync_sg_for_cpu
939 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
940 * @sg: list of buffers
941 * @nents: number of buffers to map (returned from dma_map_sg)
942 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
944 void arm_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
945 int nents, enum dma_data_direction dir)
947 struct dma_map_ops *ops = get_dma_ops(dev);
948 struct scatterlist *s;
951 for_each_sg(sg, s, nents, i)
952 ops->sync_single_for_cpu(dev, sg_dma_address(s), s->length,
957 * arm_dma_sync_sg_for_device
958 * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
959 * @sg: list of buffers
960 * @nents: number of buffers to map (returned from dma_map_sg)
961 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
963 void arm_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
964 int nents, enum dma_data_direction dir)
966 struct dma_map_ops *ops = get_dma_ops(dev);
967 struct scatterlist *s;
970 for_each_sg(sg, s, nents, i)
971 ops->sync_single_for_device(dev, sg_dma_address(s), s->length,
976 * Return whether the given device DMA address mask can be supported
977 * properly. For example, if your device can only drive the low 24-bits
978 * during bus mastering, then you would pass 0x00ffffff as the mask
981 int dma_supported(struct device *dev, u64 mask)
983 if (mask < (u64)arm_dma_limit)
987 EXPORT_SYMBOL(dma_supported);
989 static int arm_dma_set_mask(struct device *dev, u64 dma_mask)
991 if (!dev->dma_mask || !dma_supported(dev, dma_mask))
994 *dev->dma_mask = dma_mask;
999 #define PREALLOC_DMA_DEBUG_ENTRIES 4096
1001 static int __init dma_debug_do_init(void)
1004 arm_vmregion_create_proc("dma-mappings", &consistent_head);
1006 dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);
1009 fs_initcall(dma_debug_do_init);
1011 #ifdef CONFIG_ARM_DMA_USE_IOMMU
1015 static inline dma_addr_t __alloc_iova(struct dma_iommu_mapping *mapping,
1018 unsigned int order = get_order(size);
1019 unsigned int align = 0;
1020 unsigned int count, start;
1021 unsigned long flags;
1023 count = ((PAGE_ALIGN(size) >> PAGE_SHIFT) +
1024 (1 << mapping->order) - 1) >> mapping->order;
1026 if (order > mapping->order)
1027 align = (1 << (order - mapping->order)) - 1;
1029 spin_lock_irqsave(&mapping->lock, flags);
1030 start = bitmap_find_next_zero_area(mapping->bitmap, mapping->bits, 0,
1032 if (start > mapping->bits) {
1033 spin_unlock_irqrestore(&mapping->lock, flags);
1034 return DMA_ERROR_CODE;
1037 bitmap_set(mapping->bitmap, start, count);
1038 spin_unlock_irqrestore(&mapping->lock, flags);
1040 return mapping->base + (start << (mapping->order + PAGE_SHIFT));
1043 static inline void __free_iova(struct dma_iommu_mapping *mapping,
1044 dma_addr_t addr, size_t size)
1046 unsigned int start = (addr - mapping->base) >>
1047 (mapping->order + PAGE_SHIFT);
1048 unsigned int count = ((size >> PAGE_SHIFT) +
1049 (1 << mapping->order) - 1) >> mapping->order;
1050 unsigned long flags;
1052 spin_lock_irqsave(&mapping->lock, flags);
1053 bitmap_clear(mapping->bitmap, start, count);
1054 spin_unlock_irqrestore(&mapping->lock, flags);
1057 static struct page **__iommu_alloc_buffer(struct device *dev, size_t size, gfp_t gfp)
1059 struct page **pages;
1060 int count = size >> PAGE_SHIFT;
1061 int array_size = count * sizeof(struct page *);
1064 if (array_size <= PAGE_SIZE)
1065 pages = kzalloc(array_size, gfp);
1067 pages = vzalloc(array_size);
1072 int j, order = __ffs(count);
1074 pages[i] = alloc_pages(gfp | __GFP_NOWARN, order);
1075 while (!pages[i] && order)
1076 pages[i] = alloc_pages(gfp | __GFP_NOWARN, --order);
1081 split_page(pages[i], order);
1084 pages[i + j] = pages[i] + j;
1086 __dma_clear_buffer(pages[i], PAGE_SIZE << order);
1088 count -= 1 << order;
1095 __free_pages(pages[i], 0);
1096 if (array_size < PAGE_SIZE)
1103 static int __iommu_free_buffer(struct device *dev, struct page **pages, size_t size)
1105 int count = size >> PAGE_SHIFT;
1106 int array_size = count * sizeof(struct page *);
1108 for (i = 0; i < count; i++)
1110 __free_pages(pages[i], 0);
1111 if (array_size < PAGE_SIZE)
1119 * Create a CPU mapping for a specified pages
1122 __iommu_alloc_remap(struct page **pages, size_t size, gfp_t gfp, pgprot_t prot)
1124 struct arm_vmregion *c;
1126 size_t count = size >> PAGE_SHIFT;
1129 if (!consistent_pte[0]) {
1130 pr_err("%s: not initialised\n", __func__);
1136 * Align the virtual region allocation - maximum alignment is
1137 * a section size, minimum is a page size. This helps reduce
1138 * fragmentation of the DMA space, and also prevents allocations
1139 * smaller than a section from crossing a section boundary.
1141 bit = fls(size - 1);
1142 if (bit > SECTION_SHIFT)
1143 bit = SECTION_SHIFT;
1147 * Allocate a virtual address in the consistent mapping region.
1149 c = arm_vmregion_alloc(&consistent_head, align, size,
1150 gfp & ~(__GFP_DMA | __GFP_HIGHMEM), NULL);
1153 int idx = CONSISTENT_PTE_INDEX(c->vm_start);
1155 u32 off = CONSISTENT_OFFSET(c->vm_start) & (PTRS_PER_PTE-1);
1157 pte = consistent_pte[idx] + off;
1161 BUG_ON(!pte_none(*pte));
1163 set_pte_ext(pte, mk_pte(pages[i], prot), 0);
1167 if (off >= PTRS_PER_PTE) {
1169 pte = consistent_pte[++idx];
1171 } while (i < count);
1175 return (void *)c->vm_start;
1181 * Create a mapping in device IO address space for specified pages
1184 __iommu_create_mapping(struct device *dev, struct page **pages, size_t size)
1186 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1187 unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
1188 dma_addr_t dma_addr, iova;
1189 int i, ret = DMA_ERROR_CODE;
1191 dma_addr = __alloc_iova(mapping, size);
1192 if (dma_addr == DMA_ERROR_CODE)
1196 for (i = 0; i < count; ) {
1197 unsigned int next_pfn = page_to_pfn(pages[i]) + 1;
1198 phys_addr_t phys = page_to_phys(pages[i]);
1199 unsigned int len, j;
1201 for (j = i + 1; j < count; j++, next_pfn++)
1202 if (page_to_pfn(pages[j]) != next_pfn)
1205 len = (j - i) << PAGE_SHIFT;
1206 ret = iommu_map(mapping->domain, iova, phys, len, 0);
1214 iommu_unmap(mapping->domain, dma_addr, iova-dma_addr);
1215 __free_iova(mapping, dma_addr, size);
1216 return DMA_ERROR_CODE;
1219 static int __iommu_remove_mapping(struct device *dev, dma_addr_t iova, size_t size)
1221 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1224 * add optional in-page offset from iova to size and align
1225 * result to page size
1227 size = PAGE_ALIGN((iova & ~PAGE_MASK) + size);
1230 iommu_unmap(mapping->domain, iova, size);
1231 __free_iova(mapping, iova, size);
1235 static void *arm_iommu_alloc_attrs(struct device *dev, size_t size,
1236 dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs)
1238 pgprot_t prot = __get_dma_pgprot(attrs, pgprot_kernel);
1239 struct page **pages;
1242 *handle = DMA_ERROR_CODE;
1243 size = PAGE_ALIGN(size);
1245 pages = __iommu_alloc_buffer(dev, size, gfp);
1249 *handle = __iommu_create_mapping(dev, pages, size);
1250 if (*handle == DMA_ERROR_CODE)
1253 addr = __iommu_alloc_remap(pages, size, gfp, prot);
1260 __iommu_remove_mapping(dev, *handle, size);
1262 __iommu_free_buffer(dev, pages, size);
1266 static int arm_iommu_mmap_attrs(struct device *dev, struct vm_area_struct *vma,
1267 void *cpu_addr, dma_addr_t dma_addr, size_t size,
1268 struct dma_attrs *attrs)
1270 struct arm_vmregion *c;
1272 vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot);
1273 c = arm_vmregion_find(&consistent_head, (unsigned long)cpu_addr);
1276 struct page **pages = c->priv;
1278 unsigned long uaddr = vma->vm_start;
1279 unsigned long usize = vma->vm_end - vma->vm_start;
1285 ret = vm_insert_page(vma, uaddr, pages[i++]);
1287 pr_err("Remapping memory, error: %d\n", ret);
1293 } while (usize > 0);
1299 * free a page as defined by the above mapping.
1300 * Must not be called with IRQs disabled.
1302 void arm_iommu_free_attrs(struct device *dev, size_t size, void *cpu_addr,
1303 dma_addr_t handle, struct dma_attrs *attrs)
1305 struct arm_vmregion *c;
1306 size = PAGE_ALIGN(size);
1308 c = arm_vmregion_find(&consistent_head, (unsigned long)cpu_addr);
1310 struct page **pages = c->priv;
1311 __dma_free_remap(cpu_addr, size);
1312 __iommu_remove_mapping(dev, handle, size);
1313 __iommu_free_buffer(dev, pages, size);
1318 * Map a part of the scatter-gather list into contiguous io address space
1320 static int __map_sg_chunk(struct device *dev, struct scatterlist *sg,
1321 size_t size, dma_addr_t *handle,
1322 enum dma_data_direction dir)
1324 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1325 dma_addr_t iova, iova_base;
1328 struct scatterlist *s;
1330 size = PAGE_ALIGN(size);
1331 *handle = DMA_ERROR_CODE;
1333 iova_base = iova = __alloc_iova(mapping, size);
1334 if (iova == DMA_ERROR_CODE)
1337 for (count = 0, s = sg; count < (size >> PAGE_SHIFT); s = sg_next(s)) {
1338 phys_addr_t phys = page_to_phys(sg_page(s));
1339 unsigned int len = PAGE_ALIGN(s->offset + s->length);
1341 if (!arch_is_coherent())
1342 __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir);
1344 ret = iommu_map(mapping->domain, iova, phys, len, 0);
1347 count += len >> PAGE_SHIFT;
1350 *handle = iova_base;
1354 iommu_unmap(mapping->domain, iova_base, count * PAGE_SIZE);
1355 __free_iova(mapping, iova_base, size);
1360 * arm_iommu_map_sg - map a set of SG buffers for streaming mode DMA
1361 * @dev: valid struct device pointer
1362 * @sg: list of buffers
1363 * @nents: number of buffers to map
1364 * @dir: DMA transfer direction
1366 * Map a set of buffers described by scatterlist in streaming mode for DMA.
1367 * The scatter gather list elements are merged together (if possible) and
1368 * tagged with the appropriate dma address and length. They are obtained via
1369 * sg_dma_{address,length}.
1371 int arm_iommu_map_sg(struct device *dev, struct scatterlist *sg, int nents,
1372 enum dma_data_direction dir, struct dma_attrs *attrs)
1374 struct scatterlist *s = sg, *dma = sg, *start = sg;
1376 unsigned int offset = s->offset;
1377 unsigned int size = s->offset + s->length;
1378 unsigned int max = dma_get_max_seg_size(dev);
1380 for (i = 1; i < nents; i++) {
1383 s->dma_address = DMA_ERROR_CODE;
1386 if (s->offset || (size & ~PAGE_MASK) || size + s->length > max) {
1387 if (__map_sg_chunk(dev, start, size, &dma->dma_address,
1391 dma->dma_address += offset;
1392 dma->dma_length = size - offset;
1394 size = offset = s->offset;
1401 if (__map_sg_chunk(dev, start, size, &dma->dma_address, dir) < 0)
1404 dma->dma_address += offset;
1405 dma->dma_length = size - offset;
1410 for_each_sg(sg, s, count, i)
1411 __iommu_remove_mapping(dev, sg_dma_address(s), sg_dma_len(s));
1416 * arm_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
1417 * @dev: valid struct device pointer
1418 * @sg: list of buffers
1419 * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
1420 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1422 * Unmap a set of streaming mode DMA translations. Again, CPU access
1423 * rules concerning calls here are the same as for dma_unmap_single().
1425 void arm_iommu_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
1426 enum dma_data_direction dir, struct dma_attrs *attrs)
1428 struct scatterlist *s;
1431 for_each_sg(sg, s, nents, i) {
1433 __iommu_remove_mapping(dev, sg_dma_address(s),
1435 if (!arch_is_coherent())
1436 __dma_page_dev_to_cpu(sg_page(s), s->offset,
1442 * arm_iommu_sync_sg_for_cpu
1443 * @dev: valid struct device pointer
1444 * @sg: list of buffers
1445 * @nents: number of buffers to map (returned from dma_map_sg)
1446 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1448 void arm_iommu_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
1449 int nents, enum dma_data_direction dir)
1451 struct scatterlist *s;
1454 for_each_sg(sg, s, nents, i)
1455 if (!arch_is_coherent())
1456 __dma_page_dev_to_cpu(sg_page(s), s->offset, s->length, dir);
1461 * arm_iommu_sync_sg_for_device
1462 * @dev: valid struct device pointer
1463 * @sg: list of buffers
1464 * @nents: number of buffers to map (returned from dma_map_sg)
1465 * @dir: DMA transfer direction (same as was passed to dma_map_sg)
1467 void arm_iommu_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
1468 int nents, enum dma_data_direction dir)
1470 struct scatterlist *s;
1473 for_each_sg(sg, s, nents, i)
1474 if (!arch_is_coherent())
1475 __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir);
1480 * arm_iommu_map_page
1481 * @dev: valid struct device pointer
1482 * @page: page that buffer resides in
1483 * @offset: offset into page for start of buffer
1484 * @size: size of buffer to map
1485 * @dir: DMA transfer direction
1487 * IOMMU aware version of arm_dma_map_page()
1489 static dma_addr_t arm_iommu_map_page(struct device *dev, struct page *page,
1490 unsigned long offset, size_t size, enum dma_data_direction dir,
1491 struct dma_attrs *attrs)
1493 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1494 dma_addr_t dma_addr;
1495 int ret, len = PAGE_ALIGN(size + offset);
1497 if (!arch_is_coherent())
1498 __dma_page_cpu_to_dev(page, offset, size, dir);
1500 dma_addr = __alloc_iova(mapping, len);
1501 if (dma_addr == DMA_ERROR_CODE)
1504 ret = iommu_map(mapping->domain, dma_addr, page_to_phys(page), len, 0);
1508 return dma_addr + offset;
1510 __free_iova(mapping, dma_addr, len);
1511 return DMA_ERROR_CODE;
1515 * arm_iommu_unmap_page
1516 * @dev: valid struct device pointer
1517 * @handle: DMA address of buffer
1518 * @size: size of buffer (same as passed to dma_map_page)
1519 * @dir: DMA transfer direction (same as passed to dma_map_page)
1521 * IOMMU aware version of arm_dma_unmap_page()
1523 static void arm_iommu_unmap_page(struct device *dev, dma_addr_t handle,
1524 size_t size, enum dma_data_direction dir,
1525 struct dma_attrs *attrs)
1527 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1528 dma_addr_t iova = handle & PAGE_MASK;
1529 struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
1530 int offset = handle & ~PAGE_MASK;
1531 int len = PAGE_ALIGN(size + offset);
1536 if (!arch_is_coherent())
1537 __dma_page_dev_to_cpu(page, offset, size, dir);
1539 iommu_unmap(mapping->domain, iova, len);
1540 __free_iova(mapping, iova, len);
1543 static void arm_iommu_sync_single_for_cpu(struct device *dev,
1544 dma_addr_t handle, size_t size, enum dma_data_direction dir)
1546 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1547 dma_addr_t iova = handle & PAGE_MASK;
1548 struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
1549 unsigned int offset = handle & ~PAGE_MASK;
1554 if (!arch_is_coherent())
1555 __dma_page_dev_to_cpu(page, offset, size, dir);
1558 static void arm_iommu_sync_single_for_device(struct device *dev,
1559 dma_addr_t handle, size_t size, enum dma_data_direction dir)
1561 struct dma_iommu_mapping *mapping = dev->archdata.mapping;
1562 dma_addr_t iova = handle & PAGE_MASK;
1563 struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
1564 unsigned int offset = handle & ~PAGE_MASK;
1569 __dma_page_cpu_to_dev(page, offset, size, dir);
1572 struct dma_map_ops iommu_ops = {
1573 .alloc = arm_iommu_alloc_attrs,
1574 .free = arm_iommu_free_attrs,
1575 .mmap = arm_iommu_mmap_attrs,
1577 .map_page = arm_iommu_map_page,
1578 .unmap_page = arm_iommu_unmap_page,
1579 .sync_single_for_cpu = arm_iommu_sync_single_for_cpu,
1580 .sync_single_for_device = arm_iommu_sync_single_for_device,
1582 .map_sg = arm_iommu_map_sg,
1583 .unmap_sg = arm_iommu_unmap_sg,
1584 .sync_sg_for_cpu = arm_iommu_sync_sg_for_cpu,
1585 .sync_sg_for_device = arm_iommu_sync_sg_for_device,
1589 * arm_iommu_create_mapping
1590 * @bus: pointer to the bus holding the client device (for IOMMU calls)
1591 * @base: start address of the valid IO address space
1592 * @size: size of the valid IO address space
1593 * @order: accuracy of the IO addresses allocations
1595 * Creates a mapping structure which holds information about used/unused
1596 * IO address ranges, which is required to perform memory allocation and
1597 * mapping with IOMMU aware functions.
1599 * The client device need to be attached to the mapping with
1600 * arm_iommu_attach_device function.
1602 struct dma_iommu_mapping *
1603 arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, size_t size,
1606 unsigned int count = size >> (PAGE_SHIFT + order);
1607 unsigned int bitmap_size = BITS_TO_LONGS(count) * sizeof(long);
1608 struct dma_iommu_mapping *mapping;
1612 return ERR_PTR(-EINVAL);
1614 mapping = kzalloc(sizeof(struct dma_iommu_mapping), GFP_KERNEL);
1618 mapping->bitmap = kzalloc(bitmap_size, GFP_KERNEL);
1619 if (!mapping->bitmap)
1622 mapping->base = base;
1623 mapping->bits = BITS_PER_BYTE * bitmap_size;
1624 mapping->order = order;
1625 spin_lock_init(&mapping->lock);
1627 mapping->domain = iommu_domain_alloc(bus);
1628 if (!mapping->domain)
1631 kref_init(&mapping->kref);
1634 kfree(mapping->bitmap);
1638 return ERR_PTR(err);
1641 static void release_iommu_mapping(struct kref *kref)
1643 struct dma_iommu_mapping *mapping =
1644 container_of(kref, struct dma_iommu_mapping, kref);
1646 iommu_domain_free(mapping->domain);
1647 kfree(mapping->bitmap);
1651 void arm_iommu_release_mapping(struct dma_iommu_mapping *mapping)
1654 kref_put(&mapping->kref, release_iommu_mapping);
1658 * arm_iommu_attach_device
1659 * @dev: valid struct device pointer
1660 * @mapping: io address space mapping structure (returned from
1661 * arm_iommu_create_mapping)
1663 * Attaches specified io address space mapping to the provided device,
1664 * this replaces the dma operations (dma_map_ops pointer) with the
1665 * IOMMU aware version. More than one client might be attached to
1666 * the same io address space mapping.
1668 int arm_iommu_attach_device(struct device *dev,
1669 struct dma_iommu_mapping *mapping)
1673 err = iommu_attach_device(mapping->domain, dev);
1677 kref_get(&mapping->kref);
1678 dev->archdata.mapping = mapping;
1679 set_dma_ops(dev, &iommu_ops);
1681 pr_info("Attached IOMMU controller to %s device.\n", dev_name(dev));