1 comment "Processor Type"
7 # Select CPU types depending on the architecture selected. This selects
8 # which CPUs we support in the kernel image, and the compiler instruction
13 bool "Support ARM610 processor"
19 select CPU_COPY_V3 if MMU
20 select CPU_TLB_V3 if MMU
22 The ARM610 is the successor to the ARM3 processor
23 and was produced by VLSI Technology Inc.
25 Say Y if you want support for the ARM610 processor.
30 bool "Support ARM7TDMI processor"
36 A 32-bit RISC microprocessor based on the ARM7 processor core
37 which has no memory control unit and cache.
39 Say Y if you want support for the ARM7TDMI processor.
44 bool "Support ARM710 processor" if !ARCH_CLPS7500 && ARCH_RPC
45 default y if ARCH_CLPS7500
50 select CPU_COPY_V3 if MMU
51 select CPU_TLB_V3 if MMU
53 A 32-bit RISC microprocessor based on the ARM7 processor core
54 designed by Advanced RISC Machines Ltd. The ARM710 is the
55 successor to the ARM610 processor. It was released in
56 July 1994 by VLSI Technology Inc.
58 Say Y if you want support for the ARM710 processor.
63 bool "Support ARM720T processor" if !ARCH_CLPS711X && !ARCH_L7200 && !ARCH_CDB89712 && ARCH_INTEGRATOR
64 default y if ARCH_CLPS711X || ARCH_L7200 || ARCH_CDB89712 || ARCH_H720X
70 select CPU_COPY_V4WT if MMU
71 select CPU_TLB_V4WT if MMU
73 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
74 MMU built around an ARM7TDMI core.
76 Say Y if you want support for the ARM720T processor.
81 bool "Support ARM740T processor" if ARCH_INTEGRATOR
85 select CPU_CACHE_V3 # although the core is v4t
88 A 32-bit RISC processor with 8KB cache or 4KB variants,
89 write buffer and MPU(Protection Unit) built around
92 Say Y if you want support for the ARM740T processor.
97 bool "Support ARM9TDMI processor"
100 select CPU_ABRT_NOMMU
103 A 32-bit RISC microprocessor based on the ARM9 processor core
104 which has no memory control unit and cache.
106 Say Y if you want support for the ARM9TDMI processor.
111 bool "Support ARM920T processor"
112 depends on ARCH_EP93XX || ARCH_INTEGRATOR || CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_IMX || ARCH_AAEC2000 || ARCH_AT91RM9200
113 default y if CPU_S3C2410 || CPU_S3C2440 || CPU_S3C2442 || ARCH_AT91RM9200
116 select CPU_CACHE_V4WT
117 select CPU_CACHE_VIVT
119 select CPU_COPY_V4WB if MMU
120 select CPU_TLB_V4WBI if MMU
122 The ARM920T is licensed to be produced by numerous vendors,
123 and is used in the Maverick EP9312 and the Samsung S3C2410.
125 More information on the Maverick EP9312 at
126 <http://linuxdevices.com/products/PD2382866068.html>.
128 Say Y if you want support for the ARM920T processor.
133 bool "Support ARM922T processor" if ARCH_INTEGRATOR
134 depends on ARCH_LH7A40X || ARCH_INTEGRATOR || ARCH_KS8695
135 default y if ARCH_LH7A40X || ARCH_KS8695
138 select CPU_CACHE_V4WT
139 select CPU_CACHE_VIVT
141 select CPU_COPY_V4WB if MMU
142 select CPU_TLB_V4WBI if MMU
144 The ARM922T is a version of the ARM920T, but with smaller
145 instruction and data caches. It is used in Altera's
146 Excalibur XA device family and Micrel's KS8695 Centaur.
148 Say Y if you want support for the ARM922T processor.
153 bool "Support ARM925T processor" if ARCH_OMAP1
154 depends on ARCH_OMAP15XX
155 default y if ARCH_OMAP15XX
158 select CPU_CACHE_V4WT
159 select CPU_CACHE_VIVT
161 select CPU_COPY_V4WB if MMU
162 select CPU_TLB_V4WBI if MMU
164 The ARM925T is a mix between the ARM920T and ARM926T, but with
165 different instruction and data caches. It is used in TI's OMAP
168 Say Y if you want support for the ARM925T processor.
173 bool "Support ARM926T processor"
174 depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_NS9XXX || ARCH_DAVINCI
175 default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_NS9XXX || ARCH_DAVINCI
177 select CPU_ABRT_EV5TJ
178 select CPU_CACHE_VIVT
180 select CPU_COPY_V4WB if MMU
181 select CPU_TLB_V4WBI if MMU
183 This is a variant of the ARM920. It has slightly different
184 instruction sequences for cache and TLB operations. Curiously,
185 there is no documentation on it at the ARM corporate website.
187 Say Y if you want support for the ARM926T processor.
192 bool "Support ARM940T processor" if ARCH_INTEGRATOR
195 select CPU_ABRT_NOMMU
196 select CPU_CACHE_VIVT
199 ARM940T is a member of the ARM9TDMI family of general-
200 purpose microprocessors with MPU and separate 4KB
201 instruction and 4KB data cases, each with a 4-word line
204 Say Y if you want support for the ARM940T processor.
209 bool "Support ARM946E-S processor" if ARCH_INTEGRATOR
212 select CPU_ABRT_NOMMU
213 select CPU_CACHE_VIVT
216 ARM946E-S is a member of the ARM9E-S family of high-
217 performance, 32-bit system-on-chip processor solutions.
218 The TCM and ARMv5TE 32-bit instruction set is supported.
220 Say Y if you want support for the ARM946E-S processor.
223 # ARM1020 - needs validating
225 bool "Support ARM1020T (rev 0) processor"
226 depends on ARCH_INTEGRATOR
229 select CPU_CACHE_V4WT
230 select CPU_CACHE_VIVT
232 select CPU_COPY_V4WB if MMU
233 select CPU_TLB_V4WBI if MMU
235 The ARM1020 is the 32K cached version of the ARM10 processor,
236 with an addition of a floating-point unit.
238 Say Y if you want support for the ARM1020 processor.
241 # ARM1020E - needs validating
243 bool "Support ARM1020E processor"
244 depends on ARCH_INTEGRATOR
247 select CPU_CACHE_V4WT
248 select CPU_CACHE_VIVT
250 select CPU_COPY_V4WB if MMU
251 select CPU_TLB_V4WBI if MMU
256 bool "Support ARM1022E processor"
257 depends on ARCH_INTEGRATOR
260 select CPU_CACHE_VIVT
262 select CPU_COPY_V4WB if MMU # can probably do better
263 select CPU_TLB_V4WBI if MMU
265 The ARM1022E is an implementation of the ARMv5TE architecture
266 based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
267 embedded trace macrocell, and a floating-point unit.
269 Say Y if you want support for the ARM1022E processor.
274 bool "Support ARM1026EJ-S processor"
275 depends on ARCH_INTEGRATOR
277 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
278 select CPU_CACHE_VIVT
280 select CPU_COPY_V4WB if MMU # can probably do better
281 select CPU_TLB_V4WBI if MMU
283 The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
284 based upon the ARM10 integer core.
286 Say Y if you want support for the ARM1026EJ-S processor.
291 bool "Support StrongARM(R) SA-110 processor" if !ARCH_EBSA110 && !FOOTBRIDGE && !ARCH_TBOX && !ARCH_SHARK && !ARCH_NEXUSPCI && ARCH_RPC
292 default y if ARCH_EBSA110 || FOOTBRIDGE || ARCH_TBOX || ARCH_SHARK || ARCH_NEXUSPCI
293 select CPU_32v3 if ARCH_RPC
294 select CPU_32v4 if !ARCH_RPC
296 select CPU_CACHE_V4WB
297 select CPU_CACHE_VIVT
299 select CPU_COPY_V4WB if MMU
300 select CPU_TLB_V4WB if MMU
302 The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
303 is available at five speeds ranging from 100 MHz to 233 MHz.
304 More information is available at
305 <http://developer.intel.com/design/strong/sa110.htm>.
307 Say Y if you want support for the SA-110 processor.
313 depends on ARCH_SA1100
317 select CPU_CACHE_V4WB
318 select CPU_CACHE_VIVT
320 select CPU_TLB_V4WB if MMU
325 depends on ARCH_IOP32X || ARCH_IOP33X || PXA25x || PXA27x || ARCH_IXP4XX || ARCH_IXP2000
329 select CPU_CACHE_VIVT
331 select CPU_TLB_V4WBI if MMU
333 # XScale Core Version 3
336 depends on ARCH_IXP23XX || ARCH_IOP13XX || PXA3xx
340 select CPU_CACHE_VIVT
342 select CPU_TLB_V4WBI if MMU
348 depends on ARCH_ORION
352 select CPU_CACHE_VIVT
354 select CPU_COPY_V4WB if MMU
355 select CPU_TLB_V4WBI if MMU
357 config CPU_FEROCEON_OLD_ID
358 bool "Accept early Feroceon cores with an ARM926 ID"
359 depends on CPU_FEROCEON && !CPU_ARM926T
362 This enables the usage of some old Feroceon cores
363 for which the CPU ID is equal to the ARM926 ID.
364 Relevant for Feroceon-1850 and early Feroceon-2850.
368 bool "Support ARM V6 processor"
369 depends on ARCH_INTEGRATOR || MACH_REALVIEW_EB || ARCH_OMAP2 || ARCH_MX3
370 default y if ARCH_MX3
374 select CPU_CACHE_VIPT
376 select CPU_HAS_ASID if MMU
377 select CPU_COPY_V6 if MMU
378 select CPU_TLB_V6 if MMU
382 bool "Support ARM V6K processor extensions" if !SMP
384 default y if SMP && !ARCH_MX3
386 Say Y here if your ARMv6 processor supports the 'K' extension.
387 This enables the kernel to use some instructions not present
388 on previous processors, and as such a kernel build with this
389 enabled will not boot on processors with do not support these
394 bool "Support ARM V7 processor"
395 depends on ARCH_INTEGRATOR
400 select CPU_CACHE_VIPT
402 select CPU_HAS_ASID if MMU
403 select CPU_COPY_V6 if MMU
404 select CPU_TLB_V7 if MMU
406 # Figure out what processor architecture version we should be using.
407 # This defines the compiler instruction set which depends on the machine type.
410 select TLS_REG_EMUL if SMP || !MMU
411 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
415 select TLS_REG_EMUL if SMP || !MMU
416 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
420 select TLS_REG_EMUL if SMP || !MMU
421 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
425 select TLS_REG_EMUL if SMP || !MMU
426 select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
430 select TLS_REG_EMUL if !CPU_32v6K && !MMU
436 config CPU_ABRT_NOMMU
451 config CPU_ABRT_EV5TJ
467 config CPU_CACHE_V4WT
470 config CPU_CACHE_V4WB
479 config CPU_CACHE_VIVT
482 config CPU_CACHE_VIPT
486 # The copy-page model
499 # This selects the TLB model
503 ARM Architecture Version 3 TLB.
508 ARM Architecture Version 4 TLB with writethrough cache.
513 ARM Architecture Version 4 TLB with writeback cache.
518 ARM Architecture Version 4 TLB with writeback cache and invalidate
519 instruction cache entry.
532 This indicates whether the CPU has the ASID register; used to
533 tag TLB and possibly cache entries.
538 Processor has the CP15 register.
544 Processor has the CP15 register, which has MMU related registers.
550 Processor has the CP15 register, which has MPU related registers.
553 # CPU supports 36-bit I/O
558 comment "Processor Features"
561 bool "Support Thumb user binaries"
562 depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6 || CPU_V7 || CPU_FEROCEON
565 Say Y if you want to include kernel support for running user space
568 The Thumb instruction set is a compressed form of the standard ARM
569 instruction set resulting in smaller binaries at the expense of
570 slightly less efficient code.
572 If you don't know what this all is, saying Y is a safe choice.
574 config CPU_BIG_ENDIAN
575 bool "Build big-endian kernel"
576 depends on ARCH_SUPPORTS_BIG_ENDIAN
578 Say Y if you plan on running a kernel in big-endian mode.
579 Note that your board must be properly built and your board
580 port must properly enable any big-endian related features
581 of your chipset/board/processor.
583 config CPU_HIGH_VECTOR
584 depends on !MMU && CPU_CP15 && !CPU_ARM740T
585 bool "Select the High exception vector"
588 Say Y here to select high exception vector(0xFFFF0000~).
589 The exception vector can be vary depending on the platform
590 design in nommu mode. If your platform needs to select
591 high exception vector, say Y.
592 Otherwise or if you are unsure, say N, and the low exception
593 vector (0x00000000~) will be used.
595 config CPU_ICACHE_DISABLE
596 bool "Disable I-Cache (I-bit)"
597 depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)
599 Say Y here to disable the processor instruction cache. Unless
600 you have a reason not to or are unsure, say N.
602 config CPU_DCACHE_DISABLE
603 bool "Disable D-Cache (C-bit)"
606 Say Y here to disable the processor data cache. Unless
607 you have a reason not to or are unsure, say N.
609 config CPU_DCACHE_SIZE
611 depends on CPU_ARM740T || CPU_ARM946E
612 default 0x00001000 if CPU_ARM740T
613 default 0x00002000 # default size for ARM946E-S
615 Some cores are synthesizable to have various sized cache. For
616 ARM946E-S case, it can vary from 0KB to 1MB.
617 To support such cache operations, it is efficient to know the size
619 If your SoC is configured to have a different size, define the value
620 here with proper conditions.
622 config CPU_DCACHE_WRITETHROUGH
623 bool "Force write through D-cache"
624 depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FEROCEON) && !CPU_DCACHE_DISABLE
625 default y if CPU_ARM925T
627 Say Y here to use the data cache in writethrough mode. Unless you
628 specifically require this or are unsure, say N.
630 config CPU_CACHE_ROUND_ROBIN
631 bool "Round robin I and D cache replacement algorithm"
632 depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
634 Say Y here to use the predictable round-robin cache replacement
635 policy. Unless you specifically require this or are unsure, say N.
637 config CPU_BPREDICT_DISABLE
638 bool "Disable branch prediction"
639 depends on CPU_ARM1020 || CPU_V6 || CPU_XSC3 || CPU_V7
641 Say Y here to disable branch prediction. If unsure, say N.
646 An SMP system using a pre-ARMv6 processor (there are apparently
647 a few prototypes like that in existence) and therefore access to
648 that required register must be emulated.
652 depends on !TLS_REG_EMUL
653 default y if SMP || CPU_32v7
655 This selects support for the CP15 thread register.
656 It is defined to be available on some ARMv6 processors (including
657 all SMP capable ARMv6's) or later processors. User space may
658 assume directly accessing that register and always obtain the
659 expected value only on ARMv7 and above.
661 config NEEDS_SYSCALL_FOR_CMPXCHG
664 SMP on a pre-ARMv6 processor? Well OK then.
665 Forget about fast user space cmpxchg support.
666 It is just not possible.