arch/arm/mach-vexpress/ct-ca9x4.c

   1 /*
   2  * Versatile Express Core Tile Cortex A9x4 Support
   3  */
   4 #include <linux/init.h>
   5 #include <linux/gfp.h>
   6 #include <linux/device.h>
   7 #include <linux/dma-mapping.h>
   8 #include <linux/platform_device.h>
   9 #include <linux/amba/bus.h>
  10 #include <linux/amba/clcd.h>
  11
  12 #include <asm/clkdev.h>
  13 #include <asm/pgtable.h>
  14 #include <asm/hardware/arm_timer.h>
  15 #include <asm/hardware/cache-l2x0.h>
  16 #include <asm/hardware/gic.h>
  17 #include <asm/mach-types.h>
  18 #include <asm/pmu.h>
  19 #include <asm/smp_twd.h>
  20
  21 #include <mach/clkdev.h>
  22 #include <mach/ct-ca9x4.h>
  23
  24 #include <plat/timer-sp.h>
  25
  26 #include <asm/mach/arch.h>
  27 #include <asm/mach/map.h>
  28 #include <asm/mach/time.h>
  29
  30 #include "core.h"
  31
  32 #include <mach/motherboard.h>
  33
  34 #define V2M_PA_CS7      0x10000000
  35
  36 static struct map_desc ct_ca9x4_io_desc[] __initdata = {
  37         {
  38                 .virtual        = __MMIO_P2V(CT_CA9X4_MPIC),
  39                 .pfn            = __phys_to_pfn(CT_CA9X4_MPIC),
  40                 .length         = SZ_16K,
  41                 .type           = MT_DEVICE,
  42         }, {
  43                 .virtual        = __MMIO_P2V(CT_CA9X4_SP804_TIMER),
  44                 .pfn            = __phys_to_pfn(CT_CA9X4_SP804_TIMER),
  45                 .length         = SZ_4K,
  46                 .type           = MT_DEVICE,
  47         }, {
  48                 .virtual        = __MMIO_P2V(CT_CA9X4_L2CC),
  49                 .pfn            = __phys_to_pfn(CT_CA9X4_L2CC),
  50                 .length         = SZ_4K,
  51                 .type           = MT_DEVICE,
  52         },
  53 };
  54
  55 static void __init ct_ca9x4_map_io(void)
  56 {
  57 #ifdef CONFIG_LOCAL_TIMERS
  58         twd_base = MMIO_P2V(A9_MPCORE_TWD);
  59 #endif
  60         v2m_map_io(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));
  61 }
  62
  63 static void __init ct_ca9x4_init_irq(void)
  64 {
  65         gic_init(0, 29, MMIO_P2V(A9_MPCORE_GIC_DIST),
  66                  MMIO_P2V(A9_MPCORE_GIC_CPU));
  67 }
  68
  69 #if 0
  70 static void __init ct_ca9x4_timer_init(void)
  71 {
  72         writel(0, MMIO_P2V(CT_CA9X4_TIMER0) + TIMER_CTRL);
  73         writel(0, MMIO_P2V(CT_CA9X4_TIMER1) + TIMER_CTRL);
  74
  75         sp804_clocksource_init(MMIO_P2V(CT_CA9X4_TIMER1));
  76         sp804_clockevents_init(MMIO_P2V(CT_CA9X4_TIMER0), IRQ_CT_CA9X4_TIMER0);
  77 }
  78
  79 static struct sys_timer ct_ca9x4_timer = {
  80         .init   = ct_ca9x4_timer_init,
  81 };
  82 #endif
  83
  84 static struct clcd_panel xvga_panel = {
  85         .mode           = {
  86                 .name           = "XVGA",
  87                 .refresh        = 60,
  88                 .xres           = 1024,
  89                 .yres           = 768,
  90                 .pixclock       = 15384,
  91                 .left_margin    = 168,
  92                 .right_margin   = 8,
  93                 .upper_margin   = 29,
  94                 .lower_margin   = 3,
  95                 .hsync_len      = 144,
  96                 .vsync_len      = 6,
  97                 .sync           = 0,
  98                 .vmode          = FB_VMODE_NONINTERLACED,
  99         },
 100         .width          = -1,
 101         .height         = -1,
 102         .tim2           = TIM2_BCD | TIM2_IPC,
 103         .cntl           = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1),
 104         .bpp            = 16,
 105 };
 106
 107 static void ct_ca9x4_clcd_enable(struct clcd_fb *fb)
 108 {
 109         v2m_cfg_write(SYS_CFG_MUXFPGA | SYS_CFG_SITE_DB1, 0);
 110         v2m_cfg_write(SYS_CFG_DVIMODE | SYS_CFG_SITE_DB1, 2);
 111 }
 112
 113 static int ct_ca9x4_clcd_setup(struct clcd_fb *fb)
 114 {
 115         unsigned long framesize = 1024 * 768 * 2;
 116         dma_addr_t dma;
 117
 118         fb->panel = &xvga_panel;
 119
 120         fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
 121                                 &dma, GFP_KERNEL);
 122         if (!fb->fb.screen_base) {
 123                 printk(KERN_ERR "CLCD: unable to map frame buffer\n");
 124                 return -ENOMEM;
 125         }
 126         fb->fb.fix.smem_start = dma;
 127         fb->fb.fix.smem_len = framesize;
 128
 129         return 0;
 130 }
 131
 132 static int ct_ca9x4_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
 133 {
 134         return dma_mmap_writecombine(&fb->dev->dev, vma, fb->fb.screen_base,
 135                 fb->fb.fix.smem_start, fb->fb.fix.smem_len);
 136 }
 137
 138 static void ct_ca9x4_clcd_remove(struct clcd_fb *fb)
 139 {
 140         dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
 141                 fb->fb.screen_base, fb->fb.fix.smem_start);
 142 }
 143
 144 static struct clcd_board ct_ca9x4_clcd_data = {
 145         .name           = "CT-CA9X4",
 146         .check          = clcdfb_check,
 147         .decode         = clcdfb_decode,
 148         .enable         = ct_ca9x4_clcd_enable,
 149         .setup          = ct_ca9x4_clcd_setup,
 150         .mmap           = ct_ca9x4_clcd_mmap,
 151         .remove         = ct_ca9x4_clcd_remove,
 152 };
 153
 154 static AMBA_DEVICE(clcd, "ct:clcd", CT_CA9X4_CLCDC, &ct_ca9x4_clcd_data);
 155 static AMBA_DEVICE(dmc, "ct:dmc", CT_CA9X4_DMC, NULL);
 156 static AMBA_DEVICE(smc, "ct:smc", CT_CA9X4_SMC, NULL);
 157 static AMBA_DEVICE(gpio, "ct:gpio", CT_CA9X4_GPIO, NULL);
 158
 159 static struct amba_device *ct_ca9x4_amba_devs[] __initdata = {
 160         &clcd_device,
 161         &dmc_device,
 162         &smc_device,
 163         &gpio_device,
 164 };
 165
 166
 167 static long ct_round(struct clk *clk, unsigned long rate)
 168 {
 169         return rate;
 170 }
 171
 172 static int ct_set(struct clk *clk, unsigned long rate)
 173 {
 174         return v2m_cfg_write(SYS_CFG_OSC | SYS_CFG_SITE_DB1 | 1, rate);
 175 }
 176
 177 static const struct clk_ops osc1_clk_ops = {
 178         .round  = ct_round,
 179         .set    = ct_set,
 180 };
 181
 182 static struct clk osc1_clk = {
 183         .ops    = &osc1_clk_ops,
 184         .rate   = 24000000,
 185 };
 186
 187 static struct clk_lookup lookups[] = {
 188         {       /* CLCD */
 189                 .dev_id         = "ct:clcd",
 190                 .clk            = &osc1_clk,
 191         },
 192 };
 193
 194 static struct resource pmu_resources[] = {
 195         [0] = {
 196                 .start  = IRQ_CT_CA9X4_PMU_CPU0,
 197                 .end    = IRQ_CT_CA9X4_PMU_CPU0,
 198                 .flags  = IORESOURCE_IRQ,
 199         },
 200         [1] = {
 201                 .start  = IRQ_CT_CA9X4_PMU_CPU1,
 202                 .end    = IRQ_CT_CA9X4_PMU_CPU1,
 203                 .flags  = IORESOURCE_IRQ,
 204         },
 205         [2] = {
 206                 .start  = IRQ_CT_CA9X4_PMU_CPU2,
 207                 .end    = IRQ_CT_CA9X4_PMU_CPU2,
 208                 .flags  = IORESOURCE_IRQ,
 209         },
 210         [3] = {
 211                 .start  = IRQ_CT_CA9X4_PMU_CPU3,
 212                 .end    = IRQ_CT_CA9X4_PMU_CPU3,
 213                 .flags  = IORESOURCE_IRQ,
 214         },
 215 };
 216
 217 static struct platform_device pmu_device = {
 218         .name           = "arm-pmu",
 219         .id             = ARM_PMU_DEVICE_CPU,
 220         .num_resources  = ARRAY_SIZE(pmu_resources),
 221         .resource       = pmu_resources,
 222 };
 223
 224 static void __init ct_ca9x4_init(void)
 225 {
 226         int i;
 227
 228 #ifdef CONFIG_CACHE_L2X0
 229         void __iomem *l2x0_base = MMIO_P2V(CT_CA9X4_L2CC);
 230
 231         /* set RAM latencies to 1 cycle for this core tile. */
 232         writel(0, l2x0_base + L2X0_TAG_LATENCY_CTRL);
 233         writel(0, l2x0_base + L2X0_DATA_LATENCY_CTRL);
 234
 235         l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff);
 236 #endif
 237
 238         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 239
 240         for (i = 0; i < ARRAY_SIZE(ct_ca9x4_amba_devs); i++)
 241                 amba_device_register(ct_ca9x4_amba_devs[i], &iomem_resource);
 242
 243         platform_device_register(&pmu_device);
 244 }
 245
 246 MACHINE_START(VEXPRESS, "ARM-Versatile Express CA9x4")
 247         .boot_params    = PHYS_OFFSET + 0x00000100,
 248         .map_io         = ct_ca9x4_map_io,
 249         .init_irq       = ct_ca9x4_init_irq,
 250 #if 0
 251         .timer          = &ct_ca9x4_timer,
 252 #else
 253         .timer          = &v2m_timer,
 254 #endif
 255         .init_machine   = ct_ca9x4_init,
 256 MACHINE_END