2 * linux/arch/arm/mach-versatile/core.c
4 * Copyright (C) 1999 - 2003 ARM Limited
5 * Copyright (C) 2000 Deep Blue Solutions Ltd
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #include <linux/init.h>
22 #include <linux/device.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/platform_device.h>
25 #include <linux/interrupt.h>
26 #include <linux/irqdomain.h>
27 #include <linux/of_address.h>
28 #include <linux/of_platform.h>
29 #include <linux/amba/bus.h>
30 #include <linux/amba/clcd.h>
31 #include <linux/amba/pl061.h>
32 #include <linux/amba/mmci.h>
33 #include <linux/amba/pl022.h>
35 #include <linux/gfp.h>
36 #include <linux/clkdev.h>
37 #include <linux/mtd/physmap.h>
40 #include <asm/hardware/arm_timer.h>
41 #include <asm/hardware/icst.h>
42 #include <asm/hardware/vic.h>
43 #include <asm/mach-types.h>
45 #include <asm/mach/arch.h>
46 #include <asm/mach/irq.h>
47 #include <asm/mach/time.h>
48 #include <asm/mach/map.h>
49 #include <mach/hardware.h>
50 #include <mach/platform.h>
51 #include <asm/hardware/timer-sp.h>
53 #include <plat/clcd.h>
54 #include <plat/fpga-irq.h>
55 #include <plat/sched_clock.h>
60 * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
63 * Setup a VA for the Versatile Vectored Interrupt Controller.
65 #define VA_VIC_BASE __io_address(VERSATILE_VIC_BASE)
66 #define VA_SIC_BASE __io_address(VERSATILE_SIC_BASE)
69 #define IRQ_MMCI0A IRQ_VICSOURCE22
70 #define IRQ_AACI IRQ_VICSOURCE24
71 #define IRQ_ETH IRQ_VICSOURCE25
72 #define PIC_MASK 0xFFD00000
74 #define IRQ_MMCI0A IRQ_SIC_MMCI0A
75 #define IRQ_AACI IRQ_SIC_AACI
76 #define IRQ_ETH IRQ_SIC_ETH
80 /* Lookup table for finding a DT node that represents the vic instance */
81 static const struct of_device_id vic_of_match[] __initconst = {
82 { .compatible = "arm,versatile-vic", },
86 static const struct of_device_id sic_of_match[] __initconst = {
87 { .compatible = "arm,versatile-sic", },
91 void __init versatile_init_irq(void)
93 struct device_node *np;
95 np = of_find_matching_node_by_address(NULL, vic_of_match,
97 __vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0, 0, np);
99 writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
101 np = of_find_matching_node_by_address(NULL, sic_of_match,
104 fpga_irq_init(VA_SIC_BASE, "SIC", IRQ_SIC_START,
105 IRQ_VICSOURCE31, ~PIC_MASK, np);
108 * Interrupts on secondary controller from 0 to 8 are routed to
110 * Interrupts from 21 to 31 are routed directly to the VIC on
111 * the corresponding number on primary controller. This is controlled
112 * by setting PIC_ENABLEx.
114 writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE);
117 static struct map_desc versatile_io_desc[] __initdata = {
119 .virtual = IO_ADDRESS(VERSATILE_SYS_BASE),
120 .pfn = __phys_to_pfn(VERSATILE_SYS_BASE),
124 .virtual = IO_ADDRESS(VERSATILE_SIC_BASE),
125 .pfn = __phys_to_pfn(VERSATILE_SIC_BASE),
129 .virtual = IO_ADDRESS(VERSATILE_VIC_BASE),
130 .pfn = __phys_to_pfn(VERSATILE_VIC_BASE),
134 .virtual = IO_ADDRESS(VERSATILE_SCTL_BASE),
135 .pfn = __phys_to_pfn(VERSATILE_SCTL_BASE),
139 #ifdef CONFIG_MACH_VERSATILE_AB
141 .virtual = IO_ADDRESS(VERSATILE_IB2_BASE),
142 .pfn = __phys_to_pfn(VERSATILE_IB2_BASE),
147 #ifdef CONFIG_DEBUG_LL
149 .virtual = IO_ADDRESS(VERSATILE_UART0_BASE),
150 .pfn = __phys_to_pfn(VERSATILE_UART0_BASE),
157 .virtual = IO_ADDRESS(VERSATILE_PCI_CORE_BASE),
158 .pfn = __phys_to_pfn(VERSATILE_PCI_CORE_BASE),
162 .virtual = (unsigned long)VERSATILE_PCI_VIRT_BASE,
163 .pfn = __phys_to_pfn(VERSATILE_PCI_BASE),
164 .length = VERSATILE_PCI_BASE_SIZE,
167 .virtual = (unsigned long)VERSATILE_PCI_CFG_VIRT_BASE,
168 .pfn = __phys_to_pfn(VERSATILE_PCI_CFG_BASE),
169 .length = VERSATILE_PCI_CFG_BASE_SIZE,
172 .virtual = (unsigned long)VERSATILE_PCI_VIRT_MEM_BASE0,
173 .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE0),
174 .length = IO_SPACE_LIMIT,
180 void __init versatile_map_io(void)
182 iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc));
186 #define VERSATILE_FLASHCTRL (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
188 static void versatile_flash_set_vpp(struct platform_device *pdev, int on)
192 val = __raw_readl(VERSATILE_FLASHCTRL);
194 val |= VERSATILE_FLASHPROG_FLVPPEN;
196 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
197 __raw_writel(val, VERSATILE_FLASHCTRL);
200 static struct physmap_flash_data versatile_flash_data = {
202 .set_vpp = versatile_flash_set_vpp,
205 static struct resource versatile_flash_resource = {
206 .start = VERSATILE_FLASH_BASE,
207 .end = VERSATILE_FLASH_BASE + VERSATILE_FLASH_SIZE - 1,
208 .flags = IORESOURCE_MEM,
211 static struct platform_device versatile_flash_device = {
212 .name = "physmap-flash",
215 .platform_data = &versatile_flash_data,
218 .resource = &versatile_flash_resource,
221 static struct resource smc91x_resources[] = {
223 .start = VERSATILE_ETH_BASE,
224 .end = VERSATILE_ETH_BASE + SZ_64K - 1,
225 .flags = IORESOURCE_MEM,
230 .flags = IORESOURCE_IRQ,
234 static struct platform_device smc91x_device = {
237 .num_resources = ARRAY_SIZE(smc91x_resources),
238 .resource = smc91x_resources,
241 static struct resource versatile_i2c_resource = {
242 .start = VERSATILE_I2C_BASE,
243 .end = VERSATILE_I2C_BASE + SZ_4K - 1,
244 .flags = IORESOURCE_MEM,
247 static struct platform_device versatile_i2c_device = {
248 .name = "versatile-i2c",
251 .resource = &versatile_i2c_resource,
254 static struct i2c_board_info versatile_i2c_board_info[] = {
256 I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
260 static int __init versatile_i2c_init(void)
262 return i2c_register_board_info(0, versatile_i2c_board_info,
263 ARRAY_SIZE(versatile_i2c_board_info));
265 arch_initcall(versatile_i2c_init);
267 #define VERSATILE_SYSMCI (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET)
269 unsigned int mmc_status(struct device *dev)
271 struct amba_device *adev = container_of(dev, struct amba_device, dev);
274 if (adev->res.start == VERSATILE_MMCI0_BASE)
279 return readl(VERSATILE_SYSMCI) & mask;
282 static struct mmci_platform_data mmc0_plat_data = {
283 .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
284 .status = mmc_status,
289 static struct resource char_lcd_resources[] = {
291 .start = VERSATILE_CHAR_LCD_BASE,
292 .end = (VERSATILE_CHAR_LCD_BASE + SZ_4K - 1),
293 .flags = IORESOURCE_MEM,
297 static struct platform_device char_lcd_device = {
298 .name = "arm-charlcd",
300 .num_resources = ARRAY_SIZE(char_lcd_resources),
301 .resource = char_lcd_resources,
307 static const struct icst_params versatile_oscvco_params = {
309 .vco_max = ICST307_VCO_MAX,
310 .vco_min = ICST307_VCO_MIN,
315 .s2div = icst307_s2div,
316 .idx2s = icst307_idx2s,
319 static void versatile_oscvco_set(struct clk *clk, struct icst_vco vco)
321 void __iomem *sys_lock = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LOCK_OFFSET;
324 val = readl(clk->vcoreg) & ~0x7ffff;
325 val |= vco.v | (vco.r << 9) | (vco.s << 16);
327 writel(0xa05f, sys_lock);
328 writel(val, clk->vcoreg);
332 static const struct clk_ops osc4_clk_ops = {
333 .round = icst_clk_round,
335 .setvco = versatile_oscvco_set,
338 static struct clk osc4_clk = {
339 .ops = &osc4_clk_ops,
340 .params = &versatile_oscvco_params,
344 * These are fixed clocks.
346 static struct clk ref24_clk = {
350 static struct clk sp804_clk = {
354 static struct clk dummy_apb_pclk;
356 static struct clk_lookup lookups[] = {
357 { /* AMBA bus clock */
358 .con_id = "apb_pclk",
359 .clk = &dummy_apb_pclk,
390 }, { /* SP804 timers */
399 #define SYS_CLCD_MODE_MASK (3 << 0)
400 #define SYS_CLCD_MODE_888 (0 << 0)
401 #define SYS_CLCD_MODE_5551 (1 << 0)
402 #define SYS_CLCD_MODE_565_RLSB (2 << 0)
403 #define SYS_CLCD_MODE_565_BLSB (3 << 0)
404 #define SYS_CLCD_NLCDIOON (1 << 2)
405 #define SYS_CLCD_VDDPOSSWITCH (1 << 3)
406 #define SYS_CLCD_PWR3V5SWITCH (1 << 4)
407 #define SYS_CLCD_ID_MASK (0x1f << 8)
408 #define SYS_CLCD_ID_SANYO_3_8 (0x00 << 8)
409 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
410 #define SYS_CLCD_ID_EPSON_2_2 (0x02 << 8)
411 #define SYS_CLCD_ID_SANYO_2_5 (0x07 << 8)
412 #define SYS_CLCD_ID_VGA (0x1f << 8)
414 static bool is_sanyo_2_5_lcd;
417 * Disable all display connectors on the interface module.
419 static void versatile_clcd_disable(struct clcd_fb *fb)
421 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
424 val = readl(sys_clcd);
425 val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
426 writel(val, sys_clcd);
428 #ifdef CONFIG_MACH_VERSATILE_AB
430 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off
432 if (machine_is_versatile_ab() && is_sanyo_2_5_lcd) {
433 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
436 ctrl = readl(versatile_ib2_ctrl);
438 writel(ctrl, versatile_ib2_ctrl);
444 * Enable the relevant connector on the interface module.
446 static void versatile_clcd_enable(struct clcd_fb *fb)
448 struct fb_var_screeninfo *var = &fb->fb.var;
449 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
452 val = readl(sys_clcd);
453 val &= ~SYS_CLCD_MODE_MASK;
455 switch (var->green.length) {
457 val |= SYS_CLCD_MODE_5551;
460 if (var->red.offset == 0)
461 val |= SYS_CLCD_MODE_565_RLSB;
463 val |= SYS_CLCD_MODE_565_BLSB;
466 val |= SYS_CLCD_MODE_888;
473 writel(val, sys_clcd);
476 * And now enable the PSUs
478 val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
479 writel(val, sys_clcd);
481 #ifdef CONFIG_MACH_VERSATILE_AB
483 * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on
485 if (machine_is_versatile_ab() && is_sanyo_2_5_lcd) {
486 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
489 ctrl = readl(versatile_ib2_ctrl);
491 writel(ctrl, versatile_ib2_ctrl);
497 * Detect which LCD panel is connected, and return the appropriate
498 * clcd_panel structure. Note: we do not have any information on
499 * the required timings for the 8.4in panel, so we presently assume
502 static int versatile_clcd_setup(struct clcd_fb *fb)
504 void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
505 const char *panel_name;
508 is_sanyo_2_5_lcd = false;
510 val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
511 if (val == SYS_CLCD_ID_SANYO_3_8)
512 panel_name = "Sanyo TM38QV67A02A";
513 else if (val == SYS_CLCD_ID_SANYO_2_5) {
514 panel_name = "Sanyo QVGA Portrait";
515 is_sanyo_2_5_lcd = true;
516 } else if (val == SYS_CLCD_ID_EPSON_2_2)
517 panel_name = "Epson L2F50113T00";
518 else if (val == SYS_CLCD_ID_VGA)
521 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
526 fb->panel = versatile_clcd_get_panel(panel_name);
530 return versatile_clcd_setup_dma(fb, SZ_1M);
533 static void versatile_clcd_decode(struct clcd_fb *fb, struct clcd_regs *regs)
535 clcdfb_decode(fb, regs);
537 /* Always clear BGR for RGB565: we do the routing externally */
538 if (fb->fb.var.green.length == 6)
539 regs->cntl &= ~CNTL_BGR;
542 static struct clcd_board clcd_plat_data = {
544 .caps = CLCD_CAP_5551 | CLCD_CAP_565 | CLCD_CAP_888,
545 .check = clcdfb_check,
546 .decode = versatile_clcd_decode,
547 .disable = versatile_clcd_disable,
548 .enable = versatile_clcd_enable,
549 .setup = versatile_clcd_setup,
550 .mmap = versatile_clcd_mmap_dma,
551 .remove = versatile_clcd_remove_dma,
554 static struct pl061_platform_data gpio0_plat_data = {
556 .irq_base = IRQ_GPIO0_START,
559 static struct pl061_platform_data gpio1_plat_data = {
561 .irq_base = IRQ_GPIO1_START,
564 static struct pl022_ssp_controller ssp0_plat_data = {
570 #define AACI_IRQ { IRQ_AACI }
571 #define MMCI0_IRQ { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
572 #define KMI0_IRQ { IRQ_SIC_KMI0 }
573 #define KMI1_IRQ { IRQ_SIC_KMI1 }
576 * These devices are connected directly to the multi-layer AHB switch
580 #define CLCD_IRQ { IRQ_CLCDINT }
581 #define DMAC_IRQ { IRQ_DMAINT }
584 * These devices are connected via the core APB bridge
587 #define WATCHDOG_IRQ { IRQ_WDOGINT }
588 #define GPIO0_IRQ { IRQ_GPIOINT0 }
589 #define GPIO1_IRQ { IRQ_GPIOINT1 }
590 #define RTC_IRQ { IRQ_RTCINT }
593 * These devices are connected via the DMA APB bridge
595 #define SCI_IRQ { IRQ_SCIINT }
596 #define UART0_IRQ { IRQ_UARTINT0 }
597 #define UART1_IRQ { IRQ_UARTINT1 }
598 #define UART2_IRQ { IRQ_UARTINT2 }
599 #define SSP_IRQ { IRQ_SSPINT }
601 /* FPGA Primecells */
602 APB_DEVICE(aaci, "fpga:04", AACI, NULL);
603 APB_DEVICE(mmc0, "fpga:05", MMCI0, &mmc0_plat_data);
604 APB_DEVICE(kmi0, "fpga:06", KMI0, NULL);
605 APB_DEVICE(kmi1, "fpga:07", KMI1, NULL);
607 /* DevChip Primecells */
608 AHB_DEVICE(smc, "dev:00", SMC, NULL);
609 AHB_DEVICE(mpmc, "dev:10", MPMC, NULL);
610 AHB_DEVICE(clcd, "dev:20", CLCD, &clcd_plat_data);
611 AHB_DEVICE(dmac, "dev:30", DMAC, NULL);
612 APB_DEVICE(sctl, "dev:e0", SCTL, NULL);
613 APB_DEVICE(wdog, "dev:e1", WATCHDOG, NULL);
614 APB_DEVICE(gpio0, "dev:e4", GPIO0, &gpio0_plat_data);
615 APB_DEVICE(gpio1, "dev:e5", GPIO1, &gpio1_plat_data);
616 APB_DEVICE(rtc, "dev:e8", RTC, NULL);
617 APB_DEVICE(sci0, "dev:f0", SCI, NULL);
618 APB_DEVICE(uart0, "dev:f1", UART0, NULL);
619 APB_DEVICE(uart1, "dev:f2", UART1, NULL);
620 APB_DEVICE(uart2, "dev:f3", UART2, NULL);
621 APB_DEVICE(ssp0, "dev:f4", SSP, &ssp0_plat_data);
623 static struct amba_device *amba_devs[] __initdata = {
646 * Lookup table for attaching a specific name and platform_data pointer to
647 * devices as they get created by of_platform_populate(). Ideally this table
648 * would not exist, but the current clock implementation depends on some devices
649 * having a specific name.
651 struct of_dev_auxdata versatile_auxdata_lookup[] __initdata = {
652 OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI0_BASE, "fpga:05", &mmc0_plat_data),
653 OF_DEV_AUXDATA("arm,primecell", VERSATILE_KMI0_BASE, "fpga:06", NULL),
654 OF_DEV_AUXDATA("arm,primecell", VERSATILE_KMI1_BASE, "fpga:07", NULL),
655 OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART3_BASE, "fpga:09", NULL),
656 /* FIXME: this is buggy, the platform data is needed for this MMC instance too */
657 OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI1_BASE, "fpga:0b", NULL),
659 OF_DEV_AUXDATA("arm,primecell", VERSATILE_CLCD_BASE, "dev:20", &clcd_plat_data),
660 OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART0_BASE, "dev:f1", NULL),
661 OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART1_BASE, "dev:f2", NULL),
662 OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART2_BASE, "dev:f3", NULL),
663 OF_DEV_AUXDATA("arm,primecell", VERSATILE_SSP_BASE, "dev:f4", &ssp0_plat_data),
667 * These entries are unnecessary because no clocks referencing
668 * them. I've left them in for now as place holders in case
669 * any of them need to be added back, but they should be
670 * removed before actually committing this patch. --gcl
672 OF_DEV_AUXDATA("arm,primecell", VERSATILE_AACI_BASE, "fpga:04", NULL),
673 OF_DEV_AUXDATA("arm,primecell", VERSATILE_SCI1_BASE, "fpga:0a", NULL),
674 OF_DEV_AUXDATA("arm,primecell", VERSATILE_SMC_BASE, "dev:00", NULL),
675 OF_DEV_AUXDATA("arm,primecell", VERSATILE_MPMC_BASE, "dev:10", NULL),
676 OF_DEV_AUXDATA("arm,primecell", VERSATILE_DMAC_BASE, "dev:30", NULL),
678 OF_DEV_AUXDATA("arm,primecell", VERSATILE_SCTL_BASE, "dev:e0", NULL),
679 OF_DEV_AUXDATA("arm,primecell", VERSATILE_WATCHDOG_BASE, "dev:e1", NULL),
680 OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO0_BASE, "dev:e4", NULL),
681 OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO1_BASE, "dev:e5", NULL),
682 OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO2_BASE, "dev:e6", NULL),
683 OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO3_BASE, "dev:e7", NULL),
684 OF_DEV_AUXDATA("arm,primecell", VERSATILE_RTC_BASE, "dev:e8", NULL),
685 OF_DEV_AUXDATA("arm,primecell", VERSATILE_SCI_BASE, "dev:f0", NULL),
692 #define VA_LEDS_BASE (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
694 static void versatile_leds_event(led_event_t ledevt)
699 local_irq_save(flags);
700 val = readl(VA_LEDS_BASE);
704 val = val & ~VERSATILE_SYS_LED0;
708 val = val | VERSATILE_SYS_LED0;
712 val = val ^ VERSATILE_SYS_LED1;
723 writel(val, VA_LEDS_BASE);
724 local_irq_restore(flags);
726 #endif /* CONFIG_LEDS */
728 void versatile_restart(char mode, const char *cmd)
730 void __iomem *sys = __io_address(VERSATILE_SYS_BASE);
733 val = __raw_readl(sys + VERSATILE_SYS_RESETCTL_OFFSET);
736 __raw_writel(0xa05f, sys + VERSATILE_SYS_LOCK_OFFSET);
737 __raw_writel(val, sys + VERSATILE_SYS_RESETCTL_OFFSET);
738 __raw_writel(0, sys + VERSATILE_SYS_LOCK_OFFSET);
741 /* Early initializations */
742 void __init versatile_init_early(void)
744 void __iomem *sys = __io_address(VERSATILE_SYS_BASE);
746 osc4_clk.vcoreg = sys + VERSATILE_SYS_OSCCLCD_OFFSET;
747 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
749 versatile_sched_clock_init(sys + VERSATILE_SYS_24MHz_OFFSET, 24000000);
752 void __init versatile_init(void)
756 platform_device_register(&versatile_flash_device);
757 platform_device_register(&versatile_i2c_device);
758 platform_device_register(&smc91x_device);
759 platform_device_register(&char_lcd_device);
761 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
762 struct amba_device *d = amba_devs[i];
763 amba_device_register(d, &iomem_resource);
768 * Where is the timer (VA)?
770 #define TIMER0_VA_BASE __io_address(VERSATILE_TIMER0_1_BASE)
771 #define TIMER1_VA_BASE (__io_address(VERSATILE_TIMER0_1_BASE) + 0x20)
772 #define TIMER2_VA_BASE __io_address(VERSATILE_TIMER2_3_BASE)
773 #define TIMER3_VA_BASE (__io_address(VERSATILE_TIMER2_3_BASE) + 0x20)
776 * Set up timer interrupt, and return the current time in seconds.
778 static void __init versatile_timer_init(void)
783 * set clock frequency:
784 * VERSATILE_REFCLK is 32KHz
785 * VERSATILE_TIMCLK is 1MHz
787 val = readl(__io_address(VERSATILE_SCTL_BASE));
788 writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) |
789 (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
790 (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) |
791 (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val,
792 __io_address(VERSATILE_SCTL_BASE));
795 * Initialise to a known state (all timers off)
797 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
798 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
799 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
800 writel(0, TIMER3_VA_BASE + TIMER_CTRL);
802 sp804_clocksource_init(TIMER3_VA_BASE, "timer3");
803 sp804_clockevents_init(TIMER0_VA_BASE, IRQ_TIMERINT0_1, "timer0");
806 struct sys_timer versatile_timer = {
807 .init = versatile_timer_init,