arch/arm/mach-versatile/core.c

   1 /*
   2  *  linux/arch/arm/mach-versatile/core.c
   3  *
   4  *  Copyright (C) 1999 - 2003 ARM Limited
   5  *  Copyright (C) 2000 Deep Blue Solutions Ltd
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21 #include <linux/init.h>
  22 #include <linux/device.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/sysdev.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/amba/bus.h>
  28 #include <linux/amba/clcd.h>
  29 #include <linux/amba/pl061.h>
  30 #include <linux/amba/mmci.h>
  31 #include <linux/amba/pl022.h>
  32 #include <linux/io.h>
  33 #include <linux/gfp.h>
  34 #include <linux/clkdev.h>
  35
  36 #include <asm/system.h>
  37 #include <asm/irq.h>
  38 #include <asm/leds.h>
  39 #include <asm/hardware/arm_timer.h>
  40 #include <asm/hardware/icst.h>
  41 #include <asm/hardware/vic.h>
  42 #include <asm/mach-types.h>
  43
  44 #include <asm/mach/arch.h>
  45 #include <asm/mach/flash.h>
  46 #include <asm/mach/irq.h>
  47 #include <asm/mach/time.h>
  48 #include <asm/mach/map.h>
  49 #include <mach/hardware.h>
  50 #include <mach/platform.h>
  51 #include <asm/hardware/timer-sp.h>
  52
  53 #include <plat/clcd.h>
  54 #include <plat/sched_clock.h>
  55
  56 #include "core.h"
  57
  58 /*
  59  * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
  60  * is the (PA >> 12).
  61  *
  62  * Setup a VA for the Versatile Vectored Interrupt Controller.
  63  */
  64 #define VA_VIC_BASE             __io_address(VERSATILE_VIC_BASE)
  65 #define VA_SIC_BASE             __io_address(VERSATILE_SIC_BASE)
  66
  67 static void sic_mask_irq(struct irq_data *d)
  68 {
  69         unsigned int irq = d->irq - IRQ_SIC_START;
  70
  71         writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
  72 }
  73
  74 static void sic_unmask_irq(struct irq_data *d)
  75 {
  76         unsigned int irq = d->irq - IRQ_SIC_START;
  77
  78         writel(1 << irq, VA_SIC_BASE + SIC_IRQ_ENABLE_SET);
  79 }
  80
  81 static struct irq_chip sic_chip = {
  82         .name           = "SIC",
  83         .irq_ack        = sic_mask_irq,
  84         .irq_mask       = sic_mask_irq,
  85         .irq_unmask     = sic_unmask_irq,
  86 };
  87
  88 static void
  89 sic_handle_irq(unsigned int irq, struct irq_desc *desc)
  90 {
  91         unsigned long status = readl(VA_SIC_BASE + SIC_IRQ_STATUS);
  92
  93         if (status == 0) {
  94                 do_bad_IRQ(irq, desc);
  95                 return;
  96         }
  97
  98         do {
  99                 irq = ffs(status) - 1;
 100                 status &= ~(1 << irq);
 101
 102                 irq += IRQ_SIC_START;
 103
 104                 generic_handle_irq(irq);
 105         } while (status);
 106 }
 107
 108 #if 1
 109 #define IRQ_MMCI0A      IRQ_VICSOURCE22
 110 #define IRQ_AACI        IRQ_VICSOURCE24
 111 #define IRQ_ETH         IRQ_VICSOURCE25
 112 #define PIC_MASK        0xFFD00000
 113 #else
 114 #define IRQ_MMCI0A      IRQ_SIC_MMCI0A
 115 #define IRQ_AACI        IRQ_SIC_AACI
 116 #define IRQ_ETH         IRQ_SIC_ETH
 117 #define PIC_MASK        0
 118 #endif
 119
 120 void __init versatile_init_irq(void)
 121 {
 122         unsigned int i;
 123
 124         vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0, 0);
 125
 126         set_irq_chained_handler(IRQ_VICSOURCE31, sic_handle_irq);
 127
 128         /* Do second interrupt controller */
 129         writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
 130
 131         for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
 132                 if ((PIC_MASK & (1 << (i - IRQ_SIC_START))) == 0) {
 133                         set_irq_chip(i, &sic_chip);
 134                         set_irq_handler(i, handle_level_irq);
 135                         set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
 136                 }
 137         }
 138
 139         /*
 140          * Interrupts on secondary controller from 0 to 8 are routed to
 141          * source 31 on PIC.
 142          * Interrupts from 21 to 31 are routed directly to the VIC on
 143          * the corresponding number on primary controller. This is controlled
 144          * by setting PIC_ENABLEx.
 145          */
 146         writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE);
 147 }
 148
 149 static struct map_desc versatile_io_desc[] __initdata = {
 150         {
 151                 .virtual        =  IO_ADDRESS(VERSATILE_SYS_BASE),
 152                 .pfn            = __phys_to_pfn(VERSATILE_SYS_BASE),
 153                 .length         = SZ_4K,
 154                 .type           = MT_DEVICE
 155         }, {
 156                 .virtual        =  IO_ADDRESS(VERSATILE_SIC_BASE),
 157                 .pfn            = __phys_to_pfn(VERSATILE_SIC_BASE),
 158                 .length         = SZ_4K,
 159                 .type           = MT_DEVICE
 160         }, {
 161                 .virtual        =  IO_ADDRESS(VERSATILE_VIC_BASE),
 162                 .pfn            = __phys_to_pfn(VERSATILE_VIC_BASE),
 163                 .length         = SZ_4K,
 164                 .type           = MT_DEVICE
 165         }, {
 166                 .virtual        =  IO_ADDRESS(VERSATILE_SCTL_BASE),
 167                 .pfn            = __phys_to_pfn(VERSATILE_SCTL_BASE),
 168                 .length         = SZ_4K * 9,
 169                 .type           = MT_DEVICE
 170         },
 171 #ifdef CONFIG_MACH_VERSATILE_AB
 172         {
 173                 .virtual        =  IO_ADDRESS(VERSATILE_GPIO0_BASE),
 174                 .pfn            = __phys_to_pfn(VERSATILE_GPIO0_BASE),
 175                 .length         = SZ_4K,
 176                 .type           = MT_DEVICE
 177         }, {
 178                 .virtual        =  IO_ADDRESS(VERSATILE_IB2_BASE),
 179                 .pfn            = __phys_to_pfn(VERSATILE_IB2_BASE),
 180                 .length         = SZ_64M,
 181                 .type           = MT_DEVICE
 182         },
 183 #endif
 184 #ifdef CONFIG_DEBUG_LL
 185         {
 186                 .virtual        =  IO_ADDRESS(VERSATILE_UART0_BASE),
 187                 .pfn            = __phys_to_pfn(VERSATILE_UART0_BASE),
 188                 .length         = SZ_4K,
 189                 .type           = MT_DEVICE
 190         },
 191 #endif
 192 #ifdef CONFIG_PCI
 193         {
 194                 .virtual        =  IO_ADDRESS(VERSATILE_PCI_CORE_BASE),
 195                 .pfn            = __phys_to_pfn(VERSATILE_PCI_CORE_BASE),
 196                 .length         = SZ_4K,
 197                 .type           = MT_DEVICE
 198         }, {
 199                 .virtual        =  (unsigned long)VERSATILE_PCI_VIRT_BASE,
 200                 .pfn            = __phys_to_pfn(VERSATILE_PCI_BASE),
 201                 .length         = VERSATILE_PCI_BASE_SIZE,
 202                 .type           = MT_DEVICE
 203         }, {
 204                 .virtual        =  (unsigned long)VERSATILE_PCI_CFG_VIRT_BASE,
 205                 .pfn            = __phys_to_pfn(VERSATILE_PCI_CFG_BASE),
 206                 .length         = VERSATILE_PCI_CFG_BASE_SIZE,
 207                 .type           = MT_DEVICE
 208         },
 209 #if 0
 210         {
 211                 .virtual        =  VERSATILE_PCI_VIRT_MEM_BASE0,
 212                 .pfn            = __phys_to_pfn(VERSATILE_PCI_MEM_BASE0),
 213                 .length         = SZ_16M,
 214                 .type           = MT_DEVICE
 215         }, {
 216                 .virtual        =  VERSATILE_PCI_VIRT_MEM_BASE1,
 217                 .pfn            = __phys_to_pfn(VERSATILE_PCI_MEM_BASE1),
 218                 .length         = SZ_16M,
 219                 .type           = MT_DEVICE
 220         }, {
 221                 .virtual        =  VERSATILE_PCI_VIRT_MEM_BASE2,
 222                 .pfn            = __phys_to_pfn(VERSATILE_PCI_MEM_BASE2),
 223                 .length         = SZ_16M,
 224                 .type           = MT_DEVICE
 225         },
 226 #endif
 227 #endif
 228 };
 229
 230 void __init versatile_map_io(void)
 231 {
 232         iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc));
 233 }
 234
 235
 236 #define VERSATILE_FLASHCTRL    (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
 237
 238 static int versatile_flash_init(void)
 239 {
 240         u32 val;
 241
 242         val = __raw_readl(VERSATILE_FLASHCTRL);
 243         val &= ~VERSATILE_FLASHPROG_FLVPPEN;
 244         __raw_writel(val, VERSATILE_FLASHCTRL);
 245
 246         return 0;
 247 }
 248
 249 static void versatile_flash_exit(void)
 250 {
 251         u32 val;
 252
 253         val = __raw_readl(VERSATILE_FLASHCTRL);
 254         val &= ~VERSATILE_FLASHPROG_FLVPPEN;
 255         __raw_writel(val, VERSATILE_FLASHCTRL);
 256 }
 257
 258 static void versatile_flash_set_vpp(int on)
 259 {
 260         u32 val;
 261
 262         val = __raw_readl(VERSATILE_FLASHCTRL);
 263         if (on)
 264                 val |= VERSATILE_FLASHPROG_FLVPPEN;
 265         else
 266                 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
 267         __raw_writel(val, VERSATILE_FLASHCTRL);
 268 }
 269
 270 static struct flash_platform_data versatile_flash_data = {
 271         .map_name               = "cfi_probe",
 272         .width                  = 4,
 273         .init                   = versatile_flash_init,
 274         .exit                   = versatile_flash_exit,
 275         .set_vpp                = versatile_flash_set_vpp,
 276 };
 277
 278 static struct resource versatile_flash_resource = {
 279         .start                  = VERSATILE_FLASH_BASE,
 280         .end                    = VERSATILE_FLASH_BASE + VERSATILE_FLASH_SIZE - 1,
 281         .flags                  = IORESOURCE_MEM,
 282 };
 283
 284 static struct platform_device versatile_flash_device = {
 285         .name                   = "armflash",
 286         .id                     = 0,
 287         .dev                    = {
 288                 .platform_data  = &versatile_flash_data,
 289         },
 290         .num_resources          = 1,
 291         .resource               = &versatile_flash_resource,
 292 };
 293
 294 static struct resource smc91x_resources[] = {
 295         [0] = {
 296                 .start          = VERSATILE_ETH_BASE,
 297                 .end            = VERSATILE_ETH_BASE + SZ_64K - 1,
 298                 .flags          = IORESOURCE_MEM,
 299         },
 300         [1] = {
 301                 .start          = IRQ_ETH,
 302                 .end            = IRQ_ETH,
 303                 .flags          = IORESOURCE_IRQ,
 304         },
 305 };
 306
 307 static struct platform_device smc91x_device = {
 308         .name           = "smc91x",
 309         .id             = 0,
 310         .num_resources  = ARRAY_SIZE(smc91x_resources),
 311         .resource       = smc91x_resources,
 312 };
 313
 314 static struct resource versatile_i2c_resource = {
 315         .start                  = VERSATILE_I2C_BASE,
 316         .end                    = VERSATILE_I2C_BASE + SZ_4K - 1,
 317         .flags                  = IORESOURCE_MEM,
 318 };
 319
 320 static struct platform_device versatile_i2c_device = {
 321         .name                   = "versatile-i2c",
 322         .id                     = 0,
 323         .num_resources          = 1,
 324         .resource               = &versatile_i2c_resource,
 325 };
 326
 327 static struct i2c_board_info versatile_i2c_board_info[] = {
 328         {
 329                 I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
 330         },
 331 };
 332
 333 static int __init versatile_i2c_init(void)
 334 {
 335         return i2c_register_board_info(0, versatile_i2c_board_info,
 336                                        ARRAY_SIZE(versatile_i2c_board_info));
 337 }
 338 arch_initcall(versatile_i2c_init);
 339
 340 #define VERSATILE_SYSMCI        (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET)
 341
 342 unsigned int mmc_status(struct device *dev)
 343 {
 344         struct amba_device *adev = container_of(dev, struct amba_device, dev);
 345         u32 mask;
 346
 347         if (adev->res.start == VERSATILE_MMCI0_BASE)
 348                 mask = 1;
 349         else
 350                 mask = 2;
 351
 352         return readl(VERSATILE_SYSMCI) & mask;
 353 }
 354
 355 static struct mmci_platform_data mmc0_plat_data = {
 356         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
 357         .status         = mmc_status,
 358         .gpio_wp        = -1,
 359         .gpio_cd        = -1,
 360 };
 361
 362 static struct resource char_lcd_resources[] = {
 363         {
 364                 .start = VERSATILE_CHAR_LCD_BASE,
 365                 .end   = (VERSATILE_CHAR_LCD_BASE + SZ_4K - 1),
 366                 .flags = IORESOURCE_MEM,
 367         },
 368 };
 369
 370 static struct platform_device char_lcd_device = {
 371         .name           =       "arm-charlcd",
 372         .id             =       -1,
 373         .num_resources  =       ARRAY_SIZE(char_lcd_resources),
 374         .resource       =       char_lcd_resources,
 375 };
 376
 377 /*
 378  * Clock handling
 379  */
 380 static const struct icst_params versatile_oscvco_params = {
 381         .ref            = 24000000,
 382         .vco_max        = ICST307_VCO_MAX,
 383         .vco_min        = ICST307_VCO_MIN,
 384         .vd_min         = 4 + 8,
 385         .vd_max         = 511 + 8,
 386         .rd_min         = 1 + 2,
 387         .rd_max         = 127 + 2,
 388         .s2div          = icst307_s2div,
 389         .idx2s          = icst307_idx2s,
 390 };
 391
 392 static void versatile_oscvco_set(struct clk *clk, struct icst_vco vco)
 393 {
 394         void __iomem *sys_lock = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LOCK_OFFSET;
 395         u32 val;
 396
 397         val = readl(clk->vcoreg) & ~0x7ffff;
 398         val |= vco.v | (vco.r << 9) | (vco.s << 16);
 399
 400         writel(0xa05f, sys_lock);
 401         writel(val, clk->vcoreg);
 402         writel(0, sys_lock);
 403 }
 404
 405 static const struct clk_ops osc4_clk_ops = {
 406         .round  = icst_clk_round,
 407         .set    = icst_clk_set,
 408         .setvco = versatile_oscvco_set,
 409 };
 410
 411 static struct clk osc4_clk = {
 412         .ops    = &osc4_clk_ops,
 413         .params = &versatile_oscvco_params,
 414 };
 415
 416 /*
 417  * These are fixed clocks.
 418  */
 419 static struct clk ref24_clk = {
 420         .rate   = 24000000,
 421 };
 422
 423 static struct clk dummy_apb_pclk;
 424
 425 static struct clk_lookup lookups[] = {
 426         {       /* AMBA bus clock */
 427                 .con_id         = "apb_pclk",
 428                 .clk            = &dummy_apb_pclk,
 429         }, {    /* UART0 */
 430                 .dev_id         = "dev:f1",
 431                 .clk            = &ref24_clk,
 432         }, {    /* UART1 */
 433                 .dev_id         = "dev:f2",
 434                 .clk            = &ref24_clk,
 435         }, {    /* UART2 */
 436                 .dev_id         = "dev:f3",
 437                 .clk            = &ref24_clk,
 438         }, {    /* UART3 */
 439                 .dev_id         = "fpga:09",
 440                 .clk            = &ref24_clk,
 441         }, {    /* KMI0 */
 442                 .dev_id         = "fpga:06",
 443                 .clk            = &ref24_clk,
 444         }, {    /* KMI1 */
 445                 .dev_id         = "fpga:07",
 446                 .clk            = &ref24_clk,
 447         }, {    /* MMC0 */
 448                 .dev_id         = "fpga:05",
 449                 .clk            = &ref24_clk,
 450         }, {    /* MMC1 */
 451                 .dev_id         = "fpga:0b",
 452                 .clk            = &ref24_clk,
 453         }, {    /* SSP */
 454                 .dev_id         = "dev:f4",
 455                 .clk            = &ref24_clk,
 456         }, {    /* CLCD */
 457                 .dev_id         = "dev:20",
 458                 .clk            = &osc4_clk,
 459         }
 460 };
 461
 462 /*
 463  * CLCD support.
 464  */
 465 #define SYS_CLCD_MODE_MASK      (3 << 0)
 466 #define SYS_CLCD_MODE_888       (0 << 0)
 467 #define SYS_CLCD_MODE_5551      (1 << 0)
 468 #define SYS_CLCD_MODE_565_RLSB  (2 << 0)
 469 #define SYS_CLCD_MODE_565_BLSB  (3 << 0)
 470 #define SYS_CLCD_NLCDIOON       (1 << 2)
 471 #define SYS_CLCD_VDDPOSSWITCH   (1 << 3)
 472 #define SYS_CLCD_PWR3V5SWITCH   (1 << 4)
 473 #define SYS_CLCD_ID_MASK        (0x1f << 8)
 474 #define SYS_CLCD_ID_SANYO_3_8   (0x00 << 8)
 475 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
 476 #define SYS_CLCD_ID_EPSON_2_2   (0x02 << 8)
 477 #define SYS_CLCD_ID_SANYO_2_5   (0x07 << 8)
 478 #define SYS_CLCD_ID_VGA         (0x1f << 8)
 479
 480 static bool is_sanyo_2_5_lcd;
 481
 482 /*
 483  * Disable all display connectors on the interface module.
 484  */
 485 static void versatile_clcd_disable(struct clcd_fb *fb)
 486 {
 487         void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
 488         u32 val;
 489
 490         val = readl(sys_clcd);
 491         val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 492         writel(val, sys_clcd);
 493
 494 #ifdef CONFIG_MACH_VERSATILE_AB
 495         /*
 496          * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off
 497          */
 498         if (machine_is_versatile_ab() && is_sanyo_2_5_lcd) {
 499                 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
 500                 unsigned long ctrl;
 501
 502                 ctrl = readl(versatile_ib2_ctrl);
 503                 ctrl &= ~0x01;
 504                 writel(ctrl, versatile_ib2_ctrl);
 505         }
 506 #endif
 507 }
 508
 509 /*
 510  * Enable the relevant connector on the interface module.
 511  */
 512 static void versatile_clcd_enable(struct clcd_fb *fb)
 513 {
 514         struct fb_var_screeninfo *var = &fb->fb.var;
 515         void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
 516         u32 val;
 517
 518         val = readl(sys_clcd);
 519         val &= ~SYS_CLCD_MODE_MASK;
 520
 521         switch (var->green.length) {
 522         case 5:
 523                 val |= SYS_CLCD_MODE_5551;
 524                 break;
 525         case 6:
 526                 if (var->red.offset == 0)
 527                         val |= SYS_CLCD_MODE_565_RLSB;
 528                 else
 529                         val |= SYS_CLCD_MODE_565_BLSB;
 530                 break;
 531         case 8:
 532                 val |= SYS_CLCD_MODE_888;
 533                 break;
 534         }
 535
 536         /*
 537          * Set the MUX
 538          */
 539         writel(val, sys_clcd);
 540
 541         /*
 542          * And now enable the PSUs
 543          */
 544         val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 545         writel(val, sys_clcd);
 546
 547 #ifdef CONFIG_MACH_VERSATILE_AB
 548         /*
 549          * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on
 550          */
 551         if (machine_is_versatile_ab() && is_sanyo_2_5_lcd) {
 552                 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
 553                 unsigned long ctrl;
 554
 555                 ctrl = readl(versatile_ib2_ctrl);
 556                 ctrl |= 0x01;
 557                 writel(ctrl, versatile_ib2_ctrl);
 558         }
 559 #endif
 560 }
 561
 562 /*
 563  * Detect which LCD panel is connected, and return the appropriate
 564  * clcd_panel structure.  Note: we do not have any information on
 565  * the required timings for the 8.4in panel, so we presently assume
 566  * VGA timings.
 567  */
 568 static int versatile_clcd_setup(struct clcd_fb *fb)
 569 {
 570         void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
 571         const char *panel_name;
 572         u32 val;
 573
 574         is_sanyo_2_5_lcd = false;
 575
 576         val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
 577         if (val == SYS_CLCD_ID_SANYO_3_8)
 578                 panel_name = "Sanyo TM38QV67A02A";
 579         else if (val == SYS_CLCD_ID_SANYO_2_5) {
 580                 panel_name = "Sanyo QVGA Portrait";
 581                 is_sanyo_2_5_lcd = true;
 582         } else if (val == SYS_CLCD_ID_EPSON_2_2)
 583                 panel_name = "Epson L2F50113T00";
 584         else if (val == SYS_CLCD_ID_VGA)
 585                 panel_name = "VGA";
 586         else {
 587                 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
 588                         val);
 589                 panel_name = "VGA";
 590         }
 591
 592         fb->panel = versatile_clcd_get_panel(panel_name);
 593         if (!fb->panel)
 594                 return -EINVAL;
 595
 596         return versatile_clcd_setup_dma(fb, SZ_1M);
 597 }
 598
 599 static void versatile_clcd_decode(struct clcd_fb *fb, struct clcd_regs *regs)
 600 {
 601         clcdfb_decode(fb, regs);
 602
 603         /* Always clear BGR for RGB565: we do the routing externally */
 604         if (fb->fb.var.green.length == 6)
 605                 regs->cntl &= ~CNTL_BGR;
 606 }
 607
 608 static struct clcd_board clcd_plat_data = {
 609         .name           = "Versatile",
 610         .caps           = CLCD_CAP_5551 | CLCD_CAP_565 | CLCD_CAP_888,
 611         .check          = clcdfb_check,
 612         .decode         = versatile_clcd_decode,
 613         .disable        = versatile_clcd_disable,
 614         .enable         = versatile_clcd_enable,
 615         .setup          = versatile_clcd_setup,
 616         .mmap           = versatile_clcd_mmap_dma,
 617         .remove         = versatile_clcd_remove_dma,
 618 };
 619
 620 static struct pl061_platform_data gpio0_plat_data = {
 621         .gpio_base      = 0,
 622         .irq_base       = IRQ_GPIO0_START,
 623 };
 624
 625 static struct pl061_platform_data gpio1_plat_data = {
 626         .gpio_base      = 8,
 627         .irq_base       = IRQ_GPIO1_START,
 628 };
 629
 630 static struct pl022_ssp_controller ssp0_plat_data = {
 631         .bus_id = 0,
 632         .enable_dma = 0,
 633         .num_chipselect = 1,
 634 };
 635
 636 #define AACI_IRQ        { IRQ_AACI, NO_IRQ }
 637 #define AACI_DMA        { 0x80, 0x81 }
 638 #define MMCI0_IRQ       { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
 639 #define MMCI0_DMA       { 0x84, 0 }
 640 #define KMI0_IRQ        { IRQ_SIC_KMI0, NO_IRQ }
 641 #define KMI0_DMA        { 0, 0 }
 642 #define KMI1_IRQ        { IRQ_SIC_KMI1, NO_IRQ }
 643 #define KMI1_DMA        { 0, 0 }
 644
 645 /*
 646  * These devices are connected directly to the multi-layer AHB switch
 647  */
 648 #define SMC_IRQ         { NO_IRQ, NO_IRQ }
 649 #define SMC_DMA         { 0, 0 }
 650 #define MPMC_IRQ        { NO_IRQ, NO_IRQ }
 651 #define MPMC_DMA        { 0, 0 }
 652 #define CLCD_IRQ        { IRQ_CLCDINT, NO_IRQ }
 653 #define CLCD_DMA        { 0, 0 }
 654 #define DMAC_IRQ        { IRQ_DMAINT, NO_IRQ }
 655 #define DMAC_DMA        { 0, 0 }
 656
 657 /*
 658  * These devices are connected via the core APB bridge
 659  */
 660 #define SCTL_IRQ        { NO_IRQ, NO_IRQ }
 661 #define SCTL_DMA        { 0, 0 }
 662 #define WATCHDOG_IRQ    { IRQ_WDOGINT, NO_IRQ }
 663 #define WATCHDOG_DMA    { 0, 0 }
 664 #define GPIO0_IRQ       { IRQ_GPIOINT0, NO_IRQ }
 665 #define GPIO0_DMA       { 0, 0 }
 666 #define GPIO1_IRQ       { IRQ_GPIOINT1, NO_IRQ }
 667 #define GPIO1_DMA       { 0, 0 }
 668 #define RTC_IRQ         { IRQ_RTCINT, NO_IRQ }
 669 #define RTC_DMA         { 0, 0 }
 670
 671 /*
 672  * These devices are connected via the DMA APB bridge
 673  */
 674 #define SCI_IRQ         { IRQ_SCIINT, NO_IRQ }
 675 #define SCI_DMA         { 7, 6 }
 676 #define UART0_IRQ       { IRQ_UARTINT0, NO_IRQ }
 677 #define UART0_DMA       { 15, 14 }
 678 #define UART1_IRQ       { IRQ_UARTINT1, NO_IRQ }
 679 #define UART1_DMA       { 13, 12 }
 680 #define UART2_IRQ       { IRQ_UARTINT2, NO_IRQ }
 681 #define UART2_DMA       { 11, 10 }
 682 #define SSP_IRQ         { IRQ_SSPINT, NO_IRQ }
 683 #define SSP_DMA         { 9, 8 }
 684
 685 /* FPGA Primecells */
 686 AMBA_DEVICE(aaci,  "fpga:04", AACI,     NULL);
 687 AMBA_DEVICE(mmc0,  "fpga:05", MMCI0,    &mmc0_plat_data);
 688 AMBA_DEVICE(kmi0,  "fpga:06", KMI0,     NULL);
 689 AMBA_DEVICE(kmi1,  "fpga:07", KMI1,     NULL);
 690
 691 /* DevChip Primecells */
 692 AMBA_DEVICE(smc,   "dev:00",  SMC,      NULL);
 693 AMBA_DEVICE(mpmc,  "dev:10",  MPMC,     NULL);
 694 AMBA_DEVICE(clcd,  "dev:20",  CLCD,     &clcd_plat_data);
 695 AMBA_DEVICE(dmac,  "dev:30",  DMAC,     NULL);
 696 AMBA_DEVICE(sctl,  "dev:e0",  SCTL,     NULL);
 697 AMBA_DEVICE(wdog,  "dev:e1",  WATCHDOG, NULL);
 698 AMBA_DEVICE(gpio0, "dev:e4",  GPIO0,    &gpio0_plat_data);
 699 AMBA_DEVICE(gpio1, "dev:e5",  GPIO1,    &gpio1_plat_data);
 700 AMBA_DEVICE(rtc,   "dev:e8",  RTC,      NULL);
 701 AMBA_DEVICE(sci0,  "dev:f0",  SCI,      NULL);
 702 AMBA_DEVICE(uart0, "dev:f1",  UART0,    NULL);
 703 AMBA_DEVICE(uart1, "dev:f2",  UART1,    NULL);
 704 AMBA_DEVICE(uart2, "dev:f3",  UART2,    NULL);
 705 AMBA_DEVICE(ssp0,  "dev:f4",  SSP,      &ssp0_plat_data);
 706
 707 static struct amba_device *amba_devs[] __initdata = {
 708         &dmac_device,
 709         &uart0_device,
 710         &uart1_device,
 711         &uart2_device,
 712         &smc_device,
 713         &mpmc_device,
 714         &clcd_device,
 715         &sctl_device,
 716         &wdog_device,
 717         &gpio0_device,
 718         &gpio1_device,
 719         &rtc_device,
 720         &sci0_device,
 721         &ssp0_device,
 722         &aaci_device,
 723         &mmc0_device,
 724         &kmi0_device,
 725         &kmi1_device,
 726 };
 727
 728 #ifdef CONFIG_LEDS
 729 #define VA_LEDS_BASE (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
 730
 731 static void versatile_leds_event(led_event_t ledevt)
 732 {
 733         unsigned long flags;
 734         u32 val;
 735
 736         local_irq_save(flags);
 737         val = readl(VA_LEDS_BASE);
 738
 739         switch (ledevt) {
 740         case led_idle_start:
 741                 val = val & ~VERSATILE_SYS_LED0;
 742                 break;
 743
 744         case led_idle_end:
 745                 val = val | VERSATILE_SYS_LED0;
 746                 break;
 747
 748         case led_timer:
 749                 val = val ^ VERSATILE_SYS_LED1;
 750                 break;
 751
 752         case led_halted:
 753                 val = 0;
 754                 break;
 755
 756         default:
 757                 break;
 758         }
 759
 760         writel(val, VA_LEDS_BASE);
 761         local_irq_restore(flags);
 762 }
 763 #endif  /* CONFIG_LEDS */
 764
 765 /* Early initializations */
 766 void __init versatile_init_early(void)
 767 {
 768         void __iomem *sys = __io_address(VERSATILE_SYS_BASE);
 769
 770         osc4_clk.vcoreg = sys + VERSATILE_SYS_OSCCLCD_OFFSET;
 771         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 772
 773         versatile_sched_clock_init(sys + VERSATILE_SYS_24MHz_OFFSET, 24000000);
 774 }
 775
 776 void __init versatile_init(void)
 777 {
 778         int i;
 779
 780         platform_device_register(&versatile_flash_device);
 781         platform_device_register(&versatile_i2c_device);
 782         platform_device_register(&smc91x_device);
 783         platform_device_register(&char_lcd_device);
 784
 785         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
 786                 struct amba_device *d = amba_devs[i];
 787                 amba_device_register(d, &iomem_resource);
 788         }
 789
 790 #ifdef CONFIG_LEDS
 791         leds_event = versatile_leds_event;
 792 #endif
 793 }
 794
 795 /*
 796  * Where is the timer (VA)?
 797  */
 798 #define TIMER0_VA_BASE           __io_address(VERSATILE_TIMER0_1_BASE)
 799 #define TIMER1_VA_BASE          (__io_address(VERSATILE_TIMER0_1_BASE) + 0x20)
 800 #define TIMER2_VA_BASE           __io_address(VERSATILE_TIMER2_3_BASE)
 801 #define TIMER3_VA_BASE          (__io_address(VERSATILE_TIMER2_3_BASE) + 0x20)
 802
 803 /*
 804  * Set up timer interrupt, and return the current time in seconds.
 805  */
 806 static void __init versatile_timer_init(void)
 807 {
 808         u32 val;
 809
 810         /*
 811          * set clock frequency:
 812          *      VERSATILE_REFCLK is 32KHz
 813          *      VERSATILE_TIMCLK is 1MHz
 814          */
 815         val = readl(__io_address(VERSATILE_SCTL_BASE));
 816         writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) |
 817                (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
 818                (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) |
 819                (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val,
 820                __io_address(VERSATILE_SCTL_BASE));
 821
 822         /*
 823          * Initialise to a known state (all timers off)
 824          */
 825         writel(0, TIMER0_VA_BASE + TIMER_CTRL);
 826         writel(0, TIMER1_VA_BASE + TIMER_CTRL);
 827         writel(0, TIMER2_VA_BASE + TIMER_CTRL);
 828         writel(0, TIMER3_VA_BASE + TIMER_CTRL);
 829
 830         sp804_clocksource_init(TIMER3_VA_BASE);
 831         sp804_clockevents_init(TIMER0_VA_BASE, IRQ_TIMERINT0_1);
 832 }
 833
 834 struct sys_timer versatile_timer = {
 835         .init           = versatile_timer_init,
 836 };
 837