arch/arm/mach-versatile/core.c

   1 /*
   2  *  linux/arch/arm/mach-versatile/core.c
   3  *
   4  *  Copyright (C) 1999 - 2003 ARM Limited
   5  *  Copyright (C) 2000 Deep Blue Solutions Ltd
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21 #include <linux/init.h>
  22 #include <linux/device.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/irqdomain.h>
  27 #include <linux/of_address.h>
  28 #include <linux/of_platform.h>
  29 #include <linux/amba/bus.h>
  30 #include <linux/amba/clcd.h>
  31 #include <linux/amba/pl061.h>
  32 #include <linux/amba/mmci.h>
  33 #include <linux/amba/pl022.h>
  34 #include <linux/io.h>
  35 #include <linux/gfp.h>
  36 #include <linux/clkdev.h>
  37 #include <linux/mtd/physmap.h>
  38
  39 #include <asm/irq.h>
  40 #include <asm/leds.h>
  41 #include <asm/hardware/arm_timer.h>
  42 #include <asm/hardware/icst.h>
  43 #include <asm/hardware/vic.h>
  44 #include <asm/mach-types.h>
  45
  46 #include <asm/mach/arch.h>
  47 #include <asm/mach/irq.h>
  48 #include <asm/mach/time.h>
  49 #include <asm/mach/map.h>
  50 #include <mach/hardware.h>
  51 #include <mach/platform.h>
  52 #include <asm/hardware/timer-sp.h>
  53
  54 #include <plat/clcd.h>
  55 #include <plat/fpga-irq.h>
  56 #include <plat/sched_clock.h>
  57
  58 #include "core.h"
  59
  60 /*
  61  * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
  62  * is the (PA >> 12).
  63  *
  64  * Setup a VA for the Versatile Vectored Interrupt Controller.
  65  */
  66 #define VA_VIC_BASE             __io_address(VERSATILE_VIC_BASE)
  67 #define VA_SIC_BASE             __io_address(VERSATILE_SIC_BASE)
  68
  69 #if 1
  70 #define IRQ_MMCI0A      IRQ_VICSOURCE22
  71 #define IRQ_AACI        IRQ_VICSOURCE24
  72 #define IRQ_ETH         IRQ_VICSOURCE25
  73 #define PIC_MASK        0xFFD00000
  74 #else
  75 #define IRQ_MMCI0A      IRQ_SIC_MMCI0A
  76 #define IRQ_AACI        IRQ_SIC_AACI
  77 #define IRQ_ETH         IRQ_SIC_ETH
  78 #define PIC_MASK        0
  79 #endif
  80
  81 /* Lookup table for finding a DT node that represents the vic instance */
  82 static const struct of_device_id vic_of_match[] __initconst = {
  83         { .compatible = "arm,versatile-vic", },
  84         {}
  85 };
  86
  87 static const struct of_device_id sic_of_match[] __initconst = {
  88         { .compatible = "arm,versatile-sic", },
  89         {}
  90 };
  91
  92 void __init versatile_init_irq(void)
  93 {
  94         struct device_node *np;
  95
  96         np = of_find_matching_node_by_address(NULL, vic_of_match,
  97                                               VERSATILE_VIC_BASE);
  98         __vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0, 0, np);
  99
 100         writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
 101
 102         np = of_find_matching_node_by_address(NULL, sic_of_match,
 103                                               VERSATILE_SIC_BASE);
 104
 105         fpga_irq_init(VA_SIC_BASE, "SIC", IRQ_SIC_START,
 106                 IRQ_VICSOURCE31, ~PIC_MASK, np);
 107
 108         /*
 109          * Interrupts on secondary controller from 0 to 8 are routed to
 110          * source 31 on PIC.
 111          * Interrupts from 21 to 31 are routed directly to the VIC on
 112          * the corresponding number on primary controller. This is controlled
 113          * by setting PIC_ENABLEx.
 114          */
 115         writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE);
 116 }
 117
 118 static struct map_desc versatile_io_desc[] __initdata = {
 119         {
 120                 .virtual        =  IO_ADDRESS(VERSATILE_SYS_BASE),
 121                 .pfn            = __phys_to_pfn(VERSATILE_SYS_BASE),
 122                 .length         = SZ_4K,
 123                 .type           = MT_DEVICE
 124         }, {
 125                 .virtual        =  IO_ADDRESS(VERSATILE_SIC_BASE),
 126                 .pfn            = __phys_to_pfn(VERSATILE_SIC_BASE),
 127                 .length         = SZ_4K,
 128                 .type           = MT_DEVICE
 129         }, {
 130                 .virtual        =  IO_ADDRESS(VERSATILE_VIC_BASE),
 131                 .pfn            = __phys_to_pfn(VERSATILE_VIC_BASE),
 132                 .length         = SZ_4K,
 133                 .type           = MT_DEVICE
 134         }, {
 135                 .virtual        =  IO_ADDRESS(VERSATILE_SCTL_BASE),
 136                 .pfn            = __phys_to_pfn(VERSATILE_SCTL_BASE),
 137                 .length         = SZ_4K * 9,
 138                 .type           = MT_DEVICE
 139         },
 140 #ifdef CONFIG_MACH_VERSATILE_AB
 141         {
 142                 .virtual        =  IO_ADDRESS(VERSATILE_IB2_BASE),
 143                 .pfn            = __phys_to_pfn(VERSATILE_IB2_BASE),
 144                 .length         = SZ_64M,
 145                 .type           = MT_DEVICE
 146         },
 147 #endif
 148 #ifdef CONFIG_DEBUG_LL
 149         {
 150                 .virtual        =  IO_ADDRESS(VERSATILE_UART0_BASE),
 151                 .pfn            = __phys_to_pfn(VERSATILE_UART0_BASE),
 152                 .length         = SZ_4K,
 153                 .type           = MT_DEVICE
 154         },
 155 #endif
 156 #ifdef CONFIG_PCI
 157         {
 158                 .virtual        =  IO_ADDRESS(VERSATILE_PCI_CORE_BASE),
 159                 .pfn            = __phys_to_pfn(VERSATILE_PCI_CORE_BASE),
 160                 .length         = SZ_4K,
 161                 .type           = MT_DEVICE
 162         }, {
 163                 .virtual        =  (unsigned long)VERSATILE_PCI_VIRT_BASE,
 164                 .pfn            = __phys_to_pfn(VERSATILE_PCI_BASE),
 165                 .length         = VERSATILE_PCI_BASE_SIZE,
 166                 .type           = MT_DEVICE
 167         }, {
 168                 .virtual        =  (unsigned long)VERSATILE_PCI_CFG_VIRT_BASE,
 169                 .pfn            = __phys_to_pfn(VERSATILE_PCI_CFG_BASE),
 170                 .length         = VERSATILE_PCI_CFG_BASE_SIZE,
 171                 .type           = MT_DEVICE
 172         }, {
 173                 .virtual        =  (unsigned long)VERSATILE_PCI_VIRT_MEM_BASE0,
 174                 .pfn            = __phys_to_pfn(VERSATILE_PCI_MEM_BASE0),
 175                 .length         = IO_SPACE_LIMIT,
 176                 .type           = MT_DEVICE
 177         },
 178 #endif
 179 };
 180
 181 void __init versatile_map_io(void)
 182 {
 183         iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc));
 184 }
 185
 186
 187 #define VERSATILE_FLASHCTRL    (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
 188
 189 static void versatile_flash_set_vpp(struct platform_device *pdev, int on)
 190 {
 191         u32 val;
 192
 193         val = __raw_readl(VERSATILE_FLASHCTRL);
 194         if (on)
 195                 val |= VERSATILE_FLASHPROG_FLVPPEN;
 196         else
 197                 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
 198         __raw_writel(val, VERSATILE_FLASHCTRL);
 199 }
 200
 201 static struct physmap_flash_data versatile_flash_data = {
 202         .width                  = 4,
 203         .set_vpp                = versatile_flash_set_vpp,
 204 };
 205
 206 static struct resource versatile_flash_resource = {
 207         .start                  = VERSATILE_FLASH_BASE,
 208         .end                    = VERSATILE_FLASH_BASE + VERSATILE_FLASH_SIZE - 1,
 209         .flags                  = IORESOURCE_MEM,
 210 };
 211
 212 static struct platform_device versatile_flash_device = {
 213         .name                   = "physmap-flash",
 214         .id                     = 0,
 215         .dev                    = {
 216                 .platform_data  = &versatile_flash_data,
 217         },
 218         .num_resources          = 1,
 219         .resource               = &versatile_flash_resource,
 220 };
 221
 222 static struct resource smc91x_resources[] = {
 223         [0] = {
 224                 .start          = VERSATILE_ETH_BASE,
 225                 .end            = VERSATILE_ETH_BASE + SZ_64K - 1,
 226                 .flags          = IORESOURCE_MEM,
 227         },
 228         [1] = {
 229                 .start          = IRQ_ETH,
 230                 .end            = IRQ_ETH,
 231                 .flags          = IORESOURCE_IRQ,
 232         },
 233 };
 234
 235 static struct platform_device smc91x_device = {
 236         .name           = "smc91x",
 237         .id             = 0,
 238         .num_resources  = ARRAY_SIZE(smc91x_resources),
 239         .resource       = smc91x_resources,
 240 };
 241
 242 static struct resource versatile_i2c_resource = {
 243         .start                  = VERSATILE_I2C_BASE,
 244         .end                    = VERSATILE_I2C_BASE + SZ_4K - 1,
 245         .flags                  = IORESOURCE_MEM,
 246 };
 247
 248 static struct platform_device versatile_i2c_device = {
 249         .name                   = "versatile-i2c",
 250         .id                     = 0,
 251         .num_resources          = 1,
 252         .resource               = &versatile_i2c_resource,
 253 };
 254
 255 static struct i2c_board_info versatile_i2c_board_info[] = {
 256         {
 257                 I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
 258         },
 259 };
 260
 261 static int __init versatile_i2c_init(void)
 262 {
 263         return i2c_register_board_info(0, versatile_i2c_board_info,
 264                                        ARRAY_SIZE(versatile_i2c_board_info));
 265 }
 266 arch_initcall(versatile_i2c_init);
 267
 268 #define VERSATILE_SYSMCI        (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET)
 269
 270 unsigned int mmc_status(struct device *dev)
 271 {
 272         struct amba_device *adev = container_of(dev, struct amba_device, dev);
 273         u32 mask;
 274
 275         if (adev->res.start == VERSATILE_MMCI0_BASE)
 276                 mask = 1;
 277         else
 278                 mask = 2;
 279
 280         return readl(VERSATILE_SYSMCI) & mask;
 281 }
 282
 283 static struct mmci_platform_data mmc0_plat_data = {
 284         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
 285         .status         = mmc_status,
 286         .gpio_wp        = -1,
 287         .gpio_cd        = -1,
 288 };
 289
 290 static struct resource char_lcd_resources[] = {
 291         {
 292                 .start = VERSATILE_CHAR_LCD_BASE,
 293                 .end   = (VERSATILE_CHAR_LCD_BASE + SZ_4K - 1),
 294                 .flags = IORESOURCE_MEM,
 295         },
 296 };
 297
 298 static struct platform_device char_lcd_device = {
 299         .name           =       "arm-charlcd",
 300         .id             =       -1,
 301         .num_resources  =       ARRAY_SIZE(char_lcd_resources),
 302         .resource       =       char_lcd_resources,
 303 };
 304
 305 /*
 306  * Clock handling
 307  */
 308 static const struct icst_params versatile_oscvco_params = {
 309         .ref            = 24000000,
 310         .vco_max        = ICST307_VCO_MAX,
 311         .vco_min        = ICST307_VCO_MIN,
 312         .vd_min         = 4 + 8,
 313         .vd_max         = 511 + 8,
 314         .rd_min         = 1 + 2,
 315         .rd_max         = 127 + 2,
 316         .s2div          = icst307_s2div,
 317         .idx2s          = icst307_idx2s,
 318 };
 319
 320 static void versatile_oscvco_set(struct clk *clk, struct icst_vco vco)
 321 {
 322         void __iomem *sys_lock = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LOCK_OFFSET;
 323         u32 val;
 324
 325         val = readl(clk->vcoreg) & ~0x7ffff;
 326         val |= vco.v | (vco.r << 9) | (vco.s << 16);
 327
 328         writel(0xa05f, sys_lock);
 329         writel(val, clk->vcoreg);
 330         writel(0, sys_lock);
 331 }
 332
 333 static const struct clk_ops osc4_clk_ops = {
 334         .round  = icst_clk_round,
 335         .set    = icst_clk_set,
 336         .setvco = versatile_oscvco_set,
 337 };
 338
 339 static struct clk osc4_clk = {
 340         .ops    = &osc4_clk_ops,
 341         .params = &versatile_oscvco_params,
 342 };
 343
 344 /*
 345  * These are fixed clocks.
 346  */
 347 static struct clk ref24_clk = {
 348         .rate   = 24000000,
 349 };
 350
 351 static struct clk sp804_clk = {
 352         .rate   = 1000000,
 353 };
 354
 355 static struct clk dummy_apb_pclk;
 356
 357 static struct clk_lookup lookups[] = {
 358         {       /* AMBA bus clock */
 359                 .con_id         = "apb_pclk",
 360                 .clk            = &dummy_apb_pclk,
 361         }, {    /* UART0 */
 362                 .dev_id         = "dev:f1",
 363                 .clk            = &ref24_clk,
 364         }, {    /* UART1 */
 365                 .dev_id         = "dev:f2",
 366                 .clk            = &ref24_clk,
 367         }, {    /* UART2 */
 368                 .dev_id         = "dev:f3",
 369                 .clk            = &ref24_clk,
 370         }, {    /* UART3 */
 371                 .dev_id         = "fpga:09",
 372                 .clk            = &ref24_clk,
 373         }, {    /* KMI0 */
 374                 .dev_id         = "fpga:06",
 375                 .clk            = &ref24_clk,
 376         }, {    /* KMI1 */
 377                 .dev_id         = "fpga:07",
 378                 .clk            = &ref24_clk,
 379         }, {    /* MMC0 */
 380                 .dev_id         = "fpga:05",
 381                 .clk            = &ref24_clk,
 382         }, {    /* MMC1 */
 383                 .dev_id         = "fpga:0b",
 384                 .clk            = &ref24_clk,
 385         }, {    /* SSP */
 386                 .dev_id         = "dev:f4",
 387                 .clk            = &ref24_clk,
 388         }, {    /* CLCD */
 389                 .dev_id         = "dev:20",
 390                 .clk            = &osc4_clk,
 391         }, {    /* SP804 timers */
 392                 .dev_id         = "sp804",
 393                 .clk            = &sp804_clk,
 394         },
 395 };
 396
 397 /*
 398  * CLCD support.
 399  */
 400 #define SYS_CLCD_MODE_MASK      (3 << 0)
 401 #define SYS_CLCD_MODE_888       (0 << 0)
 402 #define SYS_CLCD_MODE_5551      (1 << 0)
 403 #define SYS_CLCD_MODE_565_RLSB  (2 << 0)
 404 #define SYS_CLCD_MODE_565_BLSB  (3 << 0)
 405 #define SYS_CLCD_NLCDIOON       (1 << 2)
 406 #define SYS_CLCD_VDDPOSSWITCH   (1 << 3)
 407 #define SYS_CLCD_PWR3V5SWITCH   (1 << 4)
 408 #define SYS_CLCD_ID_MASK        (0x1f << 8)
 409 #define SYS_CLCD_ID_SANYO_3_8   (0x00 << 8)
 410 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
 411 #define SYS_CLCD_ID_EPSON_2_2   (0x02 << 8)
 412 #define SYS_CLCD_ID_SANYO_2_5   (0x07 << 8)
 413 #define SYS_CLCD_ID_VGA         (0x1f << 8)
 414
 415 static bool is_sanyo_2_5_lcd;
 416
 417 /*
 418  * Disable all display connectors on the interface module.
 419  */
 420 static void versatile_clcd_disable(struct clcd_fb *fb)
 421 {
 422         void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
 423         u32 val;
 424
 425         val = readl(sys_clcd);
 426         val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 427         writel(val, sys_clcd);
 428
 429 #ifdef CONFIG_MACH_VERSATILE_AB
 430         /*
 431          * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off
 432          */
 433         if (machine_is_versatile_ab() && is_sanyo_2_5_lcd) {
 434                 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
 435                 unsigned long ctrl;
 436
 437                 ctrl = readl(versatile_ib2_ctrl);
 438                 ctrl &= ~0x01;
 439                 writel(ctrl, versatile_ib2_ctrl);
 440         }
 441 #endif
 442 }
 443
 444 /*
 445  * Enable the relevant connector on the interface module.
 446  */
 447 static void versatile_clcd_enable(struct clcd_fb *fb)
 448 {
 449         struct fb_var_screeninfo *var = &fb->fb.var;
 450         void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
 451         u32 val;
 452
 453         val = readl(sys_clcd);
 454         val &= ~SYS_CLCD_MODE_MASK;
 455
 456         switch (var->green.length) {
 457         case 5:
 458                 val |= SYS_CLCD_MODE_5551;
 459                 break;
 460         case 6:
 461                 if (var->red.offset == 0)
 462                         val |= SYS_CLCD_MODE_565_RLSB;
 463                 else
 464                         val |= SYS_CLCD_MODE_565_BLSB;
 465                 break;
 466         case 8:
 467                 val |= SYS_CLCD_MODE_888;
 468                 break;
 469         }
 470
 471         /*
 472          * Set the MUX
 473          */
 474         writel(val, sys_clcd);
 475
 476         /*
 477          * And now enable the PSUs
 478          */
 479         val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 480         writel(val, sys_clcd);
 481
 482 #ifdef CONFIG_MACH_VERSATILE_AB
 483         /*
 484          * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on
 485          */
 486         if (machine_is_versatile_ab() && is_sanyo_2_5_lcd) {
 487                 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
 488                 unsigned long ctrl;
 489
 490                 ctrl = readl(versatile_ib2_ctrl);
 491                 ctrl |= 0x01;
 492                 writel(ctrl, versatile_ib2_ctrl);
 493         }
 494 #endif
 495 }
 496
 497 /*
 498  * Detect which LCD panel is connected, and return the appropriate
 499  * clcd_panel structure.  Note: we do not have any information on
 500  * the required timings for the 8.4in panel, so we presently assume
 501  * VGA timings.
 502  */
 503 static int versatile_clcd_setup(struct clcd_fb *fb)
 504 {
 505         void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
 506         const char *panel_name;
 507         u32 val;
 508
 509         is_sanyo_2_5_lcd = false;
 510
 511         val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
 512         if (val == SYS_CLCD_ID_SANYO_3_8)
 513                 panel_name = "Sanyo TM38QV67A02A";
 514         else if (val == SYS_CLCD_ID_SANYO_2_5) {
 515                 panel_name = "Sanyo QVGA Portrait";
 516                 is_sanyo_2_5_lcd = true;
 517         } else if (val == SYS_CLCD_ID_EPSON_2_2)
 518                 panel_name = "Epson L2F50113T00";
 519         else if (val == SYS_CLCD_ID_VGA)
 520                 panel_name = "VGA";
 521         else {
 522                 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
 523                         val);
 524                 panel_name = "VGA";
 525         }
 526
 527         fb->panel = versatile_clcd_get_panel(panel_name);
 528         if (!fb->panel)
 529                 return -EINVAL;
 530
 531         return versatile_clcd_setup_dma(fb, SZ_1M);
 532 }
 533
 534 static void versatile_clcd_decode(struct clcd_fb *fb, struct clcd_regs *regs)
 535 {
 536         clcdfb_decode(fb, regs);
 537
 538         /* Always clear BGR for RGB565: we do the routing externally */
 539         if (fb->fb.var.green.length == 6)
 540                 regs->cntl &= ~CNTL_BGR;
 541 }
 542
 543 static struct clcd_board clcd_plat_data = {
 544         .name           = "Versatile",
 545         .caps           = CLCD_CAP_5551 | CLCD_CAP_565 | CLCD_CAP_888,
 546         .check          = clcdfb_check,
 547         .decode         = versatile_clcd_decode,
 548         .disable        = versatile_clcd_disable,
 549         .enable         = versatile_clcd_enable,
 550         .setup          = versatile_clcd_setup,
 551         .mmap           = versatile_clcd_mmap_dma,
 552         .remove         = versatile_clcd_remove_dma,
 553 };
 554
 555 static struct pl061_platform_data gpio0_plat_data = {
 556         .gpio_base      = 0,
 557         .irq_base       = IRQ_GPIO0_START,
 558 };
 559
 560 static struct pl061_platform_data gpio1_plat_data = {
 561         .gpio_base      = 8,
 562         .irq_base       = IRQ_GPIO1_START,
 563 };
 564
 565 static struct pl022_ssp_controller ssp0_plat_data = {
 566         .bus_id = 0,
 567         .enable_dma = 0,
 568         .num_chipselect = 1,
 569 };
 570
 571 #define AACI_IRQ        { IRQ_AACI }
 572 #define MMCI0_IRQ       { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
 573 #define KMI0_IRQ        { IRQ_SIC_KMI0 }
 574 #define KMI1_IRQ        { IRQ_SIC_KMI1 }
 575
 576 /*
 577  * These devices are connected directly to the multi-layer AHB switch
 578  */
 579 #define SMC_IRQ         { }
 580 #define MPMC_IRQ        { }
 581 #define CLCD_IRQ        { IRQ_CLCDINT }
 582 #define DMAC_IRQ        { IRQ_DMAINT }
 583
 584 /*
 585  * These devices are connected via the core APB bridge
 586  */
 587 #define SCTL_IRQ        { }
 588 #define WATCHDOG_IRQ    { IRQ_WDOGINT }
 589 #define GPIO0_IRQ       { IRQ_GPIOINT0 }
 590 #define GPIO1_IRQ       { IRQ_GPIOINT1 }
 591 #define RTC_IRQ         { IRQ_RTCINT }
 592
 593 /*
 594  * These devices are connected via the DMA APB bridge
 595  */
 596 #define SCI_IRQ         { IRQ_SCIINT }
 597 #define UART0_IRQ       { IRQ_UARTINT0 }
 598 #define UART1_IRQ       { IRQ_UARTINT1 }
 599 #define UART2_IRQ       { IRQ_UARTINT2 }
 600 #define SSP_IRQ         { IRQ_SSPINT }
 601
 602 /* FPGA Primecells */
 603 APB_DEVICE(aaci,  "fpga:04", AACI,     NULL);
 604 APB_DEVICE(mmc0,  "fpga:05", MMCI0,    &mmc0_plat_data);
 605 APB_DEVICE(kmi0,  "fpga:06", KMI0,     NULL);
 606 APB_DEVICE(kmi1,  "fpga:07", KMI1,     NULL);
 607
 608 /* DevChip Primecells */
 609 AHB_DEVICE(smc,   "dev:00",  SMC,      NULL);
 610 AHB_DEVICE(mpmc,  "dev:10",  MPMC,     NULL);
 611 AHB_DEVICE(clcd,  "dev:20",  CLCD,     &clcd_plat_data);
 612 AHB_DEVICE(dmac,  "dev:30",  DMAC,     NULL);
 613 APB_DEVICE(sctl,  "dev:e0",  SCTL,     NULL);
 614 APB_DEVICE(wdog,  "dev:e1",  WATCHDOG, NULL);
 615 APB_DEVICE(gpio0, "dev:e4",  GPIO0,    &gpio0_plat_data);
 616 APB_DEVICE(gpio1, "dev:e5",  GPIO1,    &gpio1_plat_data);
 617 APB_DEVICE(rtc,   "dev:e8",  RTC,      NULL);
 618 APB_DEVICE(sci0,  "dev:f0",  SCI,      NULL);
 619 APB_DEVICE(uart0, "dev:f1",  UART0,    NULL);
 620 APB_DEVICE(uart1, "dev:f2",  UART1,    NULL);
 621 APB_DEVICE(uart2, "dev:f3",  UART2,    NULL);
 622 APB_DEVICE(ssp0,  "dev:f4",  SSP,      &ssp0_plat_data);
 623
 624 static struct amba_device *amba_devs[] __initdata = {
 625         &dmac_device,
 626         &uart0_device,
 627         &uart1_device,
 628         &uart2_device,
 629         &smc_device,
 630         &mpmc_device,
 631         &clcd_device,
 632         &sctl_device,
 633         &wdog_device,
 634         &gpio0_device,
 635         &gpio1_device,
 636         &rtc_device,
 637         &sci0_device,
 638         &ssp0_device,
 639         &aaci_device,
 640         &mmc0_device,
 641         &kmi0_device,
 642         &kmi1_device,
 643 };
 644
 645 #ifdef CONFIG_OF
 646 /*
 647  * Lookup table for attaching a specific name and platform_data pointer to
 648  * devices as they get created by of_platform_populate().  Ideally this table
 649  * would not exist, but the current clock implementation depends on some devices
 650  * having a specific name.
 651  */
 652 struct of_dev_auxdata versatile_auxdata_lookup[] __initdata = {
 653         OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI0_BASE, "fpga:05", &mmc0_plat_data),
 654         OF_DEV_AUXDATA("arm,primecell", VERSATILE_KMI0_BASE, "fpga:06", NULL),
 655         OF_DEV_AUXDATA("arm,primecell", VERSATILE_KMI1_BASE, "fpga:07", NULL),
 656         OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART3_BASE, "fpga:09", NULL),
 657         /* FIXME: this is buggy, the platform data is needed for this MMC instance too */
 658         OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI1_BASE, "fpga:0b", NULL),
 659
 660         OF_DEV_AUXDATA("arm,primecell", VERSATILE_CLCD_BASE, "dev:20", &clcd_plat_data),
 661         OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART0_BASE, "dev:f1", NULL),
 662         OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART1_BASE, "dev:f2", NULL),
 663         OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART2_BASE, "dev:f3", NULL),
 664         OF_DEV_AUXDATA("arm,primecell", VERSATILE_SSP_BASE, "dev:f4", &ssp0_plat_data),
 665
 666 #if 0
 667         /*
 668          * These entries are unnecessary because no clocks referencing
 669          * them.  I've left them in for now as place holders in case
 670          * any of them need to be added back, but they should be
 671          * removed before actually committing this patch.  --gcl
 672          */
 673         OF_DEV_AUXDATA("arm,primecell", VERSATILE_AACI_BASE, "fpga:04", NULL),
 674         OF_DEV_AUXDATA("arm,primecell", VERSATILE_SCI1_BASE, "fpga:0a", NULL),
 675         OF_DEV_AUXDATA("arm,primecell", VERSATILE_SMC_BASE, "dev:00", NULL),
 676         OF_DEV_AUXDATA("arm,primecell", VERSATILE_MPMC_BASE, "dev:10", NULL),
 677         OF_DEV_AUXDATA("arm,primecell", VERSATILE_DMAC_BASE, "dev:30", NULL),
 678
 679         OF_DEV_AUXDATA("arm,primecell", VERSATILE_SCTL_BASE, "dev:e0", NULL),
 680         OF_DEV_AUXDATA("arm,primecell", VERSATILE_WATCHDOG_BASE, "dev:e1", NULL),
 681         OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO0_BASE, "dev:e4", NULL),
 682         OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO1_BASE, "dev:e5", NULL),
 683         OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO2_BASE, "dev:e6", NULL),
 684         OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO3_BASE, "dev:e7", NULL),
 685         OF_DEV_AUXDATA("arm,primecell", VERSATILE_RTC_BASE, "dev:e8", NULL),
 686         OF_DEV_AUXDATA("arm,primecell", VERSATILE_SCI_BASE, "dev:f0", NULL),
 687 #endif
 688         {}
 689 };
 690 #endif
 691
 692 #ifdef CONFIG_LEDS
 693 #define VA_LEDS_BASE (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
 694
 695 static void versatile_leds_event(led_event_t ledevt)
 696 {
 697         unsigned long flags;
 698         u32 val;
 699
 700         local_irq_save(flags);
 701         val = readl(VA_LEDS_BASE);
 702
 703         switch (ledevt) {
 704         case led_idle_start:
 705                 val = val & ~VERSATILE_SYS_LED0;
 706                 break;
 707
 708         case led_idle_end:
 709                 val = val | VERSATILE_SYS_LED0;
 710                 break;
 711
 712         case led_timer:
 713                 val = val ^ VERSATILE_SYS_LED1;
 714                 break;
 715
 716         case led_halted:
 717                 val = 0;
 718                 break;
 719
 720         default:
 721                 break;
 722         }
 723
 724         writel(val, VA_LEDS_BASE);
 725         local_irq_restore(flags);
 726 }
 727 #endif  /* CONFIG_LEDS */
 728
 729 void versatile_restart(char mode, const char *cmd)
 730 {
 731         void __iomem *sys = __io_address(VERSATILE_SYS_BASE);
 732         u32 val;
 733
 734         val = __raw_readl(sys + VERSATILE_SYS_RESETCTL_OFFSET);
 735         val |= 0x105;
 736
 737         __raw_writel(0xa05f, sys + VERSATILE_SYS_LOCK_OFFSET);
 738         __raw_writel(val, sys + VERSATILE_SYS_RESETCTL_OFFSET);
 739         __raw_writel(0, sys + VERSATILE_SYS_LOCK_OFFSET);
 740 }
 741
 742 /* Early initializations */
 743 void __init versatile_init_early(void)
 744 {
 745         void __iomem *sys = __io_address(VERSATILE_SYS_BASE);
 746
 747         osc4_clk.vcoreg = sys + VERSATILE_SYS_OSCCLCD_OFFSET;
 748         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 749
 750         versatile_sched_clock_init(sys + VERSATILE_SYS_24MHz_OFFSET, 24000000);
 751 }
 752
 753 void __init versatile_init(void)
 754 {
 755         int i;
 756
 757         platform_device_register(&versatile_flash_device);
 758         platform_device_register(&versatile_i2c_device);
 759         platform_device_register(&smc91x_device);
 760         platform_device_register(&char_lcd_device);
 761
 762         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
 763                 struct amba_device *d = amba_devs[i];
 764                 amba_device_register(d, &iomem_resource);
 765         }
 766
 767 #ifdef CONFIG_LEDS
 768         leds_event = versatile_leds_event;
 769 #endif
 770 }
 771
 772 /*
 773  * Where is the timer (VA)?
 774  */
 775 #define TIMER0_VA_BASE           __io_address(VERSATILE_TIMER0_1_BASE)
 776 #define TIMER1_VA_BASE          (__io_address(VERSATILE_TIMER0_1_BASE) + 0x20)
 777 #define TIMER2_VA_BASE           __io_address(VERSATILE_TIMER2_3_BASE)
 778 #define TIMER3_VA_BASE          (__io_address(VERSATILE_TIMER2_3_BASE) + 0x20)
 779
 780 /*
 781  * Set up timer interrupt, and return the current time in seconds.
 782  */
 783 static void __init versatile_timer_init(void)
 784 {
 785         u32 val;
 786
 787         /*
 788          * set clock frequency:
 789          *      VERSATILE_REFCLK is 32KHz
 790          *      VERSATILE_TIMCLK is 1MHz
 791          */
 792         val = readl(__io_address(VERSATILE_SCTL_BASE));
 793         writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) |
 794                (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
 795                (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) |
 796                (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val,
 797                __io_address(VERSATILE_SCTL_BASE));
 798
 799         /*
 800          * Initialise to a known state (all timers off)
 801          */
 802         writel(0, TIMER0_VA_BASE + TIMER_CTRL);
 803         writel(0, TIMER1_VA_BASE + TIMER_CTRL);
 804         writel(0, TIMER2_VA_BASE + TIMER_CTRL);
 805         writel(0, TIMER3_VA_BASE + TIMER_CTRL);
 806
 807         sp804_clocksource_init(TIMER3_VA_BASE, "timer3");
 808         sp804_clockevents_init(TIMER0_VA_BASE, IRQ_TIMERINT0_1, "timer0");
 809 }
 810
 811 struct sys_timer versatile_timer = {
 812         .init           = versatile_timer_init,
 813 };
 814