arch/arm/mach-versatile/core.c

   1 /*
   2  *  linux/arch/arm/mach-versatile/core.c
   3  *
   4  *  Copyright (C) 1999 - 2003 ARM Limited
   5  *  Copyright (C) 2000 Deep Blue Solutions Ltd
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21 #include <linux/init.h>
  22 #include <linux/device.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/irqdomain.h>
  27 #include <linux/of_address.h>
  28 #include <linux/of_platform.h>
  29 #include <linux/amba/bus.h>
  30 #include <linux/amba/clcd.h>
  31 #include <linux/amba/pl061.h>
  32 #include <linux/amba/mmci.h>
  33 #include <linux/amba/pl022.h>
  34 #include <linux/io.h>
  35 #include <linux/gfp.h>
  36 #include <linux/clkdev.h>
  37 #include <linux/mtd/physmap.h>
  38
  39 #include <asm/irq.h>
  40 #include <asm/leds.h>
  41 #include <asm/hardware/arm_timer.h>
  42 #include <asm/hardware/icst.h>
  43 #include <asm/hardware/vic.h>
  44 #include <asm/mach-types.h>
  45
  46 #include <asm/mach/arch.h>
  47 #include <asm/mach/irq.h>
  48 #include <asm/mach/time.h>
  49 #include <asm/mach/map.h>
  50 #include <mach/hardware.h>
  51 #include <mach/platform.h>
  52 #include <asm/hardware/timer-sp.h>
  53
  54 #include <plat/clcd.h>
  55 #include <plat/fpga-irq.h>
  56 #include <plat/sched_clock.h>
  57
  58 #include "core.h"
  59
  60 /*
  61  * All IO addresses are mapped onto VA 0xFFFx.xxxx, where x.xxxx
  62  * is the (PA >> 12).
  63  *
  64  * Setup a VA for the Versatile Vectored Interrupt Controller.
  65  */
  66 #define VA_VIC_BASE             __io_address(VERSATILE_VIC_BASE)
  67 #define VA_SIC_BASE             __io_address(VERSATILE_SIC_BASE)
  68
  69 #if 1
  70 #define IRQ_MMCI0A      IRQ_VICSOURCE22
  71 #define IRQ_AACI        IRQ_VICSOURCE24
  72 #define IRQ_ETH         IRQ_VICSOURCE25
  73 #define PIC_MASK        0xFFD00000
  74 #else
  75 #define IRQ_MMCI0A      IRQ_SIC_MMCI0A
  76 #define IRQ_AACI        IRQ_SIC_AACI
  77 #define IRQ_ETH         IRQ_SIC_ETH
  78 #define PIC_MASK        0
  79 #endif
  80
  81 /* Lookup table for finding a DT node that represents the vic instance */
  82 static const struct of_device_id vic_of_match[] __initconst = {
  83         { .compatible = "arm,versatile-vic", },
  84         {}
  85 };
  86
  87 static const struct of_device_id sic_of_match[] __initconst = {
  88         { .compatible = "arm,versatile-sic", },
  89         {}
  90 };
  91
  92 void __init versatile_init_irq(void)
  93 {
  94         struct device_node *np;
  95
  96         np = of_find_matching_node_by_address(NULL, vic_of_match,
  97                                               VERSATILE_VIC_BASE);
  98         __vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0, 0, np);
  99
 100         writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
 101
 102         np = of_find_matching_node_by_address(NULL, sic_of_match,
 103                                               VERSATILE_SIC_BASE);
 104
 105         fpga_irq_init(VA_SIC_BASE, "SIC", IRQ_SIC_START,
 106                 IRQ_VICSOURCE31, ~PIC_MASK, np);
 107
 108         /*
 109          * Interrupts on secondary controller from 0 to 8 are routed to
 110          * source 31 on PIC.
 111          * Interrupts from 21 to 31 are routed directly to the VIC on
 112          * the corresponding number on primary controller. This is controlled
 113          * by setting PIC_ENABLEx.
 114          */
 115         writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE);
 116 }
 117
 118 static struct map_desc versatile_io_desc[] __initdata = {
 119         {
 120                 .virtual        =  IO_ADDRESS(VERSATILE_SYS_BASE),
 121                 .pfn            = __phys_to_pfn(VERSATILE_SYS_BASE),
 122                 .length         = SZ_4K,
 123                 .type           = MT_DEVICE
 124         }, {
 125                 .virtual        =  IO_ADDRESS(VERSATILE_SIC_BASE),
 126                 .pfn            = __phys_to_pfn(VERSATILE_SIC_BASE),
 127                 .length         = SZ_4K,
 128                 .type           = MT_DEVICE
 129         }, {
 130                 .virtual        =  IO_ADDRESS(VERSATILE_VIC_BASE),
 131                 .pfn            = __phys_to_pfn(VERSATILE_VIC_BASE),
 132                 .length         = SZ_4K,
 133                 .type           = MT_DEVICE
 134         }, {
 135                 .virtual        =  IO_ADDRESS(VERSATILE_SCTL_BASE),
 136                 .pfn            = __phys_to_pfn(VERSATILE_SCTL_BASE),
 137                 .length         = SZ_4K * 9,
 138                 .type           = MT_DEVICE
 139         },
 140 #ifdef CONFIG_MACH_VERSATILE_AB
 141         {
 142                 .virtual        =  IO_ADDRESS(VERSATILE_IB2_BASE),
 143                 .pfn            = __phys_to_pfn(VERSATILE_IB2_BASE),
 144                 .length         = SZ_64M,
 145                 .type           = MT_DEVICE
 146         },
 147 #endif
 148 #ifdef CONFIG_DEBUG_LL
 149         {
 150                 .virtual        =  IO_ADDRESS(VERSATILE_UART0_BASE),
 151                 .pfn            = __phys_to_pfn(VERSATILE_UART0_BASE),
 152                 .length         = SZ_4K,
 153                 .type           = MT_DEVICE
 154         },
 155 #endif
 156 #ifdef CONFIG_PCI
 157         {
 158                 .virtual        =  IO_ADDRESS(VERSATILE_PCI_CORE_BASE),
 159                 .pfn            = __phys_to_pfn(VERSATILE_PCI_CORE_BASE),
 160                 .length         = SZ_4K,
 161                 .type           = MT_DEVICE
 162         }, {
 163                 .virtual        =  (unsigned long)VERSATILE_PCI_VIRT_BASE,
 164                 .pfn            = __phys_to_pfn(VERSATILE_PCI_BASE),
 165                 .length         = VERSATILE_PCI_BASE_SIZE,
 166                 .type           = MT_DEVICE
 167         }, {
 168                 .virtual        =  (unsigned long)VERSATILE_PCI_CFG_VIRT_BASE,
 169                 .pfn            = __phys_to_pfn(VERSATILE_PCI_CFG_BASE),
 170                 .length         = VERSATILE_PCI_CFG_BASE_SIZE,
 171                 .type           = MT_DEVICE
 172         },
 173 #endif
 174 };
 175
 176 void __init versatile_map_io(void)
 177 {
 178         iotable_init(versatile_io_desc, ARRAY_SIZE(versatile_io_desc));
 179 }
 180
 181
 182 #define VERSATILE_FLASHCTRL    (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
 183
 184 static void versatile_flash_set_vpp(struct platform_device *pdev, int on)
 185 {
 186         u32 val;
 187
 188         val = __raw_readl(VERSATILE_FLASHCTRL);
 189         if (on)
 190                 val |= VERSATILE_FLASHPROG_FLVPPEN;
 191         else
 192                 val &= ~VERSATILE_FLASHPROG_FLVPPEN;
 193         __raw_writel(val, VERSATILE_FLASHCTRL);
 194 }
 195
 196 static struct physmap_flash_data versatile_flash_data = {
 197         .width                  = 4,
 198         .set_vpp                = versatile_flash_set_vpp,
 199 };
 200
 201 static struct resource versatile_flash_resource = {
 202         .start                  = VERSATILE_FLASH_BASE,
 203         .end                    = VERSATILE_FLASH_BASE + VERSATILE_FLASH_SIZE - 1,
 204         .flags                  = IORESOURCE_MEM,
 205 };
 206
 207 static struct platform_device versatile_flash_device = {
 208         .name                   = "physmap-flash",
 209         .id                     = 0,
 210         .dev                    = {
 211                 .platform_data  = &versatile_flash_data,
 212         },
 213         .num_resources          = 1,
 214         .resource               = &versatile_flash_resource,
 215 };
 216
 217 static struct resource smc91x_resources[] = {
 218         [0] = {
 219                 .start          = VERSATILE_ETH_BASE,
 220                 .end            = VERSATILE_ETH_BASE + SZ_64K - 1,
 221                 .flags          = IORESOURCE_MEM,
 222         },
 223         [1] = {
 224                 .start          = IRQ_ETH,
 225                 .end            = IRQ_ETH,
 226                 .flags          = IORESOURCE_IRQ,
 227         },
 228 };
 229
 230 static struct platform_device smc91x_device = {
 231         .name           = "smc91x",
 232         .id             = 0,
 233         .num_resources  = ARRAY_SIZE(smc91x_resources),
 234         .resource       = smc91x_resources,
 235 };
 236
 237 static struct resource versatile_i2c_resource = {
 238         .start                  = VERSATILE_I2C_BASE,
 239         .end                    = VERSATILE_I2C_BASE + SZ_4K - 1,
 240         .flags                  = IORESOURCE_MEM,
 241 };
 242
 243 static struct platform_device versatile_i2c_device = {
 244         .name                   = "versatile-i2c",
 245         .id                     = 0,
 246         .num_resources          = 1,
 247         .resource               = &versatile_i2c_resource,
 248 };
 249
 250 static struct i2c_board_info versatile_i2c_board_info[] = {
 251         {
 252                 I2C_BOARD_INFO("ds1338", 0xd0 >> 1),
 253         },
 254 };
 255
 256 static int __init versatile_i2c_init(void)
 257 {
 258         return i2c_register_board_info(0, versatile_i2c_board_info,
 259                                        ARRAY_SIZE(versatile_i2c_board_info));
 260 }
 261 arch_initcall(versatile_i2c_init);
 262
 263 #define VERSATILE_SYSMCI        (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_MCI_OFFSET)
 264
 265 unsigned int mmc_status(struct device *dev)
 266 {
 267         struct amba_device *adev = container_of(dev, struct amba_device, dev);
 268         u32 mask;
 269
 270         if (adev->res.start == VERSATILE_MMCI0_BASE)
 271                 mask = 1;
 272         else
 273                 mask = 2;
 274
 275         return readl(VERSATILE_SYSMCI) & mask;
 276 }
 277
 278 static struct mmci_platform_data mmc0_plat_data = {
 279         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
 280         .status         = mmc_status,
 281         .gpio_wp        = -1,
 282         .gpio_cd        = -1,
 283 };
 284
 285 static struct resource char_lcd_resources[] = {
 286         {
 287                 .start = VERSATILE_CHAR_LCD_BASE,
 288                 .end   = (VERSATILE_CHAR_LCD_BASE + SZ_4K - 1),
 289                 .flags = IORESOURCE_MEM,
 290         },
 291 };
 292
 293 static struct platform_device char_lcd_device = {
 294         .name           =       "arm-charlcd",
 295         .id             =       -1,
 296         .num_resources  =       ARRAY_SIZE(char_lcd_resources),
 297         .resource       =       char_lcd_resources,
 298 };
 299
 300 /*
 301  * Clock handling
 302  */
 303 static const struct icst_params versatile_oscvco_params = {
 304         .ref            = 24000000,
 305         .vco_max        = ICST307_VCO_MAX,
 306         .vco_min        = ICST307_VCO_MIN,
 307         .vd_min         = 4 + 8,
 308         .vd_max         = 511 + 8,
 309         .rd_min         = 1 + 2,
 310         .rd_max         = 127 + 2,
 311         .s2div          = icst307_s2div,
 312         .idx2s          = icst307_idx2s,
 313 };
 314
 315 static void versatile_oscvco_set(struct clk *clk, struct icst_vco vco)
 316 {
 317         void __iomem *sys_lock = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LOCK_OFFSET;
 318         u32 val;
 319
 320         val = readl(clk->vcoreg) & ~0x7ffff;
 321         val |= vco.v | (vco.r << 9) | (vco.s << 16);
 322
 323         writel(0xa05f, sys_lock);
 324         writel(val, clk->vcoreg);
 325         writel(0, sys_lock);
 326 }
 327
 328 static const struct clk_ops osc4_clk_ops = {
 329         .round  = icst_clk_round,
 330         .set    = icst_clk_set,
 331         .setvco = versatile_oscvco_set,
 332 };
 333
 334 static struct clk osc4_clk = {
 335         .ops    = &osc4_clk_ops,
 336         .params = &versatile_oscvco_params,
 337 };
 338
 339 /*
 340  * These are fixed clocks.
 341  */
 342 static struct clk ref24_clk = {
 343         .rate   = 24000000,
 344 };
 345
 346 static struct clk sp804_clk = {
 347         .rate   = 1000000,
 348 };
 349
 350 static struct clk dummy_apb_pclk;
 351
 352 static struct clk_lookup lookups[] = {
 353         {       /* AMBA bus clock */
 354                 .con_id         = "apb_pclk",
 355                 .clk            = &dummy_apb_pclk,
 356         }, {    /* UART0 */
 357                 .dev_id         = "dev:f1",
 358                 .clk            = &ref24_clk,
 359         }, {    /* UART1 */
 360                 .dev_id         = "dev:f2",
 361                 .clk            = &ref24_clk,
 362         }, {    /* UART2 */
 363                 .dev_id         = "dev:f3",
 364                 .clk            = &ref24_clk,
 365         }, {    /* UART3 */
 366                 .dev_id         = "fpga:09",
 367                 .clk            = &ref24_clk,
 368         }, {    /* KMI0 */
 369                 .dev_id         = "fpga:06",
 370                 .clk            = &ref24_clk,
 371         }, {    /* KMI1 */
 372                 .dev_id         = "fpga:07",
 373                 .clk            = &ref24_clk,
 374         }, {    /* MMC0 */
 375                 .dev_id         = "fpga:05",
 376                 .clk            = &ref24_clk,
 377         }, {    /* MMC1 */
 378                 .dev_id         = "fpga:0b",
 379                 .clk            = &ref24_clk,
 380         }, {    /* SSP */
 381                 .dev_id         = "dev:f4",
 382                 .clk            = &ref24_clk,
 383         }, {    /* CLCD */
 384                 .dev_id         = "dev:20",
 385                 .clk            = &osc4_clk,
 386         }, {    /* SP804 timers */
 387                 .dev_id         = "sp804",
 388                 .clk            = &sp804_clk,
 389         },
 390 };
 391
 392 /*
 393  * CLCD support.
 394  */
 395 #define SYS_CLCD_MODE_MASK      (3 << 0)
 396 #define SYS_CLCD_MODE_888       (0 << 0)
 397 #define SYS_CLCD_MODE_5551      (1 << 0)
 398 #define SYS_CLCD_MODE_565_RLSB  (2 << 0)
 399 #define SYS_CLCD_MODE_565_BLSB  (3 << 0)
 400 #define SYS_CLCD_NLCDIOON       (1 << 2)
 401 #define SYS_CLCD_VDDPOSSWITCH   (1 << 3)
 402 #define SYS_CLCD_PWR3V5SWITCH   (1 << 4)
 403 #define SYS_CLCD_ID_MASK        (0x1f << 8)
 404 #define SYS_CLCD_ID_SANYO_3_8   (0x00 << 8)
 405 #define SYS_CLCD_ID_UNKNOWN_8_4 (0x01 << 8)
 406 #define SYS_CLCD_ID_EPSON_2_2   (0x02 << 8)
 407 #define SYS_CLCD_ID_SANYO_2_5   (0x07 << 8)
 408 #define SYS_CLCD_ID_VGA         (0x1f << 8)
 409
 410 static bool is_sanyo_2_5_lcd;
 411
 412 /*
 413  * Disable all display connectors on the interface module.
 414  */
 415 static void versatile_clcd_disable(struct clcd_fb *fb)
 416 {
 417         void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
 418         u32 val;
 419
 420         val = readl(sys_clcd);
 421         val &= ~SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 422         writel(val, sys_clcd);
 423
 424 #ifdef CONFIG_MACH_VERSATILE_AB
 425         /*
 426          * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light off
 427          */
 428         if (machine_is_versatile_ab() && is_sanyo_2_5_lcd) {
 429                 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
 430                 unsigned long ctrl;
 431
 432                 ctrl = readl(versatile_ib2_ctrl);
 433                 ctrl &= ~0x01;
 434                 writel(ctrl, versatile_ib2_ctrl);
 435         }
 436 #endif
 437 }
 438
 439 /*
 440  * Enable the relevant connector on the interface module.
 441  */
 442 static void versatile_clcd_enable(struct clcd_fb *fb)
 443 {
 444         struct fb_var_screeninfo *var = &fb->fb.var;
 445         void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
 446         u32 val;
 447
 448         val = readl(sys_clcd);
 449         val &= ~SYS_CLCD_MODE_MASK;
 450
 451         switch (var->green.length) {
 452         case 5:
 453                 val |= SYS_CLCD_MODE_5551;
 454                 break;
 455         case 6:
 456                 if (var->red.offset == 0)
 457                         val |= SYS_CLCD_MODE_565_RLSB;
 458                 else
 459                         val |= SYS_CLCD_MODE_565_BLSB;
 460                 break;
 461         case 8:
 462                 val |= SYS_CLCD_MODE_888;
 463                 break;
 464         }
 465
 466         /*
 467          * Set the MUX
 468          */
 469         writel(val, sys_clcd);
 470
 471         /*
 472          * And now enable the PSUs
 473          */
 474         val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH;
 475         writel(val, sys_clcd);
 476
 477 #ifdef CONFIG_MACH_VERSATILE_AB
 478         /*
 479          * If the LCD is Sanyo 2x5 in on the IB2 board, turn the back-light on
 480          */
 481         if (machine_is_versatile_ab() && is_sanyo_2_5_lcd) {
 482                 void __iomem *versatile_ib2_ctrl = __io_address(VERSATILE_IB2_CTRL);
 483                 unsigned long ctrl;
 484
 485                 ctrl = readl(versatile_ib2_ctrl);
 486                 ctrl |= 0x01;
 487                 writel(ctrl, versatile_ib2_ctrl);
 488         }
 489 #endif
 490 }
 491
 492 /*
 493  * Detect which LCD panel is connected, and return the appropriate
 494  * clcd_panel structure.  Note: we do not have any information on
 495  * the required timings for the 8.4in panel, so we presently assume
 496  * VGA timings.
 497  */
 498 static int versatile_clcd_setup(struct clcd_fb *fb)
 499 {
 500         void __iomem *sys_clcd = __io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_CLCD_OFFSET;
 501         const char *panel_name;
 502         u32 val;
 503
 504         is_sanyo_2_5_lcd = false;
 505
 506         val = readl(sys_clcd) & SYS_CLCD_ID_MASK;
 507         if (val == SYS_CLCD_ID_SANYO_3_8)
 508                 panel_name = "Sanyo TM38QV67A02A";
 509         else if (val == SYS_CLCD_ID_SANYO_2_5) {
 510                 panel_name = "Sanyo QVGA Portrait";
 511                 is_sanyo_2_5_lcd = true;
 512         } else if (val == SYS_CLCD_ID_EPSON_2_2)
 513                 panel_name = "Epson L2F50113T00";
 514         else if (val == SYS_CLCD_ID_VGA)
 515                 panel_name = "VGA";
 516         else {
 517                 printk(KERN_ERR "CLCD: unknown LCD panel ID 0x%08x, using VGA\n",
 518                         val);
 519                 panel_name = "VGA";
 520         }
 521
 522         fb->panel = versatile_clcd_get_panel(panel_name);
 523         if (!fb->panel)
 524                 return -EINVAL;
 525
 526         return versatile_clcd_setup_dma(fb, SZ_1M);
 527 }
 528
 529 static void versatile_clcd_decode(struct clcd_fb *fb, struct clcd_regs *regs)
 530 {
 531         clcdfb_decode(fb, regs);
 532
 533         /* Always clear BGR for RGB565: we do the routing externally */
 534         if (fb->fb.var.green.length == 6)
 535                 regs->cntl &= ~CNTL_BGR;
 536 }
 537
 538 static struct clcd_board clcd_plat_data = {
 539         .name           = "Versatile",
 540         .caps           = CLCD_CAP_5551 | CLCD_CAP_565 | CLCD_CAP_888,
 541         .check          = clcdfb_check,
 542         .decode         = versatile_clcd_decode,
 543         .disable        = versatile_clcd_disable,
 544         .enable         = versatile_clcd_enable,
 545         .setup          = versatile_clcd_setup,
 546         .mmap           = versatile_clcd_mmap_dma,
 547         .remove         = versatile_clcd_remove_dma,
 548 };
 549
 550 static struct pl061_platform_data gpio0_plat_data = {
 551         .gpio_base      = 0,
 552         .irq_base       = IRQ_GPIO0_START,
 553 };
 554
 555 static struct pl061_platform_data gpio1_plat_data = {
 556         .gpio_base      = 8,
 557         .irq_base       = IRQ_GPIO1_START,
 558 };
 559
 560 static struct pl022_ssp_controller ssp0_plat_data = {
 561         .bus_id = 0,
 562         .enable_dma = 0,
 563         .num_chipselect = 1,
 564 };
 565
 566 #define AACI_IRQ        { IRQ_AACI }
 567 #define MMCI0_IRQ       { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
 568 #define KMI0_IRQ        { IRQ_SIC_KMI0 }
 569 #define KMI1_IRQ        { IRQ_SIC_KMI1 }
 570
 571 /*
 572  * These devices are connected directly to the multi-layer AHB switch
 573  */
 574 #define SMC_IRQ         { }
 575 #define MPMC_IRQ        { }
 576 #define CLCD_IRQ        { IRQ_CLCDINT }
 577 #define DMAC_IRQ        { IRQ_DMAINT }
 578
 579 /*
 580  * These devices are connected via the core APB bridge
 581  */
 582 #define SCTL_IRQ        { }
 583 #define WATCHDOG_IRQ    { IRQ_WDOGINT }
 584 #define GPIO0_IRQ       { IRQ_GPIOINT0 }
 585 #define GPIO1_IRQ       { IRQ_GPIOINT1 }
 586 #define RTC_IRQ         { IRQ_RTCINT }
 587
 588 /*
 589  * These devices are connected via the DMA APB bridge
 590  */
 591 #define SCI_IRQ         { IRQ_SCIINT }
 592 #define UART0_IRQ       { IRQ_UARTINT0 }
 593 #define UART1_IRQ       { IRQ_UARTINT1 }
 594 #define UART2_IRQ       { IRQ_UARTINT2 }
 595 #define SSP_IRQ         { IRQ_SSPINT }
 596
 597 /* FPGA Primecells */
 598 APB_DEVICE(aaci,  "fpga:04", AACI,     NULL);
 599 APB_DEVICE(mmc0,  "fpga:05", MMCI0,    &mmc0_plat_data);
 600 APB_DEVICE(kmi0,  "fpga:06", KMI0,     NULL);
 601 APB_DEVICE(kmi1,  "fpga:07", KMI1,     NULL);
 602
 603 /* DevChip Primecells */
 604 AHB_DEVICE(smc,   "dev:00",  SMC,      NULL);
 605 AHB_DEVICE(mpmc,  "dev:10",  MPMC,     NULL);
 606 AHB_DEVICE(clcd,  "dev:20",  CLCD,     &clcd_plat_data);
 607 AHB_DEVICE(dmac,  "dev:30",  DMAC,     NULL);
 608 APB_DEVICE(sctl,  "dev:e0",  SCTL,     NULL);
 609 APB_DEVICE(wdog,  "dev:e1",  WATCHDOG, NULL);
 610 APB_DEVICE(gpio0, "dev:e4",  GPIO0,    &gpio0_plat_data);
 611 APB_DEVICE(gpio1, "dev:e5",  GPIO1,    &gpio1_plat_data);
 612 APB_DEVICE(rtc,   "dev:e8",  RTC,      NULL);
 613 APB_DEVICE(sci0,  "dev:f0",  SCI,      NULL);
 614 APB_DEVICE(uart0, "dev:f1",  UART0,    NULL);
 615 APB_DEVICE(uart1, "dev:f2",  UART1,    NULL);
 616 APB_DEVICE(uart2, "dev:f3",  UART2,    NULL);
 617 APB_DEVICE(ssp0,  "dev:f4",  SSP,      &ssp0_plat_data);
 618
 619 static struct amba_device *amba_devs[] __initdata = {
 620         &dmac_device,
 621         &uart0_device,
 622         &uart1_device,
 623         &uart2_device,
 624         &smc_device,
 625         &mpmc_device,
 626         &clcd_device,
 627         &sctl_device,
 628         &wdog_device,
 629         &gpio0_device,
 630         &gpio1_device,
 631         &rtc_device,
 632         &sci0_device,
 633         &ssp0_device,
 634         &aaci_device,
 635         &mmc0_device,
 636         &kmi0_device,
 637         &kmi1_device,
 638 };
 639
 640 #ifdef CONFIG_OF
 641 /*
 642  * Lookup table for attaching a specific name and platform_data pointer to
 643  * devices as they get created by of_platform_populate().  Ideally this table
 644  * would not exist, but the current clock implementation depends on some devices
 645  * having a specific name.
 646  */
 647 struct of_dev_auxdata versatile_auxdata_lookup[] __initdata = {
 648         OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI0_BASE, "fpga:05", &mmc0_plat_data),
 649         OF_DEV_AUXDATA("arm,primecell", VERSATILE_KMI0_BASE, "fpga:06", NULL),
 650         OF_DEV_AUXDATA("arm,primecell", VERSATILE_KMI1_BASE, "fpga:07", NULL),
 651         OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART3_BASE, "fpga:09", NULL),
 652         /* FIXME: this is buggy, the platform data is needed for this MMC instance too */
 653         OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI1_BASE, "fpga:0b", NULL),
 654
 655         OF_DEV_AUXDATA("arm,primecell", VERSATILE_CLCD_BASE, "dev:20", &clcd_plat_data),
 656         OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART0_BASE, "dev:f1", NULL),
 657         OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART1_BASE, "dev:f2", NULL),
 658         OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART2_BASE, "dev:f3", NULL),
 659         OF_DEV_AUXDATA("arm,primecell", VERSATILE_SSP_BASE, "dev:f4", &ssp0_plat_data),
 660
 661 #if 0
 662         /*
 663          * These entries are unnecessary because no clocks referencing
 664          * them.  I've left them in for now as place holders in case
 665          * any of them need to be added back, but they should be
 666          * removed before actually committing this patch.  --gcl
 667          */
 668         OF_DEV_AUXDATA("arm,primecell", VERSATILE_AACI_BASE, "fpga:04", NULL),
 669         OF_DEV_AUXDATA("arm,primecell", VERSATILE_SCI1_BASE, "fpga:0a", NULL),
 670         OF_DEV_AUXDATA("arm,primecell", VERSATILE_SMC_BASE, "dev:00", NULL),
 671         OF_DEV_AUXDATA("arm,primecell", VERSATILE_MPMC_BASE, "dev:10", NULL),
 672         OF_DEV_AUXDATA("arm,primecell", VERSATILE_DMAC_BASE, "dev:30", NULL),
 673
 674         OF_DEV_AUXDATA("arm,primecell", VERSATILE_SCTL_BASE, "dev:e0", NULL),
 675         OF_DEV_AUXDATA("arm,primecell", VERSATILE_WATCHDOG_BASE, "dev:e1", NULL),
 676         OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO0_BASE, "dev:e4", NULL),
 677         OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO1_BASE, "dev:e5", NULL),
 678         OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO2_BASE, "dev:e6", NULL),
 679         OF_DEV_AUXDATA("arm,primecell", VERSATILE_GPIO3_BASE, "dev:e7", NULL),
 680         OF_DEV_AUXDATA("arm,primecell", VERSATILE_RTC_BASE, "dev:e8", NULL),
 681         OF_DEV_AUXDATA("arm,primecell", VERSATILE_SCI_BASE, "dev:f0", NULL),
 682 #endif
 683         {}
 684 };
 685 #endif
 686
 687 #ifdef CONFIG_LEDS
 688 #define VA_LEDS_BASE (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
 689
 690 static void versatile_leds_event(led_event_t ledevt)
 691 {
 692         unsigned long flags;
 693         u32 val;
 694
 695         local_irq_save(flags);
 696         val = readl(VA_LEDS_BASE);
 697
 698         switch (ledevt) {
 699         case led_idle_start:
 700                 val = val & ~VERSATILE_SYS_LED0;
 701                 break;
 702
 703         case led_idle_end:
 704                 val = val | VERSATILE_SYS_LED0;
 705                 break;
 706
 707         case led_timer:
 708                 val = val ^ VERSATILE_SYS_LED1;
 709                 break;
 710
 711         case led_halted:
 712                 val = 0;
 713                 break;
 714
 715         default:
 716                 break;
 717         }
 718
 719         writel(val, VA_LEDS_BASE);
 720         local_irq_restore(flags);
 721 }
 722 #endif  /* CONFIG_LEDS */
 723
 724 void versatile_restart(char mode, const char *cmd)
 725 {
 726         void __iomem *sys = __io_address(VERSATILE_SYS_BASE);
 727         u32 val;
 728
 729         val = __raw_readl(sys + VERSATILE_SYS_RESETCTL_OFFSET);
 730         val |= 0x105;
 731
 732         __raw_writel(0xa05f, sys + VERSATILE_SYS_LOCK_OFFSET);
 733         __raw_writel(val, sys + VERSATILE_SYS_RESETCTL_OFFSET);
 734         __raw_writel(0, sys + VERSATILE_SYS_LOCK_OFFSET);
 735 }
 736
 737 /* Early initializations */
 738 void __init versatile_init_early(void)
 739 {
 740         void __iomem *sys = __io_address(VERSATILE_SYS_BASE);
 741
 742         osc4_clk.vcoreg = sys + VERSATILE_SYS_OSCCLCD_OFFSET;
 743         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 744
 745         versatile_sched_clock_init(sys + VERSATILE_SYS_24MHz_OFFSET, 24000000);
 746 }
 747
 748 void __init versatile_init(void)
 749 {
 750         int i;
 751
 752         platform_device_register(&versatile_flash_device);
 753         platform_device_register(&versatile_i2c_device);
 754         platform_device_register(&smc91x_device);
 755         platform_device_register(&char_lcd_device);
 756
 757         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
 758                 struct amba_device *d = amba_devs[i];
 759                 amba_device_register(d, &iomem_resource);
 760         }
 761
 762 #ifdef CONFIG_LEDS
 763         leds_event = versatile_leds_event;
 764 #endif
 765 }
 766
 767 /*
 768  * Where is the timer (VA)?
 769  */
 770 #define TIMER0_VA_BASE           __io_address(VERSATILE_TIMER0_1_BASE)
 771 #define TIMER1_VA_BASE          (__io_address(VERSATILE_TIMER0_1_BASE) + 0x20)
 772 #define TIMER2_VA_BASE           __io_address(VERSATILE_TIMER2_3_BASE)
 773 #define TIMER3_VA_BASE          (__io_address(VERSATILE_TIMER2_3_BASE) + 0x20)
 774
 775 /*
 776  * Set up timer interrupt, and return the current time in seconds.
 777  */
 778 static void __init versatile_timer_init(void)
 779 {
 780         u32 val;
 781
 782         /*
 783          * set clock frequency:
 784          *      VERSATILE_REFCLK is 32KHz
 785          *      VERSATILE_TIMCLK is 1MHz
 786          */
 787         val = readl(__io_address(VERSATILE_SCTL_BASE));
 788         writel((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) |
 789                (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
 790                (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) |
 791                (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel) | val,
 792                __io_address(VERSATILE_SCTL_BASE));
 793
 794         /*
 795          * Initialise to a known state (all timers off)
 796          */
 797         writel(0, TIMER0_VA_BASE + TIMER_CTRL);
 798         writel(0, TIMER1_VA_BASE + TIMER_CTRL);
 799         writel(0, TIMER2_VA_BASE + TIMER_CTRL);
 800         writel(0, TIMER3_VA_BASE + TIMER_CTRL);
 801
 802         sp804_clocksource_init(TIMER3_VA_BASE, "timer3");
 803         sp804_clockevents_init(TIMER0_VA_BASE, IRQ_TIMERINT0_1, "timer0");
 804 }
 805
 806 struct sys_timer versatile_timer = {
 807         .init           = versatile_timer_init,
 808 };
 809