2 * Copyright (C) 2009 ST-Ericsson
3 * Copyright (C) 2009 STMicroelectronics
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 #include <linux/module.h>
10 #include <linux/kernel.h>
11 #include <linux/list.h>
12 #include <linux/errno.h>
13 #include <linux/err.h>
14 #include <linux/clk.h>
16 #include <linux/clkdev.h>
19 #include <mach/hardware.h>
22 #ifdef CONFIG_DEBUG_FS
23 #include <linux/debugfs.h>
24 #include <linux/uaccess.h> /* for copy_from_user */
25 static LIST_HEAD(clk_list);
28 #define PRCC_PCKEN 0x00
29 #define PRCC_PCKDIS 0x04
30 #define PRCC_KCKEN 0x08
31 #define PRCC_KCKDIS 0x0C
33 #define PRCM_YYCLKEN0_MGT_SET 0x510
34 #define PRCM_YYCLKEN1_MGT_SET 0x514
35 #define PRCM_YYCLKEN0_MGT_CLR 0x518
36 #define PRCM_YYCLKEN1_MGT_CLR 0x51C
37 #define PRCM_YYCLKEN0_MGT_VAL 0x520
38 #define PRCM_YYCLKEN1_MGT_VAL 0x524
40 #define PRCM_SVAMMDSPCLK_MGT 0x008
41 #define PRCM_SIAMMDSPCLK_MGT 0x00C
42 #define PRCM_SGACLK_MGT 0x014
43 #define PRCM_UARTCLK_MGT 0x018
44 #define PRCM_MSP02CLK_MGT 0x01C
45 #define PRCM_MSP1CLK_MGT 0x288
46 #define PRCM_I2CCLK_MGT 0x020
47 #define PRCM_SDMMCCLK_MGT 0x024
48 #define PRCM_SLIMCLK_MGT 0x028
49 #define PRCM_PER1CLK_MGT 0x02C
50 #define PRCM_PER2CLK_MGT 0x030
51 #define PRCM_PER3CLK_MGT 0x034
52 #define PRCM_PER5CLK_MGT 0x038
53 #define PRCM_PER6CLK_MGT 0x03C
54 #define PRCM_PER7CLK_MGT 0x040
55 #define PRCM_LCDCLK_MGT 0x044
56 #define PRCM_BMLCLK_MGT 0x04C
57 #define PRCM_HSITXCLK_MGT 0x050
58 #define PRCM_HSIRXCLK_MGT 0x054
59 #define PRCM_HDMICLK_MGT 0x058
60 #define PRCM_APEATCLK_MGT 0x05C
61 #define PRCM_APETRACECLK_MGT 0x060
62 #define PRCM_MCDECLK_MGT 0x064
63 #define PRCM_IPI2CCLK_MGT 0x068
64 #define PRCM_DSIALTCLK_MGT 0x06C
65 #define PRCM_DMACLK_MGT 0x074
66 #define PRCM_B2R2CLK_MGT 0x078
67 #define PRCM_TVCLK_MGT 0x07C
68 #define PRCM_TCR 0x1C8
69 #define PRCM_TCR_STOPPED (1 << 16)
70 #define PRCM_TCR_DOZE_MODE (1 << 17)
71 #define PRCM_UNIPROCLK_MGT 0x278
72 #define PRCM_SSPCLK_MGT 0x280
73 #define PRCM_RNGCLK_MGT 0x284
74 #define PRCM_UICCCLK_MGT 0x27C
76 #define PRCM_MGT_ENABLE (1 << 8)
78 static DEFINE_SPINLOCK(clocks_lock);
80 static void __clk_enable(struct clk *clk)
82 if (clk->enabled++ == 0) {
83 if (clk->parent_cluster)
84 __clk_enable(clk->parent_cluster);
86 if (clk->parent_periph)
87 __clk_enable(clk->parent_periph);
89 if (clk->ops && clk->ops->enable)
90 clk->ops->enable(clk);
94 int clk_enable(struct clk *clk)
98 spin_lock_irqsave(&clocks_lock, flags);
100 spin_unlock_irqrestore(&clocks_lock, flags);
104 EXPORT_SYMBOL(clk_enable);
106 static void __clk_disable(struct clk *clk)
108 if (--clk->enabled == 0) {
109 if (clk->ops && clk->ops->disable)
110 clk->ops->disable(clk);
112 if (clk->parent_periph)
113 __clk_disable(clk->parent_periph);
115 if (clk->parent_cluster)
116 __clk_disable(clk->parent_cluster);
120 void clk_disable(struct clk *clk)
124 WARN_ON(!clk->enabled);
126 spin_lock_irqsave(&clocks_lock, flags);
128 spin_unlock_irqrestore(&clocks_lock, flags);
130 EXPORT_SYMBOL(clk_disable);
133 * The MTU has a separate, rather complex muxing setup
134 * with alternative parents (peripheral cluster or
135 * ULP or fixed 32768 Hz) depending on settings
137 static unsigned long clk_mtu_get_rate(struct clk *clk)
139 void __iomem *addr = __io_address(UX500_PRCMU_BASE)
142 int mtu = (int) clk->data;
144 * One of these is selected eventually
145 * TODO: Replace the constant with a reference
146 * to the ULP source once this is modeled.
148 unsigned long clk32k = 32768;
149 unsigned long mturate;
150 unsigned long retclk;
153 * On a startup, always conifgure the TCR to the doze mode;
154 * bootloaders do it for us. Do this in the kernel too.
156 writel(PRCM_TCR_DOZE_MODE, addr);
160 /* Get the rate from the parent as a default */
161 if (clk->parent_periph)
162 mturate = clk_get_rate(clk->parent_periph);
163 else if (clk->parent_cluster)
164 mturate = clk_get_rate(clk->parent_cluster);
166 /* We need to be connected SOMEWHERE */
169 /* Return the clock selected for this MTU */
170 if (tcr & (1 << mtu))
175 pr_info("MTU%d clock rate: %lu Hz\n", mtu, retclk);
179 unsigned long clk_get_rate(struct clk *clk)
184 * If there is a custom getrate callback for this clock,
185 * it will take precedence.
188 return clk->get_rate(clk);
190 if (clk->ops && clk->ops->get_rate)
191 return clk->ops->get_rate(clk);
195 if (clk->parent_periph)
196 rate = clk_get_rate(clk->parent_periph);
197 else if (clk->parent_cluster)
198 rate = clk_get_rate(clk->parent_cluster);
203 EXPORT_SYMBOL(clk_get_rate);
205 long clk_round_rate(struct clk *clk, unsigned long rate)
210 EXPORT_SYMBOL(clk_round_rate);
212 int clk_set_rate(struct clk *clk, unsigned long rate)
217 EXPORT_SYMBOL(clk_set_rate);
219 static void clk_prcmu_enable(struct clk *clk)
221 void __iomem *cg_set_reg = __io_address(U8500_PRCMU_BASE)
222 + PRCM_YYCLKEN0_MGT_SET + clk->prcmu_cg_off;
224 writel(1 << clk->prcmu_cg_bit, cg_set_reg);
227 static void clk_prcmu_disable(struct clk *clk)
229 void __iomem *cg_clr_reg = __io_address(U8500_PRCMU_BASE)
230 + PRCM_YYCLKEN0_MGT_CLR + clk->prcmu_cg_off;
232 writel(1 << clk->prcmu_cg_bit, cg_clr_reg);
235 /* ED doesn't have the combined set/clr registers */
236 static void clk_prcmu_ed_enable(struct clk *clk)
238 void __iomem *addr = __io_address(U8500_PRCMU_BASE)
241 writel(readl(addr) | PRCM_MGT_ENABLE, addr);
244 static void clk_prcmu_ed_disable(struct clk *clk)
246 void __iomem *addr = __io_address(U8500_PRCMU_BASE)
249 writel(readl(addr) & ~PRCM_MGT_ENABLE, addr);
252 static struct clkops clk_prcmu_ops = {
253 .enable = clk_prcmu_enable,
254 .disable = clk_prcmu_disable,
257 static unsigned int clkrst_base[] = {
258 [1] = U8500_CLKRST1_BASE,
259 [2] = U8500_CLKRST2_BASE,
260 [3] = U8500_CLKRST3_BASE,
261 [5] = U8500_CLKRST5_BASE,
262 [6] = U8500_CLKRST6_BASE,
263 [7] = U8500_CLKRST7_BASE_ED,
266 static void clk_prcc_enable(struct clk *clk)
268 void __iomem *addr = __io_address(clkrst_base[clk->cluster]);
270 if (clk->prcc_kernel != -1)
271 writel(1 << clk->prcc_kernel, addr + PRCC_KCKEN);
273 if (clk->prcc_bus != -1)
274 writel(1 << clk->prcc_bus, addr + PRCC_PCKEN);
277 static void clk_prcc_disable(struct clk *clk)
279 void __iomem *addr = __io_address(clkrst_base[clk->cluster]);
281 if (clk->prcc_bus != -1)
282 writel(1 << clk->prcc_bus, addr + PRCC_PCKDIS);
284 if (clk->prcc_kernel != -1)
285 writel(1 << clk->prcc_kernel, addr + PRCC_KCKDIS);
288 static struct clkops clk_prcc_ops = {
289 .enable = clk_prcc_enable,
290 .disable = clk_prcc_disable,
293 static struct clk clk_32khz = {
299 * PRCMU level clock gating
303 static DEFINE_PRCMU_CLK(svaclk, 0x0, 2, SVAMMDSPCLK);
304 static DEFINE_PRCMU_CLK(siaclk, 0x0, 3, SIAMMDSPCLK);
305 static DEFINE_PRCMU_CLK(sgaclk, 0x0, 4, SGACLK);
306 static DEFINE_PRCMU_CLK_RATE(uartclk, 0x0, 5, UARTCLK, 38400000);
307 static DEFINE_PRCMU_CLK(msp02clk, 0x0, 6, MSP02CLK);
308 static DEFINE_PRCMU_CLK(msp1clk, 0x0, 7, MSP1CLK); /* v1 */
309 static DEFINE_PRCMU_CLK_RATE(i2cclk, 0x0, 8, I2CCLK, 48000000);
310 static DEFINE_PRCMU_CLK_RATE(sdmmcclk, 0x0, 9, SDMMCCLK, 50000000);
311 static DEFINE_PRCMU_CLK(slimclk, 0x0, 10, SLIMCLK);
312 static DEFINE_PRCMU_CLK(per1clk, 0x0, 11, PER1CLK);
313 static DEFINE_PRCMU_CLK(per2clk, 0x0, 12, PER2CLK);
314 static DEFINE_PRCMU_CLK(per3clk, 0x0, 13, PER3CLK);
315 static DEFINE_PRCMU_CLK(per5clk, 0x0, 14, PER5CLK);
316 static DEFINE_PRCMU_CLK_RATE(per6clk, 0x0, 15, PER6CLK, 133330000);
317 static DEFINE_PRCMU_CLK_RATE(per7clk, 0x0, 16, PER7CLK, 100000000);
318 static DEFINE_PRCMU_CLK(lcdclk, 0x0, 17, LCDCLK);
319 static DEFINE_PRCMU_CLK(bmlclk, 0x0, 18, BMLCLK);
320 static DEFINE_PRCMU_CLK(hsitxclk, 0x0, 19, HSITXCLK);
321 static DEFINE_PRCMU_CLK(hsirxclk, 0x0, 20, HSIRXCLK);
322 static DEFINE_PRCMU_CLK(hdmiclk, 0x0, 21, HDMICLK);
323 static DEFINE_PRCMU_CLK(apeatclk, 0x0, 22, APEATCLK);
324 static DEFINE_PRCMU_CLK(apetraceclk, 0x0, 23, APETRACECLK);
325 static DEFINE_PRCMU_CLK(mcdeclk, 0x0, 24, MCDECLK);
326 static DEFINE_PRCMU_CLK(ipi2clk, 0x0, 25, IPI2CCLK);
327 static DEFINE_PRCMU_CLK(dsialtclk, 0x0, 26, DSIALTCLK); /* v1 */
328 static DEFINE_PRCMU_CLK(dmaclk, 0x0, 27, DMACLK);
329 static DEFINE_PRCMU_CLK(b2r2clk, 0x0, 28, B2R2CLK);
330 static DEFINE_PRCMU_CLK(tvclk, 0x0, 29, TVCLK);
331 static DEFINE_PRCMU_CLK(uniproclk, 0x0, 30, UNIPROCLK); /* v1 */
332 static DEFINE_PRCMU_CLK_RATE(sspclk, 0x0, 31, SSPCLK, 48000000); /* v1 */
335 static DEFINE_PRCMU_CLK(rngclk, 0x4, 0, RNGCLK); /* v1 */
336 static DEFINE_PRCMU_CLK(uiccclk, 0x4, 1, UICCCLK); /* v1 */
339 * PRCC level clock gating
340 * Format: per#, clk, PCKEN bit, KCKEN bit, parent
343 /* Peripheral Cluster #1 */
344 static DEFINE_PRCC_CLK(1, i2c4, 10, 9, &clk_i2cclk);
345 static DEFINE_PRCC_CLK(1, gpio0, 9, -1, NULL);
346 static DEFINE_PRCC_CLK(1, slimbus0, 8, 8, &clk_slimclk);
347 static DEFINE_PRCC_CLK(1, spi3_ed, 7, 7, NULL);
348 static DEFINE_PRCC_CLK(1, spi3_v1, 7, -1, NULL);
349 static DEFINE_PRCC_CLK(1, i2c2, 6, 6, &clk_i2cclk);
350 static DEFINE_PRCC_CLK(1, sdi0, 5, 5, &clk_sdmmcclk);
351 static DEFINE_PRCC_CLK(1, msp1_ed, 4, 4, &clk_msp02clk);
352 static DEFINE_PRCC_CLK(1, msp1_v1, 4, 4, &clk_msp1clk);
353 static DEFINE_PRCC_CLK(1, msp0, 3, 3, &clk_msp02clk);
354 static DEFINE_PRCC_CLK(1, i2c1, 2, 2, &clk_i2cclk);
355 static DEFINE_PRCC_CLK(1, uart1, 1, 1, &clk_uartclk);
356 static DEFINE_PRCC_CLK(1, uart0, 0, 0, &clk_uartclk);
358 /* Peripheral Cluster #2 */
360 static DEFINE_PRCC_CLK(2, gpio1_ed, 12, -1, NULL);
361 static DEFINE_PRCC_CLK(2, ssitx_ed, 11, -1, NULL);
362 static DEFINE_PRCC_CLK(2, ssirx_ed, 10, -1, NULL);
363 static DEFINE_PRCC_CLK(2, spi0_ed, 9, -1, NULL);
364 static DEFINE_PRCC_CLK(2, sdi3_ed, 8, 6, &clk_sdmmcclk);
365 static DEFINE_PRCC_CLK(2, sdi1_ed, 7, 5, &clk_sdmmcclk);
366 static DEFINE_PRCC_CLK(2, msp2_ed, 6, 4, &clk_msp02clk);
367 static DEFINE_PRCC_CLK(2, sdi4_ed, 4, 2, &clk_sdmmcclk);
368 static DEFINE_PRCC_CLK(2, pwl_ed, 3, 1, NULL);
369 static DEFINE_PRCC_CLK(2, spi1_ed, 2, -1, NULL);
370 static DEFINE_PRCC_CLK(2, spi2_ed, 1, -1, NULL);
371 static DEFINE_PRCC_CLK(2, i2c3_ed, 0, 0, &clk_i2cclk);
373 static DEFINE_PRCC_CLK(2, gpio1_v1, 11, -1, NULL);
374 static DEFINE_PRCC_CLK(2, ssitx_v1, 10, 7, NULL);
375 static DEFINE_PRCC_CLK(2, ssirx_v1, 9, 6, NULL);
376 static DEFINE_PRCC_CLK(2, spi0_v1, 8, -1, NULL);
377 static DEFINE_PRCC_CLK(2, sdi3_v1, 7, 5, &clk_sdmmcclk);
378 static DEFINE_PRCC_CLK(2, sdi1_v1, 6, 4, &clk_sdmmcclk);
379 static DEFINE_PRCC_CLK(2, msp2_v1, 5, 3, &clk_msp02clk);
380 static DEFINE_PRCC_CLK(2, sdi4_v1, 4, 2, &clk_sdmmcclk);
381 static DEFINE_PRCC_CLK(2, pwl_v1, 3, 1, NULL);
382 static DEFINE_PRCC_CLK(2, spi1_v1, 2, -1, NULL);
383 static DEFINE_PRCC_CLK(2, spi2_v1, 1, -1, NULL);
384 static DEFINE_PRCC_CLK(2, i2c3_v1, 0, 0, &clk_i2cclk);
386 /* Peripheral Cluster #3 */
387 static DEFINE_PRCC_CLK(3, gpio2, 8, -1, NULL);
388 static DEFINE_PRCC_CLK(3, sdi5, 7, 7, &clk_sdmmcclk);
389 static DEFINE_PRCC_CLK(3, uart2, 6, 6, &clk_uartclk);
390 static DEFINE_PRCC_CLK(3, ske, 5, 5, &clk_32khz);
391 static DEFINE_PRCC_CLK(3, sdi2, 4, 4, &clk_sdmmcclk);
392 static DEFINE_PRCC_CLK(3, i2c0, 3, 3, &clk_i2cclk);
393 static DEFINE_PRCC_CLK(3, ssp1_ed, 2, 2, &clk_i2cclk);
394 static DEFINE_PRCC_CLK(3, ssp0_ed, 1, 1, &clk_i2cclk);
395 static DEFINE_PRCC_CLK(3, ssp1_v1, 2, 2, &clk_sspclk);
396 static DEFINE_PRCC_CLK(3, ssp0_v1, 1, 1, &clk_sspclk);
397 static DEFINE_PRCC_CLK(3, fsmc, 0, -1, NULL);
399 /* Peripheral Cluster #4 is in the always on domain */
401 /* Peripheral Cluster #5 */
402 static DEFINE_PRCC_CLK(5, gpio3, 1, -1, NULL);
403 static DEFINE_PRCC_CLK(5, usb_ed, 0, 0, &clk_i2cclk);
404 static DEFINE_PRCC_CLK(5, usb_v1, 0, 0, NULL);
406 /* Peripheral Cluster #6 */
409 static DEFINE_PRCC_CLK_CUSTOM(6, mtu1_v1, 8, -1, NULL, clk_mtu_get_rate, 1);
410 static DEFINE_PRCC_CLK_CUSTOM(6, mtu0_v1, 7, -1, NULL, clk_mtu_get_rate, 0);
411 static DEFINE_PRCC_CLK(6, cfgreg_v1, 6, 6, NULL);
412 static DEFINE_PRCC_CLK(6, dmc_ed, 6, 6, NULL);
413 static DEFINE_PRCC_CLK(6, hash1, 5, -1, NULL);
414 static DEFINE_PRCC_CLK(6, unipro_v1, 4, 1, &clk_uniproclk);
415 static DEFINE_PRCC_CLK(6, cryp1_ed, 4, -1, NULL);
416 static DEFINE_PRCC_CLK(6, pka, 3, -1, NULL);
417 static DEFINE_PRCC_CLK(6, hash0, 2, -1, NULL);
418 static DEFINE_PRCC_CLK(6, cryp0, 1, -1, NULL);
419 static DEFINE_PRCC_CLK(6, rng_ed, 0, 0, &clk_i2cclk);
420 static DEFINE_PRCC_CLK(6, rng_v1, 0, 0, &clk_rngclk);
422 /* Peripheral Cluster #7 */
424 static DEFINE_PRCC_CLK(7, tzpc0_ed, 4, -1, NULL);
426 static DEFINE_PRCC_CLK_CUSTOM(7, mtu1_ed, 3, -1, NULL, clk_mtu_get_rate, 1);
427 static DEFINE_PRCC_CLK_CUSTOM(7, mtu0_ed, 2, -1, NULL, clk_mtu_get_rate, 0);
428 static DEFINE_PRCC_CLK(7, wdg_ed, 1, -1, NULL);
429 static DEFINE_PRCC_CLK(7, cfgreg_ed, 0, -1, NULL);
431 static struct clk clk_dummy_apb_pclk = {
435 static struct clk_lookup u8500_common_clks[] = {
436 CLK(dummy_apb_pclk, NULL, "apb_pclk"),
438 /* Peripheral Cluster #1 */
439 CLK(gpio0, "gpio.0", NULL),
440 CLK(gpio0, "gpio.1", NULL),
441 CLK(slimbus0, "slimbus0", NULL),
442 CLK(i2c2, "nmk-i2c.2", NULL),
443 CLK(sdi0, "sdi0", NULL),
444 CLK(msp0, "msp0", NULL),
445 CLK(i2c1, "nmk-i2c.1", NULL),
446 CLK(uart1, "uart1", NULL),
447 CLK(uart0, "uart0", NULL),
449 /* Peripheral Cluster #3 */
450 CLK(gpio2, "gpio.2", NULL),
451 CLK(gpio2, "gpio.3", NULL),
452 CLK(gpio2, "gpio.4", NULL),
453 CLK(gpio2, "gpio.5", NULL),
454 CLK(sdi5, "sdi5", NULL),
455 CLK(uart2, "uart2", NULL),
456 CLK(ske, "ske", NULL),
457 CLK(ske, "nmk-ske-keypad", NULL),
458 CLK(sdi2, "sdi2", NULL),
459 CLK(i2c0, "nmk-i2c.0", NULL),
460 CLK(fsmc, "fsmc", NULL),
462 /* Peripheral Cluster #5 */
463 CLK(gpio3, "gpio.8", NULL),
465 /* Peripheral Cluster #6 */
466 CLK(hash1, "hash1", NULL),
467 CLK(pka, "pka", NULL),
468 CLK(hash0, "hash0", NULL),
469 CLK(cryp0, "cryp0", NULL),
471 /* PRCMU level clock gating */
474 CLK(svaclk, "sva", NULL),
475 CLK(siaclk, "sia", NULL),
476 CLK(sgaclk, "sga", NULL),
477 CLK(slimclk, "slim", NULL),
478 CLK(lcdclk, "lcd", NULL),
479 CLK(bmlclk, "bml", NULL),
480 CLK(hsitxclk, "stm-hsi.0", NULL),
481 CLK(hsirxclk, "stm-hsi.1", NULL),
482 CLK(hdmiclk, "hdmi", NULL),
483 CLK(apeatclk, "apeat", NULL),
484 CLK(apetraceclk, "apetrace", NULL),
485 CLK(mcdeclk, "mcde", NULL),
486 CLK(ipi2clk, "ipi2", NULL),
487 CLK(dmaclk, "dma40.0", NULL),
488 CLK(b2r2clk, "b2r2", NULL),
489 CLK(tvclk, "tv", NULL),
492 static struct clk_lookup u8500_ed_clks[] = {
493 /* Peripheral Cluster #1 */
494 CLK(spi3_ed, "spi3", NULL),
495 CLK(msp1_ed, "msp1", NULL),
497 /* Peripheral Cluster #2 */
498 CLK(gpio1_ed, "gpio.6", NULL),
499 CLK(gpio1_ed, "gpio.7", NULL),
500 CLK(ssitx_ed, "ssitx", NULL),
501 CLK(ssirx_ed, "ssirx", NULL),
502 CLK(spi0_ed, "spi0", NULL),
503 CLK(sdi3_ed, "sdi3", NULL),
504 CLK(sdi1_ed, "sdi1", NULL),
505 CLK(msp2_ed, "msp2", NULL),
506 CLK(sdi4_ed, "sdi4", NULL),
507 CLK(pwl_ed, "pwl", NULL),
508 CLK(spi1_ed, "spi1", NULL),
509 CLK(spi2_ed, "spi2", NULL),
510 CLK(i2c3_ed, "nmk-i2c.3", NULL),
512 /* Peripheral Cluster #3 */
513 CLK(ssp1_ed, "ssp1", NULL),
514 CLK(ssp0_ed, "ssp0", NULL),
516 /* Peripheral Cluster #5 */
517 CLK(usb_ed, "musb_hdrc.0", "usb"),
519 /* Peripheral Cluster #6 */
520 CLK(dmc_ed, "dmc", NULL),
521 CLK(cryp1_ed, "cryp1", NULL),
522 CLK(rng_ed, "rng", NULL),
524 /* Peripheral Cluster #7 */
525 CLK(tzpc0_ed, "tzpc0", NULL),
526 CLK(mtu1_ed, "mtu1", NULL),
527 CLK(mtu0_ed, "mtu0", NULL),
528 CLK(wdg_ed, "wdg", NULL),
529 CLK(cfgreg_ed, "cfgreg", NULL),
532 static struct clk_lookup u8500_v1_clks[] = {
533 /* Peripheral Cluster #1 */
534 CLK(i2c4, "nmk-i2c.4", NULL),
535 CLK(spi3_v1, "spi3", NULL),
536 CLK(msp1_v1, "msp1", NULL),
538 /* Peripheral Cluster #2 */
539 CLK(gpio1_v1, "gpio.6", NULL),
540 CLK(gpio1_v1, "gpio.7", NULL),
541 CLK(ssitx_v1, "ssitx", NULL),
542 CLK(ssirx_v1, "ssirx", NULL),
543 CLK(spi0_v1, "spi0", NULL),
544 CLK(sdi3_v1, "sdi3", NULL),
545 CLK(sdi1_v1, "sdi1", NULL),
546 CLK(msp2_v1, "msp2", NULL),
547 CLK(sdi4_v1, "sdi4", NULL),
548 CLK(pwl_v1, "pwl", NULL),
549 CLK(spi1_v1, "spi1", NULL),
550 CLK(spi2_v1, "spi2", NULL),
551 CLK(i2c3_v1, "nmk-i2c.3", NULL),
553 /* Peripheral Cluster #3 */
554 CLK(ssp1_v1, "ssp1", NULL),
555 CLK(ssp0_v1, "ssp0", NULL),
557 /* Peripheral Cluster #5 */
558 CLK(usb_v1, "musb_hdrc.0", "usb"),
560 /* Peripheral Cluster #6 */
561 CLK(mtu1_v1, "mtu1", NULL),
562 CLK(mtu0_v1, "mtu0", NULL),
563 CLK(cfgreg_v1, "cfgreg", NULL),
564 CLK(hash1, "hash1", NULL),
565 CLK(unipro_v1, "unipro", NULL),
566 CLK(rng_v1, "rng", NULL),
568 /* PRCMU level clock gating */
571 CLK(uniproclk, "uniproclk", NULL),
572 CLK(dsialtclk, "dsialt", NULL),
575 CLK(rngclk, "rng", NULL),
576 CLK(uiccclk, "uicc", NULL),
579 #ifdef CONFIG_DEBUG_FS
581 * debugfs support to trace clock tree hierarchy and attributes with
584 static struct dentry *clk_debugfs_root;
586 void __init clk_debugfs_add_table(struct clk_lookup *cl, size_t num)
589 /* Check that the clock has not been already registered */
590 if (!(cl->clk->list.prev != cl->clk->list.next))
591 list_add_tail(&cl->clk->list, &clk_list);
597 static ssize_t usecount_dbg_read(struct file *file, char __user *buf,
598 size_t size, loff_t *off)
600 struct clk *clk = file->f_dentry->d_inode->i_private;
604 len = sprintf(cusecount, "%u\n", clk->enabled);
605 return simple_read_from_buffer(buf, size, off, cusecount, len);
608 static ssize_t rate_dbg_read(struct file *file, char __user *buf,
609 size_t size, loff_t *off)
611 struct clk *clk = file->f_dentry->d_inode->i_private;
616 rate = clk_get_rate(clk);
617 len = sprintf(crate, "%u\n", rate);
618 return simple_read_from_buffer(buf, size, off, crate, len);
621 static const struct file_operations usecount_fops = {
622 .read = usecount_dbg_read,
625 static const struct file_operations set_rate_fops = {
626 .read = rate_dbg_read,
629 static struct dentry *clk_debugfs_register_dir(struct clk *c,
630 struct dentry *p_dentry)
632 struct dentry *d, *clk_d, *child, *child_tmp;
637 p += sprintf(p, "BUG");
639 p += sprintf(p, "%s", c->name);
641 clk_d = debugfs_create_dir(s, p_dentry);
645 d = debugfs_create_file("usecount", S_IRUGO,
646 clk_d, c, &usecount_fops);
649 d = debugfs_create_file("rate", S_IRUGO,
650 clk_d, c, &set_rate_fops);
654 * TODO : not currently available in ux500
655 * d = debugfs_create_x32("flags", S_IRUGO, clk_d, (u32 *)&c->flags);
664 list_for_each_entry_safe(child, child_tmp, &d->d_subdirs, d_u.d_child)
665 debugfs_remove(child);
666 debugfs_remove(clk_d);
670 static void clk_debugfs_remove_dir(struct dentry *cdentry)
672 struct dentry *d, *child, *child_tmp;
675 list_for_each_entry_safe(child, child_tmp, &d->d_subdirs, d_u.d_child)
676 debugfs_remove(child);
677 debugfs_remove(cdentry);
681 static int clk_debugfs_register_one(struct clk *c)
683 struct clk *pa = c->parent_periph;
684 struct clk *bpa = c->parent_cluster;
687 c->dent = clk_debugfs_register_dir(c,
688 pa ? pa->dent : clk_debugfs_root);
694 c->dent_bus = clk_debugfs_register_dir(c,
695 bpa->dent_bus ? bpa->dent_bus : bpa->dent);
696 if ((!c->dent_bus) && (c->dent)) {
697 clk_debugfs_remove_dir(c->dent);
705 static int clk_debugfs_register(struct clk *c)
708 struct clk *pa = c->parent_periph;
709 struct clk *bpa = c->parent_cluster;
711 if (pa && (!pa->dent && !pa->dent_bus)) {
712 err = clk_debugfs_register(pa);
717 if (bpa && (!bpa->dent && !bpa->dent_bus)) {
718 err = clk_debugfs_register(bpa);
723 if ((!c->dent) && (!c->dent_bus)) {
724 err = clk_debugfs_register_one(c);
731 static int __init clk_debugfs_init(void)
737 d = debugfs_create_dir("clock", NULL);
740 clk_debugfs_root = d;
742 list_for_each_entry(c, &clk_list, list) {
743 err = clk_debugfs_register(c);
749 debugfs_remove_recursive(clk_debugfs_root);
753 late_initcall(clk_debugfs_init);
754 #endif /* defined(CONFIG_DEBUG_FS) */
756 int __init clk_init(void)
758 if (cpu_is_u8500ed()) {
759 clk_prcmu_ops.enable = clk_prcmu_ed_enable;
760 clk_prcmu_ops.disable = clk_prcmu_ed_disable;
761 clk_per6clk.rate = 100000000;
762 } else if (cpu_is_u5500()) {
763 /* Clock tree for U5500 not implemented yet */
764 clk_prcc_ops.enable = clk_prcc_ops.disable = NULL;
765 clk_prcmu_ops.enable = clk_prcmu_ops.disable = NULL;
766 clk_uartclk.rate = 36360000;
767 clk_sdmmcclk.rate = 99900000;
770 clkdev_add_table(u8500_common_clks, ARRAY_SIZE(u8500_common_clks));
771 if (cpu_is_u8500ed())
772 clkdev_add_table(u8500_ed_clks, ARRAY_SIZE(u8500_ed_clks));
774 clkdev_add_table(u8500_v1_clks, ARRAY_SIZE(u8500_v1_clks));
776 #ifdef CONFIG_DEBUG_FS
777 clk_debugfs_add_table(u8500_common_clks, ARRAY_SIZE(u8500_common_clks));
778 if (cpu_is_u8500ed())
779 clk_debugfs_add_table(u8500_ed_clks, ARRAY_SIZE(u8500_ed_clks));
781 clk_debugfs_add_table(u8500_v1_clks, ARRAY_SIZE(u8500_v1_clks));