2 * Copyright (C) ST-Ericsson SA 2010
4 * Author: Hanumath Prasad <hanumath.prasad@stericsson.com>
5 * License terms: GNU General Public License (GPL) version 2
8 #include <linux/kernel.h>
9 #include <linux/gpio.h>
10 #include <linux/amba/bus.h>
11 #include <linux/amba/mmci.h>
12 #include <linux/mmc/host.h>
13 #include <linux/platform_device.h>
15 #include <plat/pincfg.h>
16 #include <plat/ste_dma40.h>
17 #include <mach/devices.h>
18 #include <mach/hardware.h>
20 #include "devices-db8500.h"
21 #include "pins-db8500.h"
22 #include "board-mop500.h"
23 #include "ste-dma40-db8500.h"
25 static pin_cfg_t mop500_sdi_pins[] = {
26 /* SDI0 (MicroSD slot) */
39 /* SDI4 (on-board eMMC) */
53 static pin_cfg_t mop500_sdi2_pins[] = {
69 * SDI 0 (MicroSD slot)
73 #define MCI_DATA2DIREN (1 << 2)
74 #define MCI_CMDDIREN (1 << 3)
75 #define MCI_DATA0DIREN (1 << 4)
76 #define MCI_DATA31DIREN (1 << 5)
77 #define MCI_FBCLKEN (1 << 7)
79 static u32 mop500_sdi0_vdd_handler(struct device *dev, unsigned int vdd,
80 unsigned char power_mode)
82 if (power_mode == MMC_POWER_UP)
83 gpio_set_value_cansleep(GPIO_SDMMC_EN, 1);
84 else if (power_mode == MMC_POWER_OFF)
85 gpio_set_value_cansleep(GPIO_SDMMC_EN, 0);
87 return MCI_FBCLKEN | MCI_CMDDIREN | MCI_DATA0DIREN |
88 MCI_DATA2DIREN | MCI_DATA31DIREN;
91 #ifdef CONFIG_STE_DMA40
92 struct stedma40_chan_cfg mop500_sdi0_dma_cfg_rx = {
93 .mode = STEDMA40_MODE_LOGICAL,
94 .dir = STEDMA40_PERIPH_TO_MEM,
95 .src_dev_type = DB8500_DMA_DEV29_SD_MM0_RX,
96 .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
97 .src_info.data_width = STEDMA40_WORD_WIDTH,
98 .dst_info.data_width = STEDMA40_WORD_WIDTH,
101 static struct stedma40_chan_cfg mop500_sdi0_dma_cfg_tx = {
102 .mode = STEDMA40_MODE_LOGICAL,
103 .dir = STEDMA40_MEM_TO_PERIPH,
104 .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
105 .dst_dev_type = DB8500_DMA_DEV29_SD_MM0_TX,
106 .src_info.data_width = STEDMA40_WORD_WIDTH,
107 .dst_info.data_width = STEDMA40_WORD_WIDTH,
111 static struct mmci_platform_data mop500_sdi0_data = {
112 .vdd_handler = mop500_sdi0_vdd_handler,
113 .ocr_mask = MMC_VDD_29_30,
115 .capabilities = MMC_CAP_4_BIT_DATA,
116 .gpio_cd = GPIO_SDMMC_CD,
118 #ifdef CONFIG_STE_DMA40
119 .dma_filter = stedma40_filter,
120 .dma_rx_param = &mop500_sdi0_dma_cfg_rx,
121 .dma_tx_param = &mop500_sdi0_dma_cfg_tx,
125 void mop500_sdi_tc35892_init(void)
129 ret = gpio_request(GPIO_SDMMC_EN, "SDMMC_EN");
131 ret = gpio_request(GPIO_SDMMC_1V8_3V_SEL,
132 "GPIO_SDMMC_1V8_3V_SEL");
136 gpio_direction_output(GPIO_SDMMC_1V8_3V_SEL, 0);
137 gpio_direction_output(GPIO_SDMMC_EN, 1);
139 db8500_add_sdi0(&mop500_sdi0_data);
143 * SDI 2 (POP eMMC, not on DB8500ed)
146 #ifdef CONFIG_STE_DMA40
147 struct stedma40_chan_cfg mop500_sdi2_dma_cfg_rx = {
148 .mode = STEDMA40_MODE_LOGICAL,
149 .dir = STEDMA40_PERIPH_TO_MEM,
150 .src_dev_type = DB8500_DMA_DEV28_SD_MM2_RX,
151 .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
152 .src_info.data_width = STEDMA40_WORD_WIDTH,
153 .dst_info.data_width = STEDMA40_WORD_WIDTH,
156 static struct stedma40_chan_cfg mop500_sdi2_dma_cfg_tx = {
157 .mode = STEDMA40_MODE_LOGICAL,
158 .dir = STEDMA40_MEM_TO_PERIPH,
159 .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
160 .dst_dev_type = DB8500_DMA_DEV28_SD_MM2_TX,
161 .src_info.data_width = STEDMA40_WORD_WIDTH,
162 .dst_info.data_width = STEDMA40_WORD_WIDTH,
166 static struct mmci_platform_data mop500_sdi2_data = {
167 .ocr_mask = MMC_VDD_165_195,
169 .capabilities = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
172 #ifdef CONFIG_STE_DMA40
173 .dma_filter = stedma40_filter,
174 .dma_rx_param = &mop500_sdi2_dma_cfg_rx,
175 .dma_tx_param = &mop500_sdi2_dma_cfg_tx,
180 * SDI 4 (on-board eMMC)
183 #ifdef CONFIG_STE_DMA40
184 struct stedma40_chan_cfg mop500_sdi4_dma_cfg_rx = {
185 .mode = STEDMA40_MODE_LOGICAL,
186 .dir = STEDMA40_PERIPH_TO_MEM,
187 .src_dev_type = DB8500_DMA_DEV42_SD_MM4_RX,
188 .dst_dev_type = STEDMA40_DEV_DST_MEMORY,
189 .src_info.data_width = STEDMA40_WORD_WIDTH,
190 .dst_info.data_width = STEDMA40_WORD_WIDTH,
193 static struct stedma40_chan_cfg mop500_sdi4_dma_cfg_tx = {
194 .mode = STEDMA40_MODE_LOGICAL,
195 .dir = STEDMA40_MEM_TO_PERIPH,
196 .src_dev_type = STEDMA40_DEV_SRC_MEMORY,
197 .dst_dev_type = DB8500_DMA_DEV42_SD_MM4_TX,
198 .src_info.data_width = STEDMA40_WORD_WIDTH,
199 .dst_info.data_width = STEDMA40_WORD_WIDTH,
203 static struct mmci_platform_data mop500_sdi4_data = {
204 .ocr_mask = MMC_VDD_29_30,
206 .capabilities = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA |
207 MMC_CAP_MMC_HIGHSPEED,
210 #ifdef CONFIG_STE_DMA40
211 .dma_filter = stedma40_filter,
212 .dma_rx_param = &mop500_sdi4_dma_cfg_rx,
213 .dma_tx_param = &mop500_sdi4_dma_cfg_tx,
217 void __init mop500_sdi_init(void)
219 nmk_config_pins(mop500_sdi_pins, ARRAY_SIZE(mop500_sdi_pins));
222 * sdi0 will finally be added when the TC35892 initializes and calls
223 * mop500_sdi_tc35892_init() above.
227 if (!cpu_is_u8500ed()) {
228 nmk_config_pins(mop500_sdi2_pins, ARRAY_SIZE(mop500_sdi2_pins));
229 /* POP eMMC on v1.0 has problems with high speed */
230 if (!cpu_is_u8500v10())
231 mop500_sdi2_data.capabilities |= MMC_CAP_MMC_HIGHSPEED;
232 db8500_add_sdi2(&mop500_sdi2_data);
236 db8500_add_sdi4(&mop500_sdi4_data);