arch/arm/mach-u300/timer.c

   1 /*
   2  *
   3  * arch/arm/mach-u300/timer.c
   4  *
   5  *
   6  * Copyright (C) 2007-2009 ST-Ericsson AB
   7  * License terms: GNU General Public License (GPL) version 2
   8  * Timer COH 901 328, runs the OS timer interrupt.
   9  * Author: Linus Walleij <linus.walleij@stericsson.com>
  10  */
  11 #include <linux/interrupt.h>
  12 #include <linux/time.h>
  13 #include <linux/timex.h>
  14 #include <linux/clockchips.h>
  15 #include <linux/clocksource.h>
  16 #include <linux/types.h>
  17 #include <linux/io.h>
  18 #include <linux/clk.h>
  19 #include <linux/err.h>
  20
  21 #include <mach/hardware.h>
  22
  23 /* Generic stuff */
  24 #include <asm/sched_clock.h>
  25 #include <asm/mach/map.h>
  26 #include <asm/mach/time.h>
  27 #include <asm/mach/irq.h>
  28
  29 /*
  30  * APP side special timer registers
  31  * This timer contains four timers which can fire an interrupt each.
  32  * OS (operating system) timer @ 32768 Hz
  33  * DD (device driver) timer @ 1 kHz
  34  * GP1 (general purpose 1) timer @ 1MHz
  35  * GP2 (general purpose 2) timer @ 1MHz
  36  */
  37
  38 /* Reset OS Timer 32bit (-/W) */
  39 #define U300_TIMER_APP_ROST                                     (0x0000)
  40 #define U300_TIMER_APP_ROST_TIMER_RESET                         (0x00000000)
  41 /* Enable OS Timer 32bit (-/W) */
  42 #define U300_TIMER_APP_EOST                                     (0x0004)
  43 #define U300_TIMER_APP_EOST_TIMER_ENABLE                        (0x00000000)
  44 /* Disable OS Timer 32bit (-/W) */
  45 #define U300_TIMER_APP_DOST                                     (0x0008)
  46 #define U300_TIMER_APP_DOST_TIMER_DISABLE                       (0x00000000)
  47 /* OS Timer Mode Register 32bit (-/W) */
  48 #define U300_TIMER_APP_SOSTM                                    (0x000c)
  49 #define U300_TIMER_APP_SOSTM_MODE_CONTINUOUS                    (0x00000000)
  50 #define U300_TIMER_APP_SOSTM_MODE_ONE_SHOT                      (0x00000001)
  51 /* OS Timer Status Register 32bit (R/-) */
  52 #define U300_TIMER_APP_OSTS                                     (0x0010)
  53 #define U300_TIMER_APP_OSTS_TIMER_STATE_MASK                    (0x0000000F)
  54 #define U300_TIMER_APP_OSTS_TIMER_STATE_IDLE                    (0x00000001)
  55 #define U300_TIMER_APP_OSTS_TIMER_STATE_ACTIVE                  (0x00000002)
  56 #define U300_TIMER_APP_OSTS_ENABLE_IND                          (0x00000010)
  57 #define U300_TIMER_APP_OSTS_MODE_MASK                           (0x00000020)
  58 #define U300_TIMER_APP_OSTS_MODE_CONTINUOUS                     (0x00000000)
  59 #define U300_TIMER_APP_OSTS_MODE_ONE_SHOT                       (0x00000020)
  60 #define U300_TIMER_APP_OSTS_IRQ_ENABLED_IND                     (0x00000040)
  61 #define U300_TIMER_APP_OSTS_IRQ_PENDING_IND                     (0x00000080)
  62 /* OS Timer Current Count Register 32bit (R/-) */
  63 #define U300_TIMER_APP_OSTCC                                    (0x0014)
  64 /* OS Timer Terminal Count Register 32bit (R/W) */
  65 #define U300_TIMER_APP_OSTTC                                    (0x0018)
  66 /* OS Timer Interrupt Enable Register 32bit (-/W) */
  67 #define U300_TIMER_APP_OSTIE                                    (0x001c)
  68 #define U300_TIMER_APP_OSTIE_IRQ_DISABLE                        (0x00000000)
  69 #define U300_TIMER_APP_OSTIE_IRQ_ENABLE                         (0x00000001)
  70 /* OS Timer Interrupt Acknowledge Register 32bit (-/W) */
  71 #define U300_TIMER_APP_OSTIA                                    (0x0020)
  72 #define U300_TIMER_APP_OSTIA_IRQ_ACK                            (0x00000080)
  73
  74 /* Reset DD Timer 32bit (-/W) */
  75 #define U300_TIMER_APP_RDDT                                     (0x0040)
  76 #define U300_TIMER_APP_RDDT_TIMER_RESET                         (0x00000000)
  77 /* Enable DD Timer 32bit (-/W) */
  78 #define U300_TIMER_APP_EDDT                                     (0x0044)
  79 #define U300_TIMER_APP_EDDT_TIMER_ENABLE                        (0x00000000)
  80 /* Disable DD Timer 32bit (-/W) */
  81 #define U300_TIMER_APP_DDDT                                     (0x0048)
  82 #define U300_TIMER_APP_DDDT_TIMER_DISABLE                       (0x00000000)
  83 /* DD Timer Mode Register 32bit (-/W) */
  84 #define U300_TIMER_APP_SDDTM                                    (0x004c)
  85 #define U300_TIMER_APP_SDDTM_MODE_CONTINUOUS                    (0x00000000)
  86 #define U300_TIMER_APP_SDDTM_MODE_ONE_SHOT                      (0x00000001)
  87 /* DD Timer Status Register 32bit (R/-) */
  88 #define U300_TIMER_APP_DDTS                                     (0x0050)
  89 #define U300_TIMER_APP_DDTS_TIMER_STATE_MASK                    (0x0000000F)
  90 #define U300_TIMER_APP_DDTS_TIMER_STATE_IDLE                    (0x00000001)
  91 #define U300_TIMER_APP_DDTS_TIMER_STATE_ACTIVE                  (0x00000002)
  92 #define U300_TIMER_APP_DDTS_ENABLE_IND                          (0x00000010)
  93 #define U300_TIMER_APP_DDTS_MODE_MASK                           (0x00000020)
  94 #define U300_TIMER_APP_DDTS_MODE_CONTINUOUS                     (0x00000000)
  95 #define U300_TIMER_APP_DDTS_MODE_ONE_SHOT                       (0x00000020)
  96 #define U300_TIMER_APP_DDTS_IRQ_ENABLED_IND                     (0x00000040)
  97 #define U300_TIMER_APP_DDTS_IRQ_PENDING_IND                     (0x00000080)
  98 /* DD Timer Current Count Register 32bit (R/-) */
  99 #define U300_TIMER_APP_DDTCC                                    (0x0054)
 100 /* DD Timer Terminal Count Register 32bit (R/W) */
 101 #define U300_TIMER_APP_DDTTC                                    (0x0058)
 102 /* DD Timer Interrupt Enable Register 32bit (-/W) */
 103 #define U300_TIMER_APP_DDTIE                                    (0x005c)
 104 #define U300_TIMER_APP_DDTIE_IRQ_DISABLE                        (0x00000000)
 105 #define U300_TIMER_APP_DDTIE_IRQ_ENABLE                         (0x00000001)
 106 /* DD Timer Interrupt Acknowledge Register 32bit (-/W) */
 107 #define U300_TIMER_APP_DDTIA                                    (0x0060)
 108 #define U300_TIMER_APP_DDTIA_IRQ_ACK                            (0x00000080)
 109
 110 /* Reset GP1 Timer 32bit (-/W) */
 111 #define U300_TIMER_APP_RGPT1                                    (0x0080)
 112 #define U300_TIMER_APP_RGPT1_TIMER_RESET                        (0x00000000)
 113 /* Enable GP1 Timer 32bit (-/W) */
 114 #define U300_TIMER_APP_EGPT1                                    (0x0084)
 115 #define U300_TIMER_APP_EGPT1_TIMER_ENABLE                       (0x00000000)
 116 /* Disable GP1 Timer 32bit (-/W) */
 117 #define U300_TIMER_APP_DGPT1                                    (0x0088)
 118 #define U300_TIMER_APP_DGPT1_TIMER_DISABLE                      (0x00000000)
 119 /* GP1 Timer Mode Register 32bit (-/W) */
 120 #define U300_TIMER_APP_SGPT1M                                   (0x008c)
 121 #define U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS                   (0x00000000)
 122 #define U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT                     (0x00000001)
 123 /* GP1 Timer Status Register 32bit (R/-) */
 124 #define U300_TIMER_APP_GPT1S                                    (0x0090)
 125 #define U300_TIMER_APP_GPT1S_TIMER_STATE_MASK                   (0x0000000F)
 126 #define U300_TIMER_APP_GPT1S_TIMER_STATE_IDLE                   (0x00000001)
 127 #define U300_TIMER_APP_GPT1S_TIMER_STATE_ACTIVE                 (0x00000002)
 128 #define U300_TIMER_APP_GPT1S_ENABLE_IND                         (0x00000010)
 129 #define U300_TIMER_APP_GPT1S_MODE_MASK                          (0x00000020)
 130 #define U300_TIMER_APP_GPT1S_MODE_CONTINUOUS                    (0x00000000)
 131 #define U300_TIMER_APP_GPT1S_MODE_ONE_SHOT                      (0x00000020)
 132 #define U300_TIMER_APP_GPT1S_IRQ_ENABLED_IND                    (0x00000040)
 133 #define U300_TIMER_APP_GPT1S_IRQ_PENDING_IND                    (0x00000080)
 134 /* GP1 Timer Current Count Register 32bit (R/-) */
 135 #define U300_TIMER_APP_GPT1CC                                   (0x0094)
 136 /* GP1 Timer Terminal Count Register 32bit (R/W) */
 137 #define U300_TIMER_APP_GPT1TC                                   (0x0098)
 138 /* GP1 Timer Interrupt Enable Register 32bit (-/W) */
 139 #define U300_TIMER_APP_GPT1IE                                   (0x009c)
 140 #define U300_TIMER_APP_GPT1IE_IRQ_DISABLE                       (0x00000000)
 141 #define U300_TIMER_APP_GPT1IE_IRQ_ENABLE                        (0x00000001)
 142 /* GP1 Timer Interrupt Acknowledge Register 32bit (-/W) */
 143 #define U300_TIMER_APP_GPT1IA                                   (0x00a0)
 144 #define U300_TIMER_APP_GPT1IA_IRQ_ACK                           (0x00000080)
 145
 146 /* Reset GP2 Timer 32bit (-/W) */
 147 #define U300_TIMER_APP_RGPT2                                    (0x00c0)
 148 #define U300_TIMER_APP_RGPT2_TIMER_RESET                        (0x00000000)
 149 /* Enable GP2 Timer 32bit (-/W) */
 150 #define U300_TIMER_APP_EGPT2                                    (0x00c4)
 151 #define U300_TIMER_APP_EGPT2_TIMER_ENABLE                       (0x00000000)
 152 /* Disable GP2 Timer 32bit (-/W) */
 153 #define U300_TIMER_APP_DGPT2                                    (0x00c8)
 154 #define U300_TIMER_APP_DGPT2_TIMER_DISABLE                      (0x00000000)
 155 /* GP2 Timer Mode Register 32bit (-/W) */
 156 #define U300_TIMER_APP_SGPT2M                                   (0x00cc)
 157 #define U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS                   (0x00000000)
 158 #define U300_TIMER_APP_SGPT2M_MODE_ONE_SHOT                     (0x00000001)
 159 /* GP2 Timer Status Register 32bit (R/-) */
 160 #define U300_TIMER_APP_GPT2S                                    (0x00d0)
 161 #define U300_TIMER_APP_GPT2S_TIMER_STATE_MASK                   (0x0000000F)
 162 #define U300_TIMER_APP_GPT2S_TIMER_STATE_IDLE                   (0x00000001)
 163 #define U300_TIMER_APP_GPT2S_TIMER_STATE_ACTIVE                 (0x00000002)
 164 #define U300_TIMER_APP_GPT2S_ENABLE_IND                         (0x00000010)
 165 #define U300_TIMER_APP_GPT2S_MODE_MASK                          (0x00000020)
 166 #define U300_TIMER_APP_GPT2S_MODE_CONTINUOUS                    (0x00000000)
 167 #define U300_TIMER_APP_GPT2S_MODE_ONE_SHOT                      (0x00000020)
 168 #define U300_TIMER_APP_GPT2S_IRQ_ENABLED_IND                    (0x00000040)
 169 #define U300_TIMER_APP_GPT2S_IRQ_PENDING_IND                    (0x00000080)
 170 /* GP2 Timer Current Count Register 32bit (R/-) */
 171 #define U300_TIMER_APP_GPT2CC                                   (0x00d4)
 172 /* GP2 Timer Terminal Count Register 32bit (R/W) */
 173 #define U300_TIMER_APP_GPT2TC                                   (0x00d8)
 174 /* GP2 Timer Interrupt Enable Register 32bit (-/W) */
 175 #define U300_TIMER_APP_GPT2IE                                   (0x00dc)
 176 #define U300_TIMER_APP_GPT2IE_IRQ_DISABLE                       (0x00000000)
 177 #define U300_TIMER_APP_GPT2IE_IRQ_ENABLE                        (0x00000001)
 178 /* GP2 Timer Interrupt Acknowledge Register 32bit (-/W) */
 179 #define U300_TIMER_APP_GPT2IA                                   (0x00e0)
 180 #define U300_TIMER_APP_GPT2IA_IRQ_ACK                           (0x00000080)
 181
 182 /* Clock request control register - all four timers */
 183 #define U300_TIMER_APP_CRC                                      (0x100)
 184 #define U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE                 (0x00000001)
 185
 186 #define TICKS_PER_JIFFY ((CLOCK_TICK_RATE + (HZ/2)) / HZ)
 187 #define US_PER_TICK ((1000000 + (HZ/2)) / HZ)
 188
 189 /*
 190  * The u300_set_mode() function is always called first, if we
 191  * have oneshot timer active, the oneshot scheduling function
 192  * u300_set_next_event() is called immediately after.
 193  */
 194 static void u300_set_mode(enum clock_event_mode mode,
 195                           struct clock_event_device *evt)
 196 {
 197         switch (mode) {
 198         case CLOCK_EVT_MODE_PERIODIC:
 199                 /* Disable interrupts on GPT1 */
 200                 writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
 201                        U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
 202                 /* Disable GP1 while we're reprogramming it. */
 203                 writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
 204                        U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1);
 205                 /*
 206                  * Set the periodic mode to a certain number of ticks per
 207                  * jiffy.
 208                  */
 209                 writel(TICKS_PER_JIFFY,
 210                        U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC);
 211                 /*
 212                  * Set continuous mode, so the timer keeps triggering
 213                  * interrupts.
 214                  */
 215                 writel(U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS,
 216                        U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M);
 217                 /* Enable timer interrupts */
 218                 writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
 219                        U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
 220                 /* Then enable the OS timer again */
 221                 writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
 222                        U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1);
 223                 break;
 224         case CLOCK_EVT_MODE_ONESHOT:
 225                 /* Just break; here? */
 226                 /*
 227                  * The actual event will be programmed by the next event hook,
 228                  * so we just set a dummy value somewhere at the end of the
 229                  * universe here.
 230                  */
 231                 /* Disable interrupts on GPT1 */
 232                 writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
 233                        U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
 234                 /* Disable GP1 while we're reprogramming it. */
 235                 writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
 236                        U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1);
 237                 /*
 238                  * Expire far in the future, u300_set_next_event() will be
 239                  * called soon...
 240                  */
 241                 writel(0xFFFFFFFF, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC);
 242                 /* We run one shot per tick here! */
 243                 writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT,
 244                        U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M);
 245                 /* Enable interrupts for this timer */
 246                 writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
 247                        U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
 248                 /* Enable timer */
 249                 writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
 250                        U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1);
 251                 break;
 252         case CLOCK_EVT_MODE_UNUSED:
 253         case CLOCK_EVT_MODE_SHUTDOWN:
 254                 /* Disable interrupts on GP1 */
 255                 writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
 256                        U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
 257                 /* Disable GP1 */
 258                 writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
 259                        U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1);
 260                 break;
 261         case CLOCK_EVT_MODE_RESUME:
 262                 /* Ignore this call */
 263                 break;
 264         }
 265 }
 266
 267 /*
 268  * The app timer in one shot mode obviously has to be reprogrammed
 269  * in EXACTLY this sequence to work properly. Do NOT try to e.g. replace
 270  * the interrupt disable + timer disable commands with a reset command,
 271  * it will fail miserably. Apparently (and I found this the hard way)
 272  * the timer is very sensitive to the instruction order, though you don't
 273  * get that impression from the data sheet.
 274  */
 275 static int u300_set_next_event(unsigned long cycles,
 276                                struct clock_event_device *evt)
 277
 278 {
 279         /* Disable interrupts on GPT1 */
 280         writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
 281                U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
 282         /* Disable GP1 while we're reprogramming it. */
 283         writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
 284                U300_TIMER_APP_VBASE + U300_TIMER_APP_DGPT1);
 285         /* Reset the General Purpose timer 1. */
 286         writel(U300_TIMER_APP_RGPT1_TIMER_RESET,
 287                U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT1);
 288         /* IRQ in n * cycles */
 289         writel(cycles, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1TC);
 290         /*
 291          * We run one shot per tick here! (This is necessary to reconfigure,
 292          * the timer will tilt if you don't!)
 293          */
 294         writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT,
 295                U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT1M);
 296         /* Enable timer interrupts */
 297         writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
 298                U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IE);
 299         /* Then enable the OS timer again */
 300         writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
 301                U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT1);
 302         return 0;
 303 }
 304
 305
 306 /* Use general purpose timer 1 as clock event */
 307 static struct clock_event_device clockevent_u300_1mhz = {
 308         .name           = "GPT1",
 309         .rating         = 300, /* Reasonably fast and accurate clock event */
 310         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 311         .set_next_event = u300_set_next_event,
 312         .set_mode       = u300_set_mode,
 313 };
 314
 315 /* Clock event timer interrupt handler */
 316 static irqreturn_t u300_timer_interrupt(int irq, void *dev_id)
 317 {
 318         struct clock_event_device *evt = &clockevent_u300_1mhz;
 319         /* ACK/Clear timer IRQ for the APP GPT1 Timer */
 320         writel(U300_TIMER_APP_GPT1IA_IRQ_ACK,
 321                 U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT1IA);
 322         evt->event_handler(evt);
 323         return IRQ_HANDLED;
 324 }
 325
 326 static struct irqaction u300_timer_irq = {
 327         .name           = "U300 Timer Tick",
 328         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 329         .handler        = u300_timer_interrupt,
 330 };
 331
 332 /*
 333  * Override the global weak sched_clock symbol with this
 334  * local implementation which uses the clocksource to get some
 335  * better resolution when scheduling the kernel. We accept that
 336  * this wraps around for now, since it is just a relative time
 337  * stamp. (Inspired by OMAP implementation.)
 338  */
 339
 340 static u32 notrace u300_read_sched_clock(void)
 341 {
 342         return readl(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC);
 343 }
 344
 345
 346 /*
 347  * This sets up the system timers, clock source and clock event.
 348  */
 349 static void __init u300_timer_init(void)
 350 {
 351         struct clk *clk;
 352         unsigned long rate;
 353
 354         /* Clock the interrupt controller */
 355         clk = clk_get_sys("apptimer", NULL);
 356         BUG_ON(IS_ERR(clk));
 357         clk_enable(clk);
 358         rate = clk_get_rate(clk);
 359
 360         setup_sched_clock(u300_read_sched_clock, 32, rate);
 361
 362         /*
 363          * Disable the "OS" and "DD" timers - these are designed for Symbian!
 364          * Example usage in cnh1601578 cpu subsystem pd_timer_app.c
 365          */
 366         writel(U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE,
 367                 U300_TIMER_APP_VBASE + U300_TIMER_APP_CRC);
 368         writel(U300_TIMER_APP_ROST_TIMER_RESET,
 369                 U300_TIMER_APP_VBASE + U300_TIMER_APP_ROST);
 370         writel(U300_TIMER_APP_DOST_TIMER_DISABLE,
 371                 U300_TIMER_APP_VBASE + U300_TIMER_APP_DOST);
 372         writel(U300_TIMER_APP_RDDT_TIMER_RESET,
 373                 U300_TIMER_APP_VBASE + U300_TIMER_APP_RDDT);
 374         writel(U300_TIMER_APP_DDDT_TIMER_DISABLE,
 375                 U300_TIMER_APP_VBASE + U300_TIMER_APP_DDDT);
 376
 377         /* Reset the General Purpose timer 1. */
 378         writel(U300_TIMER_APP_RGPT1_TIMER_RESET,
 379                 U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT1);
 380
 381         /* Set up the IRQ handler */
 382         setup_irq(IRQ_U300_TIMER_APP_GP1, &u300_timer_irq);
 383
 384         /* Reset the General Purpose timer 2 */
 385         writel(U300_TIMER_APP_RGPT2_TIMER_RESET,
 386                 U300_TIMER_APP_VBASE + U300_TIMER_APP_RGPT2);
 387         /* Set this timer to run around forever */
 388         writel(0xFFFFFFFFU, U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2TC);
 389         /* Set continuous mode so it wraps around */
 390         writel(U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS,
 391                U300_TIMER_APP_VBASE + U300_TIMER_APP_SGPT2M);
 392         /* Disable timer interrupts */
 393         writel(U300_TIMER_APP_GPT2IE_IRQ_DISABLE,
 394                 U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2IE);
 395         /* Then enable the GP2 timer to use as a free running us counter */
 396         writel(U300_TIMER_APP_EGPT2_TIMER_ENABLE,
 397                 U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT2);
 398
 399         /* Use general purpose timer 2 as clock source */
 400         if (clocksource_mmio_init(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC,
 401                         "GPT2", rate, 300, 32, clocksource_mmio_readl_up))
 402                 pr_err("timer: failed to initialize U300 clock source\n");
 403
 404         /* Configure and register the clockevent */
 405         clockevents_config_and_register(&clockevent_u300_1mhz, rate,
 406                                         1, 0xffffffff);
 407
 408         /*
 409          * TODO: init and register the rest of the timers too, they can be
 410          * used by hrtimers!
 411          */
 412 }
 413
 414 /*
 415  * Very simple system timer that only register the clock event and
 416  * clock source.
 417  */
 418 struct sys_timer u300_timer = {
 419         .init           = u300_timer_init,
 420 };