arch/arm/mach-u300/core.c

   1 /*
   2  *
   3  * arch/arm/mach-u300/core.c
   4  *
   5  *
   6  * Copyright (C) 2007-2010 ST-Ericsson SA
   7  * License terms: GNU General Public License (GPL) version 2
   8  * Core platform support, IRQ handling and device definitions.
   9  * Author: Linus Walleij <linus.walleij@stericsson.com>
  10  */
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/spinlock.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/bitops.h>
  16 #include <linux/device.h>
  17 #include <linux/mm.h>
  18 #include <linux/termios.h>
  19 #include <linux/dmaengine.h>
  20 #include <linux/amba/bus.h>
  21 #include <linux/amba/serial.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/gpio.h>
  24 #include <linux/clk.h>
  25 #include <linux/err.h>
  26 #include <linux/mtd/nand.h>
  27 #include <linux/mtd/fsmc.h>
  28 #include <linux/pinctrl/machine.h>
  29 #include <linux/pinctrl/pinmux.h>
  30
  31 #include <asm/types.h>
  32 #include <asm/setup.h>
  33 #include <asm/memory.h>
  34 #include <asm/hardware/vic.h>
  35 #include <asm/mach/map.h>
  36 #include <asm/mach/irq.h>
  37
  38 #include <mach/coh901318.h>
  39 #include <mach/hardware.h>
  40 #include <mach/syscon.h>
  41 #include <mach/dma_channels.h>
  42
  43 #include "clock.h"
  44 #include "mmc.h"
  45 #include "spi.h"
  46 #include "i2c.h"
  47
  48 /*
  49  * Static I/O mappings that are needed for booting the U300 platforms. The
  50  * only things we need are the areas where we find the timer, syscon and
  51  * intcon, since the remaining device drivers will map their own memory
  52  * physical to virtual as the need arise.
  53  */
  54 static struct map_desc u300_io_desc[] __initdata = {
  55         {
  56                 .virtual        = U300_SLOW_PER_VIRT_BASE,
  57                 .pfn            = __phys_to_pfn(U300_SLOW_PER_PHYS_BASE),
  58                 .length         = SZ_64K,
  59                 .type           = MT_DEVICE,
  60         },
  61         {
  62                 .virtual        = U300_AHB_PER_VIRT_BASE,
  63                 .pfn            = __phys_to_pfn(U300_AHB_PER_PHYS_BASE),
  64                 .length         = SZ_32K,
  65                 .type           = MT_DEVICE,
  66         },
  67         {
  68                 .virtual        = U300_FAST_PER_VIRT_BASE,
  69                 .pfn            = __phys_to_pfn(U300_FAST_PER_PHYS_BASE),
  70                 .length         = SZ_32K,
  71                 .type           = MT_DEVICE,
  72         },
  73         {
  74                 .virtual        = 0xffff2000, /* TCM memory */
  75                 .pfn            = __phys_to_pfn(0xffff2000),
  76                 .length         = SZ_16K,
  77                 .type           = MT_DEVICE,
  78         },
  79
  80         /*
  81          * This overlaps with the IRQ vectors etc at 0xffff0000, so these
  82          * may have to be moved to 0x00000000 in order to use the ROM.
  83          */
  84         /*
  85         {
  86                 .virtual        = U300_BOOTROM_VIRT_BASE,
  87                 .pfn            = __phys_to_pfn(U300_BOOTROM_PHYS_BASE),
  88                 .length         = SZ_64K,
  89                 .type           = MT_ROM,
  90         },
  91         */
  92 };
  93
  94 void __init u300_map_io(void)
  95 {
  96         iotable_init(u300_io_desc, ARRAY_SIZE(u300_io_desc));
  97 }
  98
  99 /*
 100  * Declaration of devices found on the U300 board and
 101  * their respective memory locations.
 102  */
 103
 104 static struct amba_pl011_data uart0_plat_data = {
 105 #ifdef CONFIG_COH901318
 106         .dma_filter = coh901318_filter_id,
 107         .dma_rx_param = (void *) U300_DMA_UART0_RX,
 108         .dma_tx_param = (void *) U300_DMA_UART0_TX,
 109 #endif
 110 };
 111
 112 static struct amba_device uart0_device = {
 113         .dev = {
 114                 .coherent_dma_mask = ~0,
 115                 .init_name = "uart0", /* Slow device at 0x3000 offset */
 116                 .platform_data = &uart0_plat_data,
 117         },
 118         .res = {
 119                 .start = U300_UART0_BASE,
 120                 .end   = U300_UART0_BASE + SZ_4K - 1,
 121                 .flags = IORESOURCE_MEM,
 122         },
 123         .irq = { IRQ_U300_UART0, NO_IRQ },
 124 };
 125
 126 /* The U335 have an additional UART1 on the APP CPU */
 127 #ifdef CONFIG_MACH_U300_BS335
 128 static struct amba_pl011_data uart1_plat_data = {
 129 #ifdef CONFIG_COH901318
 130         .dma_filter = coh901318_filter_id,
 131         .dma_rx_param = (void *) U300_DMA_UART1_RX,
 132         .dma_tx_param = (void *) U300_DMA_UART1_TX,
 133 #endif
 134 };
 135
 136 static struct amba_device uart1_device = {
 137         .dev = {
 138                 .coherent_dma_mask = ~0,
 139                 .init_name = "uart1", /* Fast device at 0x7000 offset */
 140                 .platform_data = &uart1_plat_data,
 141         },
 142         .res = {
 143                 .start = U300_UART1_BASE,
 144                 .end   = U300_UART1_BASE + SZ_4K - 1,
 145                 .flags = IORESOURCE_MEM,
 146         },
 147         .irq = { IRQ_U300_UART1, NO_IRQ },
 148 };
 149 #endif
 150
 151 static struct amba_device pl172_device = {
 152         .dev = {
 153                 .init_name = "pl172", /* AHB device at 0x4000 offset */
 154                 .platform_data = NULL,
 155         },
 156         .res = {
 157                 .start = U300_EMIF_CFG_BASE,
 158                 .end   = U300_EMIF_CFG_BASE + SZ_4K - 1,
 159                 .flags = IORESOURCE_MEM,
 160         },
 161 };
 162
 163
 164 /*
 165  * Everything within this next ifdef deals with external devices connected to
 166  * the APP SPI bus.
 167  */
 168 static struct amba_device pl022_device = {
 169         .dev = {
 170                 .coherent_dma_mask = ~0,
 171                 .init_name = "pl022", /* Fast device at 0x6000 offset */
 172         },
 173         .res = {
 174                 .start = U300_SPI_BASE,
 175                 .end   = U300_SPI_BASE + SZ_4K - 1,
 176                 .flags = IORESOURCE_MEM,
 177         },
 178         .irq = {IRQ_U300_SPI, NO_IRQ },
 179         /*
 180          * This device has a DMA channel but the Linux driver does not use
 181          * it currently.
 182          */
 183 };
 184
 185 static struct amba_device mmcsd_device = {
 186         .dev = {
 187                 .init_name = "mmci", /* Fast device at 0x1000 offset */
 188                 .platform_data = NULL, /* Added later */
 189         },
 190         .res = {
 191                 .start = U300_MMCSD_BASE,
 192                 .end   = U300_MMCSD_BASE + SZ_4K - 1,
 193                 .flags = IORESOURCE_MEM,
 194         },
 195         .irq = {IRQ_U300_MMCSD_MCIINTR0, IRQ_U300_MMCSD_MCIINTR1 },
 196         /*
 197          * This device has a DMA channel but the Linux driver does not use
 198          * it currently.
 199          */
 200 };
 201
 202 /*
 203  * The order of device declaration may be important, since some devices
 204  * have dependencies on other devices being initialized first.
 205  */
 206 static struct amba_device *amba_devs[] __initdata = {
 207         &uart0_device,
 208 #ifdef CONFIG_MACH_U300_BS335
 209         &uart1_device,
 210 #endif
 211         &pl022_device,
 212         &pl172_device,
 213         &mmcsd_device,
 214 };
 215
 216 /* Here follows a list of all hw resources that the platform devices
 217  * allocate. Note, clock dependencies are not included
 218  */
 219
 220 static struct resource gpio_resources[] = {
 221         {
 222                 .start = U300_GPIO_BASE,
 223                 .end   = (U300_GPIO_BASE + SZ_4K - 1),
 224                 .flags = IORESOURCE_MEM,
 225         },
 226         {
 227                 .name  = "gpio0",
 228                 .start = IRQ_U300_GPIO_PORT0,
 229                 .end   = IRQ_U300_GPIO_PORT0,
 230                 .flags = IORESOURCE_IRQ,
 231         },
 232         {
 233                 .name  = "gpio1",
 234                 .start = IRQ_U300_GPIO_PORT1,
 235                 .end   = IRQ_U300_GPIO_PORT1,
 236                 .flags = IORESOURCE_IRQ,
 237         },
 238         {
 239                 .name  = "gpio2",
 240                 .start = IRQ_U300_GPIO_PORT2,
 241                 .end   = IRQ_U300_GPIO_PORT2,
 242                 .flags = IORESOURCE_IRQ,
 243         },
 244 #ifdef U300_COH901571_3
 245         {
 246                 .name  = "gpio3",
 247                 .start = IRQ_U300_GPIO_PORT3,
 248                 .end   = IRQ_U300_GPIO_PORT3,
 249                 .flags = IORESOURCE_IRQ,
 250         },
 251         {
 252                 .name  = "gpio4",
 253                 .start = IRQ_U300_GPIO_PORT4,
 254                 .end   = IRQ_U300_GPIO_PORT4,
 255                 .flags = IORESOURCE_IRQ,
 256         },
 257 #ifdef CONFIG_MACH_U300_BS335
 258         {
 259                 .name  = "gpio5",
 260                 .start = IRQ_U300_GPIO_PORT5,
 261                 .end   = IRQ_U300_GPIO_PORT5,
 262                 .flags = IORESOURCE_IRQ,
 263         },
 264         {
 265                 .name  = "gpio6",
 266                 .start = IRQ_U300_GPIO_PORT6,
 267                 .end   = IRQ_U300_GPIO_PORT6,
 268                 .flags = IORESOURCE_IRQ,
 269         },
 270 #endif /* CONFIG_MACH_U300_BS335 */
 271 #endif /* U300_COH901571_3 */
 272 };
 273
 274 static struct resource keypad_resources[] = {
 275         {
 276                 .start = U300_KEYPAD_BASE,
 277                 .end   = U300_KEYPAD_BASE + SZ_4K - 1,
 278                 .flags = IORESOURCE_MEM,
 279         },
 280         {
 281                 .name  = "coh901461-press",
 282                 .start = IRQ_U300_KEYPAD_KEYBF,
 283                 .end   = IRQ_U300_KEYPAD_KEYBF,
 284                 .flags = IORESOURCE_IRQ,
 285         },
 286         {
 287                 .name  = "coh901461-release",
 288                 .start = IRQ_U300_KEYPAD_KEYBR,
 289                 .end   = IRQ_U300_KEYPAD_KEYBR,
 290                 .flags = IORESOURCE_IRQ,
 291         },
 292 };
 293
 294 static struct resource rtc_resources[] = {
 295         {
 296                 .start = U300_RTC_BASE,
 297                 .end   = U300_RTC_BASE + SZ_4K - 1,
 298                 .flags = IORESOURCE_MEM,
 299         },
 300         {
 301                 .start = IRQ_U300_RTC,
 302                 .end   = IRQ_U300_RTC,
 303                 .flags = IORESOURCE_IRQ,
 304         },
 305 };
 306
 307 /*
 308  * Fsmc does have IRQs: #43 and #44 (NFIF and NFIF2)
 309  * but these are not yet used by the driver.
 310  */
 311 static struct resource fsmc_resources[] = {
 312         {
 313                 .name  = "nand_data",
 314                 .start = U300_NAND_CS0_PHYS_BASE,
 315                 .end   = U300_NAND_CS0_PHYS_BASE + SZ_16K - 1,
 316                 .flags = IORESOURCE_MEM,
 317         },
 318         {
 319                 .name  = "fsmc_regs",
 320                 .start = U300_NAND_IF_PHYS_BASE,
 321                 .end   = U300_NAND_IF_PHYS_BASE + SZ_4K - 1,
 322                 .flags = IORESOURCE_MEM,
 323         },
 324 };
 325
 326 static struct resource i2c0_resources[] = {
 327         {
 328                 .start = U300_I2C0_BASE,
 329                 .end   = U300_I2C0_BASE + SZ_4K - 1,
 330                 .flags = IORESOURCE_MEM,
 331         },
 332         {
 333                 .start = IRQ_U300_I2C0,
 334                 .end   = IRQ_U300_I2C0,
 335                 .flags = IORESOURCE_IRQ,
 336         },
 337 };
 338
 339 static struct resource i2c1_resources[] = {
 340         {
 341                 .start = U300_I2C1_BASE,
 342                 .end   = U300_I2C1_BASE + SZ_4K - 1,
 343                 .flags = IORESOURCE_MEM,
 344         },
 345         {
 346                 .start = IRQ_U300_I2C1,
 347                 .end   = IRQ_U300_I2C1,
 348                 .flags = IORESOURCE_IRQ,
 349         },
 350
 351 };
 352
 353 static struct resource wdog_resources[] = {
 354         {
 355                 .start = U300_WDOG_BASE,
 356                 .end   = U300_WDOG_BASE + SZ_4K - 1,
 357                 .flags = IORESOURCE_MEM,
 358         },
 359         {
 360                 .start = IRQ_U300_WDOG,
 361                 .end   = IRQ_U300_WDOG,
 362                 .flags = IORESOURCE_IRQ,
 363         }
 364 };
 365
 366 /* TODO: These should be protected by suitable #ifdef's */
 367 static struct resource ave_resources[] = {
 368         {
 369                 .name  = "AVE3e I/O Area",
 370                 .start = U300_VIDEOENC_BASE,
 371                 .end   = U300_VIDEOENC_BASE + SZ_512K - 1,
 372                 .flags = IORESOURCE_MEM,
 373         },
 374         {
 375                 .name  = "AVE3e IRQ0",
 376                 .start = IRQ_U300_VIDEO_ENC_0,
 377                 .end   = IRQ_U300_VIDEO_ENC_0,
 378                 .flags = IORESOURCE_IRQ,
 379         },
 380         {
 381                 .name  = "AVE3e IRQ1",
 382                 .start = IRQ_U300_VIDEO_ENC_1,
 383                 .end   = IRQ_U300_VIDEO_ENC_1,
 384                 .flags = IORESOURCE_IRQ,
 385         },
 386         {
 387                 .name  = "AVE3e Physmem Area",
 388                 .start = 0, /* 0 will be remapped to reserved memory */
 389                 .end   = SZ_1M - 1,
 390                 .flags = IORESOURCE_MEM,
 391         },
 392         /*
 393          * The AVE3e requires two regions of 256MB that it considers
 394          * "invisible". The hardware will not be able to access these
 395          * addresses, so they should never point to system RAM.
 396          */
 397         {
 398                 .name  = "AVE3e Reserved 0",
 399                 .start = 0xd0000000,
 400                 .end   = 0xd0000000 + SZ_256M - 1,
 401                 .flags = IORESOURCE_MEM,
 402         },
 403         {
 404                 .name  = "AVE3e Reserved 1",
 405                 .start = 0xe0000000,
 406                 .end   = 0xe0000000 + SZ_256M - 1,
 407                 .flags = IORESOURCE_MEM,
 408         },
 409 };
 410
 411 static struct resource dma_resource[] = {
 412         {
 413                 .start = U300_DMAC_BASE,
 414                 .end = U300_DMAC_BASE + PAGE_SIZE - 1,
 415                 .flags =  IORESOURCE_MEM,
 416         },
 417         {
 418                 .start = IRQ_U300_DMA,
 419                 .end = IRQ_U300_DMA,
 420                 .flags =  IORESOURCE_IRQ,
 421         }
 422 };
 423
 424 #ifdef CONFIG_MACH_U300_BS335
 425 /* points out all dma slave channels.
 426  * Syntax is [A1, B1, A2, B2, .... ,-1,-1]
 427  * Select all channels from A to B, end of list is marked with -1,-1
 428  */
 429 static int dma_slave_channels[] = {
 430         U300_DMA_MSL_TX_0, U300_DMA_SPI_RX,
 431         U300_DMA_UART1_TX, U300_DMA_UART1_RX, -1, -1};
 432
 433 /* points out all dma memcpy channels. */
 434 static int dma_memcpy_channels[] = {
 435         U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_8, -1, -1};
 436
 437 #else /* CONFIG_MACH_U300_BS335 */
 438
 439 static int dma_slave_channels[] = {U300_DMA_MSL_TX_0, U300_DMA_SPI_RX, -1, -1};
 440 static int dma_memcpy_channels[] = {
 441         U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_10, -1, -1};
 442
 443 #endif
 444
 445 /** register dma for memory access
 446  *
 447  * active  1 means dma intends to access memory
 448  *         0 means dma wont access memory
 449  */
 450 static void coh901318_access_memory_state(struct device *dev, bool active)
 451 {
 452 }
 453
 454 #define flags_memcpy_config (COH901318_CX_CFG_CH_DISABLE | \
 455                         COH901318_CX_CFG_RM_MEMORY_TO_MEMORY | \
 456                         COH901318_CX_CFG_LCR_DISABLE | \
 457                         COH901318_CX_CFG_TC_IRQ_ENABLE | \
 458                         COH901318_CX_CFG_BE_IRQ_ENABLE)
 459 #define flags_memcpy_lli_chained (COH901318_CX_CTRL_TC_ENABLE | \
 460                         COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
 461                         COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
 462                         COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
 463                         COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
 464                         COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
 465                         COH901318_CX_CTRL_MASTER_MODE_M1RW | \
 466                         COH901318_CX_CTRL_TCP_DISABLE | \
 467                         COH901318_CX_CTRL_TC_IRQ_DISABLE | \
 468                         COH901318_CX_CTRL_HSP_DISABLE | \
 469                         COH901318_CX_CTRL_HSS_DISABLE | \
 470                         COH901318_CX_CTRL_DDMA_LEGACY | \
 471                         COH901318_CX_CTRL_PRDD_SOURCE)
 472 #define flags_memcpy_lli (COH901318_CX_CTRL_TC_ENABLE | \
 473                         COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
 474                         COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
 475                         COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
 476                         COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
 477                         COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
 478                         COH901318_CX_CTRL_MASTER_MODE_M1RW | \
 479                         COH901318_CX_CTRL_TCP_DISABLE | \
 480                         COH901318_CX_CTRL_TC_IRQ_DISABLE | \
 481                         COH901318_CX_CTRL_HSP_DISABLE | \
 482                         COH901318_CX_CTRL_HSS_DISABLE | \
 483                         COH901318_CX_CTRL_DDMA_LEGACY | \
 484                         COH901318_CX_CTRL_PRDD_SOURCE)
 485 #define flags_memcpy_lli_last (COH901318_CX_CTRL_TC_ENABLE | \
 486                         COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
 487                         COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
 488                         COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
 489                         COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
 490                         COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
 491                         COH901318_CX_CTRL_MASTER_MODE_M1RW | \
 492                         COH901318_CX_CTRL_TCP_DISABLE | \
 493                         COH901318_CX_CTRL_TC_IRQ_ENABLE | \
 494                         COH901318_CX_CTRL_HSP_DISABLE | \
 495                         COH901318_CX_CTRL_HSS_DISABLE | \
 496                         COH901318_CX_CTRL_DDMA_LEGACY | \
 497                         COH901318_CX_CTRL_PRDD_SOURCE)
 498
 499 const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
 500         {
 501                 .number = U300_DMA_MSL_TX_0,
 502                 .name = "MSL TX 0",
 503                 .priority_high = 0,
 504                 .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x20,
 505         },
 506         {
 507                 .number = U300_DMA_MSL_TX_1,
 508                 .name = "MSL TX 1",
 509                 .priority_high = 0,
 510                 .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x20,
 511                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 512                                 COH901318_CX_CFG_LCR_DISABLE |
 513                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 514                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 515                 .param.ctrl_lli_chained = 0 |
 516                                 COH901318_CX_CTRL_TC_ENABLE |
 517                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 518                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 519                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 520                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 521                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 522                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 523                                 COH901318_CX_CTRL_TCP_DISABLE |
 524                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 525                                 COH901318_CX_CTRL_HSP_ENABLE |
 526                                 COH901318_CX_CTRL_HSS_DISABLE |
 527                                 COH901318_CX_CTRL_DDMA_LEGACY |
 528                                 COH901318_CX_CTRL_PRDD_SOURCE,
 529                 .param.ctrl_lli = 0 |
 530                                 COH901318_CX_CTRL_TC_ENABLE |
 531                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 532                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 533                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 534                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 535                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 536                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 537                                 COH901318_CX_CTRL_TCP_ENABLE |
 538                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 539                                 COH901318_CX_CTRL_HSP_ENABLE |
 540                                 COH901318_CX_CTRL_HSS_DISABLE |
 541                                 COH901318_CX_CTRL_DDMA_LEGACY |
 542                                 COH901318_CX_CTRL_PRDD_SOURCE,
 543                 .param.ctrl_lli_last = 0 |
 544                                 COH901318_CX_CTRL_TC_ENABLE |
 545                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 546                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 547                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 548                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 549                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 550                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 551                                 COH901318_CX_CTRL_TCP_ENABLE |
 552                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 553                                 COH901318_CX_CTRL_HSP_ENABLE |
 554                                 COH901318_CX_CTRL_HSS_DISABLE |
 555                                 COH901318_CX_CTRL_DDMA_LEGACY |
 556                                 COH901318_CX_CTRL_PRDD_SOURCE,
 557         },
 558         {
 559                 .number = U300_DMA_MSL_TX_2,
 560                 .name = "MSL TX 2",
 561                 .priority_high = 0,
 562                 .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x20,
 563                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 564                                 COH901318_CX_CFG_LCR_DISABLE |
 565                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 566                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 567                 .param.ctrl_lli_chained = 0 |
 568                                 COH901318_CX_CTRL_TC_ENABLE |
 569                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 570                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 571                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 572                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 573                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 574                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 575                                 COH901318_CX_CTRL_TCP_DISABLE |
 576                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 577                                 COH901318_CX_CTRL_HSP_ENABLE |
 578                                 COH901318_CX_CTRL_HSS_DISABLE |
 579                                 COH901318_CX_CTRL_DDMA_LEGACY |
 580                                 COH901318_CX_CTRL_PRDD_SOURCE,
 581                 .param.ctrl_lli = 0 |
 582                                 COH901318_CX_CTRL_TC_ENABLE |
 583                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 584                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 585                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 586                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 587                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 588                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 589                                 COH901318_CX_CTRL_TCP_ENABLE |
 590                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 591                                 COH901318_CX_CTRL_HSP_ENABLE |
 592                                 COH901318_CX_CTRL_HSS_DISABLE |
 593                                 COH901318_CX_CTRL_DDMA_LEGACY |
 594                                 COH901318_CX_CTRL_PRDD_SOURCE,
 595                 .param.ctrl_lli_last = 0 |
 596                                 COH901318_CX_CTRL_TC_ENABLE |
 597                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 598                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 599                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 600                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 601                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 602                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 603                                 COH901318_CX_CTRL_TCP_ENABLE |
 604                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 605                                 COH901318_CX_CTRL_HSP_ENABLE |
 606                                 COH901318_CX_CTRL_HSS_DISABLE |
 607                                 COH901318_CX_CTRL_DDMA_LEGACY |
 608                                 COH901318_CX_CTRL_PRDD_SOURCE,
 609                 .desc_nbr_max = 10,
 610         },
 611         {
 612                 .number = U300_DMA_MSL_TX_3,
 613                 .name = "MSL TX 3",
 614                 .priority_high = 0,
 615                 .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x20,
 616                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 617                                 COH901318_CX_CFG_LCR_DISABLE |
 618                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 619                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 620                 .param.ctrl_lli_chained = 0 |
 621                                 COH901318_CX_CTRL_TC_ENABLE |
 622                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 623                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 624                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 625                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 626                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 627                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 628                                 COH901318_CX_CTRL_TCP_DISABLE |
 629                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 630                                 COH901318_CX_CTRL_HSP_ENABLE |
 631                                 COH901318_CX_CTRL_HSS_DISABLE |
 632                                 COH901318_CX_CTRL_DDMA_LEGACY |
 633                                 COH901318_CX_CTRL_PRDD_SOURCE,
 634                 .param.ctrl_lli = 0 |
 635                                 COH901318_CX_CTRL_TC_ENABLE |
 636                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 637                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 638                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 639                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 640                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 641                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 642                                 COH901318_CX_CTRL_TCP_ENABLE |
 643                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 644                                 COH901318_CX_CTRL_HSP_ENABLE |
 645                                 COH901318_CX_CTRL_HSS_DISABLE |
 646                                 COH901318_CX_CTRL_DDMA_LEGACY |
 647                                 COH901318_CX_CTRL_PRDD_SOURCE,
 648                 .param.ctrl_lli_last = 0 |
 649                                 COH901318_CX_CTRL_TC_ENABLE |
 650                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 651                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 652                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 653                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 654                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 655                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 656                                 COH901318_CX_CTRL_TCP_ENABLE |
 657                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 658                                 COH901318_CX_CTRL_HSP_ENABLE |
 659                                 COH901318_CX_CTRL_HSS_DISABLE |
 660                                 COH901318_CX_CTRL_DDMA_LEGACY |
 661                                 COH901318_CX_CTRL_PRDD_SOURCE,
 662         },
 663         {
 664                 .number = U300_DMA_MSL_TX_4,
 665                 .name = "MSL TX 4",
 666                 .priority_high = 0,
 667                 .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x20,
 668                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 669                                 COH901318_CX_CFG_LCR_DISABLE |
 670                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 671                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 672                 .param.ctrl_lli_chained = 0 |
 673                                 COH901318_CX_CTRL_TC_ENABLE |
 674                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 675                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 676                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 677                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 678                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 679                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 680                                 COH901318_CX_CTRL_TCP_DISABLE |
 681                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 682                                 COH901318_CX_CTRL_HSP_ENABLE |
 683                                 COH901318_CX_CTRL_HSS_DISABLE |
 684                                 COH901318_CX_CTRL_DDMA_LEGACY |
 685                                 COH901318_CX_CTRL_PRDD_SOURCE,
 686                 .param.ctrl_lli = 0 |
 687                                 COH901318_CX_CTRL_TC_ENABLE |
 688                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 689                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 690                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 691                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 692                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 693                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 694                                 COH901318_CX_CTRL_TCP_ENABLE |
 695                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 696                                 COH901318_CX_CTRL_HSP_ENABLE |
 697                                 COH901318_CX_CTRL_HSS_DISABLE |
 698                                 COH901318_CX_CTRL_DDMA_LEGACY |
 699                                 COH901318_CX_CTRL_PRDD_SOURCE,
 700                 .param.ctrl_lli_last = 0 |
 701                                 COH901318_CX_CTRL_TC_ENABLE |
 702                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 703                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 704                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 705                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 706                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 707                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 708                                 COH901318_CX_CTRL_TCP_ENABLE |
 709                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 710                                 COH901318_CX_CTRL_HSP_ENABLE |
 711                                 COH901318_CX_CTRL_HSS_DISABLE |
 712                                 COH901318_CX_CTRL_DDMA_LEGACY |
 713                                 COH901318_CX_CTRL_PRDD_SOURCE,
 714         },
 715         {
 716                 .number = U300_DMA_MSL_TX_5,
 717                 .name = "MSL TX 5",
 718                 .priority_high = 0,
 719                 .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x20,
 720         },
 721         {
 722                 .number = U300_DMA_MSL_TX_6,
 723                 .name = "MSL TX 6",
 724                 .priority_high = 0,
 725                 .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x20,
 726         },
 727         {
 728                 .number = U300_DMA_MSL_RX_0,
 729                 .name = "MSL RX 0",
 730                 .priority_high = 0,
 731                 .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x220,
 732         },
 733         {
 734                 .number = U300_DMA_MSL_RX_1,
 735                 .name = "MSL RX 1",
 736                 .priority_high = 0,
 737                 .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x220,
 738                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 739                                 COH901318_CX_CFG_LCR_DISABLE |
 740                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 741                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 742                 .param.ctrl_lli_chained = 0 |
 743                                 COH901318_CX_CTRL_TC_ENABLE |
 744                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 745                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 746                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 747                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 748                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 749                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 750                                 COH901318_CX_CTRL_TCP_DISABLE |
 751                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 752                                 COH901318_CX_CTRL_HSP_ENABLE |
 753                                 COH901318_CX_CTRL_HSS_DISABLE |
 754                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 755                                 COH901318_CX_CTRL_PRDD_DEST,
 756                 .param.ctrl_lli = 0,
 757                 .param.ctrl_lli_last = 0 |
 758                                 COH901318_CX_CTRL_TC_ENABLE |
 759                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 760                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 761                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 762                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 763                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 764                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 765                                 COH901318_CX_CTRL_TCP_DISABLE |
 766                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 767                                 COH901318_CX_CTRL_HSP_ENABLE |
 768                                 COH901318_CX_CTRL_HSS_DISABLE |
 769                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 770                                 COH901318_CX_CTRL_PRDD_DEST,
 771         },
 772         {
 773                 .number = U300_DMA_MSL_RX_2,
 774                 .name = "MSL RX 2",
 775                 .priority_high = 0,
 776                 .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x220,
 777                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 778                                 COH901318_CX_CFG_LCR_DISABLE |
 779                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 780                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 781                 .param.ctrl_lli_chained = 0 |
 782                                 COH901318_CX_CTRL_TC_ENABLE |
 783                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 784                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 785                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 786                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 787                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 788                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 789                                 COH901318_CX_CTRL_TCP_DISABLE |
 790                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 791                                 COH901318_CX_CTRL_HSP_ENABLE |
 792                                 COH901318_CX_CTRL_HSS_DISABLE |
 793                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 794                                 COH901318_CX_CTRL_PRDD_DEST,
 795                 .param.ctrl_lli = 0 |
 796                                 COH901318_CX_CTRL_TC_ENABLE |
 797                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 798                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 799                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 800                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 801                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 802                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 803                                 COH901318_CX_CTRL_TCP_DISABLE |
 804                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 805                                 COH901318_CX_CTRL_HSP_ENABLE |
 806                                 COH901318_CX_CTRL_HSS_DISABLE |
 807                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 808                                 COH901318_CX_CTRL_PRDD_DEST,
 809                 .param.ctrl_lli_last = 0 |
 810                                 COH901318_CX_CTRL_TC_ENABLE |
 811                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 812                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 813                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 814                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 815                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 816                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 817                                 COH901318_CX_CTRL_TCP_DISABLE |
 818                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 819                                 COH901318_CX_CTRL_HSP_ENABLE |
 820                                 COH901318_CX_CTRL_HSS_DISABLE |
 821                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 822                                 COH901318_CX_CTRL_PRDD_DEST,
 823         },
 824         {
 825                 .number = U300_DMA_MSL_RX_3,
 826                 .name = "MSL RX 3",
 827                 .priority_high = 0,
 828                 .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x220,
 829                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 830                                 COH901318_CX_CFG_LCR_DISABLE |
 831                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 832                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 833                 .param.ctrl_lli_chained = 0 |
 834                                 COH901318_CX_CTRL_TC_ENABLE |
 835                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 836                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 837                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 838                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 839                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 840                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 841                                 COH901318_CX_CTRL_TCP_DISABLE |
 842                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 843                                 COH901318_CX_CTRL_HSP_ENABLE |
 844                                 COH901318_CX_CTRL_HSS_DISABLE |
 845                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 846                                 COH901318_CX_CTRL_PRDD_DEST,
 847                 .param.ctrl_lli = 0 |
 848                                 COH901318_CX_CTRL_TC_ENABLE |
 849                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 850                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 851                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 852                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 853                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 854                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 855                                 COH901318_CX_CTRL_TCP_DISABLE |
 856                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 857                                 COH901318_CX_CTRL_HSP_ENABLE |
 858                                 COH901318_CX_CTRL_HSS_DISABLE |
 859                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 860                                 COH901318_CX_CTRL_PRDD_DEST,
 861                 .param.ctrl_lli_last = 0 |
 862                                 COH901318_CX_CTRL_TC_ENABLE |
 863                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 864                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 865                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 866                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 867                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 868                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 869                                 COH901318_CX_CTRL_TCP_DISABLE |
 870                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 871                                 COH901318_CX_CTRL_HSP_ENABLE |
 872                                 COH901318_CX_CTRL_HSS_DISABLE |
 873                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 874                                 COH901318_CX_CTRL_PRDD_DEST,
 875         },
 876         {
 877                 .number = U300_DMA_MSL_RX_4,
 878                 .name = "MSL RX 4",
 879                 .priority_high = 0,
 880                 .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x220,
 881                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 882                                 COH901318_CX_CFG_LCR_DISABLE |
 883                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 884                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 885                 .param.ctrl_lli_chained = 0 |
 886                                 COH901318_CX_CTRL_TC_ENABLE |
 887                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 888                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 889                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 890                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 891                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 892                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 893                                 COH901318_CX_CTRL_TCP_DISABLE |
 894                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 895                                 COH901318_CX_CTRL_HSP_ENABLE |
 896                                 COH901318_CX_CTRL_HSS_DISABLE |
 897                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 898                                 COH901318_CX_CTRL_PRDD_DEST,
 899                 .param.ctrl_lli = 0 |
 900                                 COH901318_CX_CTRL_TC_ENABLE |
 901                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 902                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 903                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 904                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 905                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 906                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 907                                 COH901318_CX_CTRL_TCP_DISABLE |
 908                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 909                                 COH901318_CX_CTRL_HSP_ENABLE |
 910                                 COH901318_CX_CTRL_HSS_DISABLE |
 911                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 912                                 COH901318_CX_CTRL_PRDD_DEST,
 913                 .param.ctrl_lli_last = 0 |
 914                                 COH901318_CX_CTRL_TC_ENABLE |
 915                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 916                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 917                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 918                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 919                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 920                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 921                                 COH901318_CX_CTRL_TCP_DISABLE |
 922                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 923                                 COH901318_CX_CTRL_HSP_ENABLE |
 924                                 COH901318_CX_CTRL_HSS_DISABLE |
 925                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 926                                 COH901318_CX_CTRL_PRDD_DEST,
 927         },
 928         {
 929                 .number = U300_DMA_MSL_RX_5,
 930                 .name = "MSL RX 5",
 931                 .priority_high = 0,
 932                 .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x220,
 933                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 934                                 COH901318_CX_CFG_LCR_DISABLE |
 935                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 936                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 937                 .param.ctrl_lli_chained = 0 |
 938                                 COH901318_CX_CTRL_TC_ENABLE |
 939                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 940                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 941                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 942                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 943                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 944                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 945                                 COH901318_CX_CTRL_TCP_DISABLE |
 946                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 947                                 COH901318_CX_CTRL_HSP_ENABLE |
 948                                 COH901318_CX_CTRL_HSS_DISABLE |
 949                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 950                                 COH901318_CX_CTRL_PRDD_DEST,
 951                 .param.ctrl_lli = 0 |
 952                                 COH901318_CX_CTRL_TC_ENABLE |
 953                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 954                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 955                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 956                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 957                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 958                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 959                                 COH901318_CX_CTRL_TCP_DISABLE |
 960                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 961                                 COH901318_CX_CTRL_HSP_ENABLE |
 962                                 COH901318_CX_CTRL_HSS_DISABLE |
 963                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 964                                 COH901318_CX_CTRL_PRDD_DEST,
 965                 .param.ctrl_lli_last = 0 |
 966                                 COH901318_CX_CTRL_TC_ENABLE |
 967                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 968                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 969                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 970                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 971                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 972                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 973                                 COH901318_CX_CTRL_TCP_DISABLE |
 974                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 975                                 COH901318_CX_CTRL_HSP_ENABLE |
 976                                 COH901318_CX_CTRL_HSS_DISABLE |
 977                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 978                                 COH901318_CX_CTRL_PRDD_DEST,
 979         },
 980         {
 981                 .number = U300_DMA_MSL_RX_6,
 982                 .name = "MSL RX 6",
 983                 .priority_high = 0,
 984                 .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x220,
 985         },
 986         /*
 987          * Don't set up device address, burst count or size of src
 988          * or dst bus for this peripheral - handled by PrimeCell
 989          * DMA extension.
 990          */
 991         {
 992                 .number = U300_DMA_MMCSD_RX_TX,
 993                 .name = "MMCSD RX TX",
 994                 .priority_high = 0,
 995                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 996                                 COH901318_CX_CFG_LCR_DISABLE |
 997                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 998                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 999                 .param.ctrl_lli_chained = 0 |
1000                                 COH901318_CX_CTRL_TC_ENABLE |
1001                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1002                                 COH901318_CX_CTRL_TCP_ENABLE |
1003                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1004                                 COH901318_CX_CTRL_HSP_ENABLE |
1005                                 COH901318_CX_CTRL_HSS_DISABLE |
1006                                 COH901318_CX_CTRL_DDMA_LEGACY,
1007                 .param.ctrl_lli = 0 |
1008                                 COH901318_CX_CTRL_TC_ENABLE |
1009                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1010                                 COH901318_CX_CTRL_TCP_ENABLE |
1011                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1012                                 COH901318_CX_CTRL_HSP_ENABLE |
1013                                 COH901318_CX_CTRL_HSS_DISABLE |
1014                                 COH901318_CX_CTRL_DDMA_LEGACY,
1015                 .param.ctrl_lli_last = 0 |
1016                                 COH901318_CX_CTRL_TC_ENABLE |
1017                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1018                                 COH901318_CX_CTRL_TCP_DISABLE |
1019                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1020                                 COH901318_CX_CTRL_HSP_ENABLE |
1021                                 COH901318_CX_CTRL_HSS_DISABLE |
1022                                 COH901318_CX_CTRL_DDMA_LEGACY,
1023
1024         },
1025         {
1026                 .number = U300_DMA_MSPRO_TX,
1027                 .name = "MSPRO TX",
1028                 .priority_high = 0,
1029         },
1030         {
1031                 .number = U300_DMA_MSPRO_RX,
1032                 .name = "MSPRO RX",
1033                 .priority_high = 0,
1034         },
1035         /*
1036          * Don't set up device address, burst count or size of src
1037          * or dst bus for this peripheral - handled by PrimeCell
1038          * DMA extension.
1039          */
1040         {
1041                 .number = U300_DMA_UART0_TX,
1042                 .name = "UART0 TX",
1043                 .priority_high = 0,
1044                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1045                                 COH901318_CX_CFG_LCR_DISABLE |
1046                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1047                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1048                 .param.ctrl_lli_chained = 0 |
1049                                 COH901318_CX_CTRL_TC_ENABLE |
1050                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1051                                 COH901318_CX_CTRL_TCP_ENABLE |
1052                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1053                                 COH901318_CX_CTRL_HSP_ENABLE |
1054                                 COH901318_CX_CTRL_HSS_DISABLE |
1055                                 COH901318_CX_CTRL_DDMA_LEGACY,
1056                 .param.ctrl_lli = 0 |
1057                                 COH901318_CX_CTRL_TC_ENABLE |
1058                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1059                                 COH901318_CX_CTRL_TCP_ENABLE |
1060                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1061                                 COH901318_CX_CTRL_HSP_ENABLE |
1062                                 COH901318_CX_CTRL_HSS_DISABLE |
1063                                 COH901318_CX_CTRL_DDMA_LEGACY,
1064                 .param.ctrl_lli_last = 0 |
1065                                 COH901318_CX_CTRL_TC_ENABLE |
1066                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1067                                 COH901318_CX_CTRL_TCP_ENABLE |
1068                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1069                                 COH901318_CX_CTRL_HSP_ENABLE |
1070                                 COH901318_CX_CTRL_HSS_DISABLE |
1071                                 COH901318_CX_CTRL_DDMA_LEGACY,
1072         },
1073         {
1074                 .number = U300_DMA_UART0_RX,
1075                 .name = "UART0 RX",
1076                 .priority_high = 0,
1077                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1078                                 COH901318_CX_CFG_LCR_DISABLE |
1079                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1080                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1081                 .param.ctrl_lli_chained = 0 |
1082                                 COH901318_CX_CTRL_TC_ENABLE |
1083                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1084                                 COH901318_CX_CTRL_TCP_ENABLE |
1085                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1086                                 COH901318_CX_CTRL_HSP_ENABLE |
1087                                 COH901318_CX_CTRL_HSS_DISABLE |
1088                                 COH901318_CX_CTRL_DDMA_LEGACY,
1089                 .param.ctrl_lli = 0 |
1090                                 COH901318_CX_CTRL_TC_ENABLE |
1091                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1092                                 COH901318_CX_CTRL_TCP_ENABLE |
1093                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1094                                 COH901318_CX_CTRL_HSP_ENABLE |
1095                                 COH901318_CX_CTRL_HSS_DISABLE |
1096                                 COH901318_CX_CTRL_DDMA_LEGACY,
1097                 .param.ctrl_lli_last = 0 |
1098                                 COH901318_CX_CTRL_TC_ENABLE |
1099                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1100                                 COH901318_CX_CTRL_TCP_ENABLE |
1101                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1102                                 COH901318_CX_CTRL_HSP_ENABLE |
1103                                 COH901318_CX_CTRL_HSS_DISABLE |
1104                                 COH901318_CX_CTRL_DDMA_LEGACY,
1105         },
1106         {
1107                 .number = U300_DMA_APEX_TX,
1108                 .name = "APEX TX",
1109                 .priority_high = 0,
1110         },
1111         {
1112                 .number = U300_DMA_APEX_RX,
1113                 .name = "APEX RX",
1114                 .priority_high = 0,
1115         },
1116         {
1117                 .number = U300_DMA_PCM_I2S0_TX,
1118                 .name = "PCM I2S0 TX",
1119                 .priority_high = 1,
1120                 .dev_addr = U300_PCM_I2S0_BASE + 0x14,
1121                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1122                                 COH901318_CX_CFG_LCR_DISABLE |
1123                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1124                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1125                 .param.ctrl_lli_chained = 0 |
1126                                 COH901318_CX_CTRL_TC_ENABLE |
1127                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1128                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1129                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1130                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1131                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1132                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1133                                 COH901318_CX_CTRL_TCP_DISABLE |
1134                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1135                                 COH901318_CX_CTRL_HSP_ENABLE |
1136                                 COH901318_CX_CTRL_HSS_DISABLE |
1137                                 COH901318_CX_CTRL_DDMA_LEGACY |
1138                                 COH901318_CX_CTRL_PRDD_SOURCE,
1139                 .param.ctrl_lli = 0 |
1140                                 COH901318_CX_CTRL_TC_ENABLE |
1141                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1142                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1143                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1144                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1145                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1146                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1147                                 COH901318_CX_CTRL_TCP_ENABLE |
1148                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1149                                 COH901318_CX_CTRL_HSP_ENABLE |
1150                                 COH901318_CX_CTRL_HSS_DISABLE |
1151                                 COH901318_CX_CTRL_DDMA_LEGACY |
1152                                 COH901318_CX_CTRL_PRDD_SOURCE,
1153                 .param.ctrl_lli_last = 0 |
1154                                 COH901318_CX_CTRL_TC_ENABLE |
1155                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1156                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1157                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1158                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1159                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1160                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1161                                 COH901318_CX_CTRL_TCP_ENABLE |
1162                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1163                                 COH901318_CX_CTRL_HSP_ENABLE |
1164                                 COH901318_CX_CTRL_HSS_DISABLE |
1165                                 COH901318_CX_CTRL_DDMA_LEGACY |
1166                                 COH901318_CX_CTRL_PRDD_SOURCE,
1167         },
1168         {
1169                 .number = U300_DMA_PCM_I2S0_RX,
1170                 .name = "PCM I2S0 RX",
1171                 .priority_high = 1,
1172                 .dev_addr = U300_PCM_I2S0_BASE + 0x10,
1173                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1174                                 COH901318_CX_CFG_LCR_DISABLE |
1175                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1176                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1177                 .param.ctrl_lli_chained = 0 |
1178                                 COH901318_CX_CTRL_TC_ENABLE |
1179                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1180                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1181                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1182                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1183                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1184                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1185                                 COH901318_CX_CTRL_TCP_DISABLE |
1186                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1187                                 COH901318_CX_CTRL_HSP_ENABLE |
1188                                 COH901318_CX_CTRL_HSS_DISABLE |
1189                                 COH901318_CX_CTRL_DDMA_LEGACY |
1190                                 COH901318_CX_CTRL_PRDD_DEST,
1191                 .param.ctrl_lli = 0 |
1192                                 COH901318_CX_CTRL_TC_ENABLE |
1193                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1194                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1195                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1196                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1197                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1198                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1199                                 COH901318_CX_CTRL_TCP_ENABLE |
1200                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1201                                 COH901318_CX_CTRL_HSP_ENABLE |
1202                                 COH901318_CX_CTRL_HSS_DISABLE |
1203                                 COH901318_CX_CTRL_DDMA_LEGACY |
1204                                 COH901318_CX_CTRL_PRDD_DEST,
1205                 .param.ctrl_lli_last = 0 |
1206                                 COH901318_CX_CTRL_TC_ENABLE |
1207                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1208                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1209                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1210                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1211                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1212                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1213                                 COH901318_CX_CTRL_TCP_ENABLE |
1214                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1215                                 COH901318_CX_CTRL_HSP_ENABLE |
1216                                 COH901318_CX_CTRL_HSS_DISABLE |
1217                                 COH901318_CX_CTRL_DDMA_LEGACY |
1218                                 COH901318_CX_CTRL_PRDD_DEST,
1219         },
1220         {
1221                 .number = U300_DMA_PCM_I2S1_TX,
1222                 .name = "PCM I2S1 TX",
1223                 .priority_high = 1,
1224                 .dev_addr =  U300_PCM_I2S1_BASE + 0x14,
1225                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1226                                 COH901318_CX_CFG_LCR_DISABLE |
1227                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1228                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1229                 .param.ctrl_lli_chained = 0 |
1230                                 COH901318_CX_CTRL_TC_ENABLE |
1231                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1232                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1233                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1234                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1235                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1236                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1237                                 COH901318_CX_CTRL_TCP_DISABLE |
1238                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1239                                 COH901318_CX_CTRL_HSP_ENABLE |
1240                                 COH901318_CX_CTRL_HSS_DISABLE |
1241                                 COH901318_CX_CTRL_DDMA_LEGACY |
1242                                 COH901318_CX_CTRL_PRDD_SOURCE,
1243                 .param.ctrl_lli = 0 |
1244                                 COH901318_CX_CTRL_TC_ENABLE |
1245                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1246                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1247                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1248                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1249                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1250                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1251                                 COH901318_CX_CTRL_TCP_ENABLE |
1252                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1253                                 COH901318_CX_CTRL_HSP_ENABLE |
1254                                 COH901318_CX_CTRL_HSS_DISABLE |
1255                                 COH901318_CX_CTRL_DDMA_LEGACY |
1256                                 COH901318_CX_CTRL_PRDD_SOURCE,
1257                 .param.ctrl_lli_last = 0 |
1258                                 COH901318_CX_CTRL_TC_ENABLE |
1259                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1260                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1261                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1262                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1263                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1264                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1265                                 COH901318_CX_CTRL_TCP_ENABLE |
1266                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1267                                 COH901318_CX_CTRL_HSP_ENABLE |
1268                                 COH901318_CX_CTRL_HSS_DISABLE |
1269                                 COH901318_CX_CTRL_DDMA_LEGACY |
1270                                 COH901318_CX_CTRL_PRDD_SOURCE,
1271         },
1272         {
1273                 .number = U300_DMA_PCM_I2S1_RX,
1274                 .name = "PCM I2S1 RX",
1275                 .priority_high = 1,
1276                 .dev_addr = U300_PCM_I2S1_BASE + 0x10,
1277                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1278                                 COH901318_CX_CFG_LCR_DISABLE |
1279                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1280                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1281                 .param.ctrl_lli_chained = 0 |
1282                                 COH901318_CX_CTRL_TC_ENABLE |
1283                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1284                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1285                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1286                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1287                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1288                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1289                                 COH901318_CX_CTRL_TCP_DISABLE |
1290                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1291                                 COH901318_CX_CTRL_HSP_ENABLE |
1292                                 COH901318_CX_CTRL_HSS_DISABLE |
1293                                 COH901318_CX_CTRL_DDMA_LEGACY |
1294                                 COH901318_CX_CTRL_PRDD_DEST,
1295                 .param.ctrl_lli = 0 |
1296                                 COH901318_CX_CTRL_TC_ENABLE |
1297                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1298                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1299                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1300                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1301                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1302                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1303                                 COH901318_CX_CTRL_TCP_ENABLE |
1304                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1305                                 COH901318_CX_CTRL_HSP_ENABLE |
1306                                 COH901318_CX_CTRL_HSS_DISABLE |
1307                                 COH901318_CX_CTRL_DDMA_LEGACY |
1308                                 COH901318_CX_CTRL_PRDD_DEST,
1309                 .param.ctrl_lli_last = 0 |
1310                                 COH901318_CX_CTRL_TC_ENABLE |
1311                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1312                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1313                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1314                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1315                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1316                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1317                                 COH901318_CX_CTRL_TCP_ENABLE |
1318                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1319                                 COH901318_CX_CTRL_HSP_ENABLE |
1320                                 COH901318_CX_CTRL_HSS_DISABLE |
1321                                 COH901318_CX_CTRL_DDMA_LEGACY |
1322                                 COH901318_CX_CTRL_PRDD_DEST,
1323         },
1324         {
1325                 .number = U300_DMA_XGAM_CDI,
1326                 .name = "XGAM CDI",
1327                 .priority_high = 0,
1328         },
1329         {
1330                 .number = U300_DMA_XGAM_PDI,
1331                 .name = "XGAM PDI",
1332                 .priority_high = 0,
1333         },
1334         /*
1335          * Don't set up device address, burst count or size of src
1336          * or dst bus for this peripheral - handled by PrimeCell
1337          * DMA extension.
1338          */
1339         {
1340                 .number = U300_DMA_SPI_TX,
1341                 .name = "SPI TX",
1342                 .priority_high = 0,
1343                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1344                                 COH901318_CX_CFG_LCR_DISABLE |
1345                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1346                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1347                 .param.ctrl_lli_chained = 0 |
1348                                 COH901318_CX_CTRL_TC_ENABLE |
1349                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1350                                 COH901318_CX_CTRL_TCP_DISABLE |
1351                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1352                                 COH901318_CX_CTRL_HSP_ENABLE |
1353                                 COH901318_CX_CTRL_HSS_DISABLE |
1354                                 COH901318_CX_CTRL_DDMA_LEGACY,
1355                 .param.ctrl_lli = 0 |
1356                                 COH901318_CX_CTRL_TC_ENABLE |
1357                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1358                                 COH901318_CX_CTRL_TCP_DISABLE |
1359                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1360                                 COH901318_CX_CTRL_HSP_ENABLE |
1361                                 COH901318_CX_CTRL_HSS_DISABLE |
1362                                 COH901318_CX_CTRL_DDMA_LEGACY,
1363                 .param.ctrl_lli_last = 0 |
1364                                 COH901318_CX_CTRL_TC_ENABLE |
1365                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1366                                 COH901318_CX_CTRL_TCP_DISABLE |
1367                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1368                                 COH901318_CX_CTRL_HSP_ENABLE |
1369                                 COH901318_CX_CTRL_HSS_DISABLE |
1370                                 COH901318_CX_CTRL_DDMA_LEGACY,
1371         },
1372         {
1373                 .number = U300_DMA_SPI_RX,
1374                 .name = "SPI RX",
1375                 .priority_high = 0,
1376                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1377                                 COH901318_CX_CFG_LCR_DISABLE |
1378                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1379                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1380                 .param.ctrl_lli_chained = 0 |
1381                                 COH901318_CX_CTRL_TC_ENABLE |
1382                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1383                                 COH901318_CX_CTRL_TCP_DISABLE |
1384                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1385                                 COH901318_CX_CTRL_HSP_ENABLE |
1386                                 COH901318_CX_CTRL_HSS_DISABLE |
1387                                 COH901318_CX_CTRL_DDMA_LEGACY,
1388                 .param.ctrl_lli = 0 |
1389                                 COH901318_CX_CTRL_TC_ENABLE |
1390                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1391                                 COH901318_CX_CTRL_TCP_DISABLE |
1392                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1393                                 COH901318_CX_CTRL_HSP_ENABLE |
1394                                 COH901318_CX_CTRL_HSS_DISABLE |
1395                                 COH901318_CX_CTRL_DDMA_LEGACY,
1396                 .param.ctrl_lli_last = 0 |
1397                                 COH901318_CX_CTRL_TC_ENABLE |
1398                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1399                                 COH901318_CX_CTRL_TCP_DISABLE |
1400                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1401                                 COH901318_CX_CTRL_HSP_ENABLE |
1402                                 COH901318_CX_CTRL_HSS_DISABLE |
1403                                 COH901318_CX_CTRL_DDMA_LEGACY,
1404
1405         },
1406         {
1407                 .number = U300_DMA_GENERAL_PURPOSE_0,
1408                 .name = "GENERAL 00",
1409                 .priority_high = 0,
1410
1411                 .param.config = flags_memcpy_config,
1412                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1413                 .param.ctrl_lli = flags_memcpy_lli,
1414                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1415         },
1416         {
1417                 .number = U300_DMA_GENERAL_PURPOSE_1,
1418                 .name = "GENERAL 01",
1419                 .priority_high = 0,
1420
1421                 .param.config = flags_memcpy_config,
1422                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1423                 .param.ctrl_lli = flags_memcpy_lli,
1424                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1425         },
1426         {
1427                 .number = U300_DMA_GENERAL_PURPOSE_2,
1428                 .name = "GENERAL 02",
1429                 .priority_high = 0,
1430
1431                 .param.config = flags_memcpy_config,
1432                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1433                 .param.ctrl_lli = flags_memcpy_lli,
1434                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1435         },
1436         {
1437                 .number = U300_DMA_GENERAL_PURPOSE_3,
1438                 .name = "GENERAL 03",
1439                 .priority_high = 0,
1440
1441                 .param.config = flags_memcpy_config,
1442                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1443                 .param.ctrl_lli = flags_memcpy_lli,
1444                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1445         },
1446         {
1447                 .number = U300_DMA_GENERAL_PURPOSE_4,
1448                 .name = "GENERAL 04",
1449                 .priority_high = 0,
1450
1451                 .param.config = flags_memcpy_config,
1452                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1453                 .param.ctrl_lli = flags_memcpy_lli,
1454                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1455         },
1456         {
1457                 .number = U300_DMA_GENERAL_PURPOSE_5,
1458                 .name = "GENERAL 05",
1459                 .priority_high = 0,
1460
1461                 .param.config = flags_memcpy_config,
1462                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1463                 .param.ctrl_lli = flags_memcpy_lli,
1464                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1465         },
1466         {
1467                 .number = U300_DMA_GENERAL_PURPOSE_6,
1468                 .name = "GENERAL 06",
1469                 .priority_high = 0,
1470
1471                 .param.config = flags_memcpy_config,
1472                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1473                 .param.ctrl_lli = flags_memcpy_lli,
1474                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1475         },
1476         {
1477                 .number = U300_DMA_GENERAL_PURPOSE_7,
1478                 .name = "GENERAL 07",
1479                 .priority_high = 0,
1480
1481                 .param.config = flags_memcpy_config,
1482                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1483                 .param.ctrl_lli = flags_memcpy_lli,
1484                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1485         },
1486         {
1487                 .number = U300_DMA_GENERAL_PURPOSE_8,
1488                 .name = "GENERAL 08",
1489                 .priority_high = 0,
1490
1491                 .param.config = flags_memcpy_config,
1492                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1493                 .param.ctrl_lli = flags_memcpy_lli,
1494                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1495         },
1496 #ifdef CONFIG_MACH_U300_BS335
1497         {
1498                 .number = U300_DMA_UART1_TX,
1499                 .name = "UART1 TX",
1500                 .priority_high = 0,
1501         },
1502         {
1503                 .number = U300_DMA_UART1_RX,
1504                 .name = "UART1 RX",
1505                 .priority_high = 0,
1506         }
1507 #else
1508         {
1509                 .number = U300_DMA_GENERAL_PURPOSE_9,
1510                 .name = "GENERAL 09",
1511                 .priority_high = 0,
1512
1513                 .param.config = flags_memcpy_config,
1514                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1515                 .param.ctrl_lli = flags_memcpy_lli,
1516                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1517         },
1518         {
1519                 .number = U300_DMA_GENERAL_PURPOSE_10,
1520                 .name = "GENERAL 10",
1521                 .priority_high = 0,
1522
1523                 .param.config = flags_memcpy_config,
1524                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1525                 .param.ctrl_lli = flags_memcpy_lli,
1526                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1527         }
1528 #endif
1529 };
1530
1531
1532 static struct coh901318_platform coh901318_platform = {
1533         .chans_slave = dma_slave_channels,
1534         .chans_memcpy = dma_memcpy_channels,
1535         .access_memory_state = coh901318_access_memory_state,
1536         .chan_conf = chan_config,
1537         .max_channels = U300_DMA_CHANNELS,
1538 };
1539
1540 static struct resource pinmux_resources[] = {
1541         {
1542                 .start = U300_SYSCON_BASE,
1543                 .end   = U300_SYSCON_BASE + SZ_4K - 1,
1544                 .flags = IORESOURCE_MEM,
1545         },
1546 };
1547
1548 static struct platform_device wdog_device = {
1549         .name = "coh901327_wdog",
1550         .id = -1,
1551         .num_resources = ARRAY_SIZE(wdog_resources),
1552         .resource = wdog_resources,
1553 };
1554
1555 static struct platform_device i2c0_device = {
1556         .name = "stu300",
1557         .id = 0,
1558         .num_resources = ARRAY_SIZE(i2c0_resources),
1559         .resource = i2c0_resources,
1560 };
1561
1562 static struct platform_device i2c1_device = {
1563         .name = "stu300",
1564         .id = 1,
1565         .num_resources = ARRAY_SIZE(i2c1_resources),
1566         .resource = i2c1_resources,
1567 };
1568
1569 static struct platform_device gpio_device = {
1570         .name = "u300-gpio",
1571         .id = -1,
1572         .num_resources = ARRAY_SIZE(gpio_resources),
1573         .resource = gpio_resources,
1574 };
1575
1576 static struct platform_device keypad_device = {
1577         .name = "keypad",
1578         .id = -1,
1579         .num_resources = ARRAY_SIZE(keypad_resources),
1580         .resource = keypad_resources,
1581 };
1582
1583 static struct platform_device rtc_device = {
1584         .name = "rtc-coh901331",
1585         .id = -1,
1586         .num_resources = ARRAY_SIZE(rtc_resources),
1587         .resource = rtc_resources,
1588 };
1589
1590 static struct mtd_partition u300_partitions[] = {
1591         {
1592                 .name = "bootrecords",
1593                 .offset = 0,
1594                 .size = SZ_128K,
1595         },
1596         {
1597                 .name = "free",
1598                 .offset = SZ_128K,
1599                 .size = 8064 * SZ_1K,
1600         },
1601         {
1602                 .name = "platform",
1603                 .offset = 8192 * SZ_1K,
1604                 .size = 253952 * SZ_1K,
1605         },
1606 };
1607
1608 static struct fsmc_nand_platform_data nand_platform_data = {
1609         .partitions = u300_partitions,
1610         .nr_partitions = ARRAY_SIZE(u300_partitions),
1611         .options = NAND_SKIP_BBTSCAN,
1612         .width = FSMC_NAND_BW8,
1613 };
1614
1615 static struct platform_device nand_device = {
1616         .name = "fsmc-nand",
1617         .id = -1,
1618         .resource = fsmc_resources,
1619         .num_resources = ARRAY_SIZE(fsmc_resources),
1620         .dev = {
1621                 .platform_data = &nand_platform_data,
1622         },
1623 };
1624
1625 static struct platform_device ave_device = {
1626         .name = "video_enc",
1627         .id = -1,
1628         .num_resources = ARRAY_SIZE(ave_resources),
1629         .resource = ave_resources,
1630 };
1631
1632 static struct platform_device dma_device = {
1633         .name           = "coh901318",
1634         .id             = -1,
1635         .resource       = dma_resource,
1636         .num_resources  = ARRAY_SIZE(dma_resource),
1637         .dev = {
1638                 .platform_data = &coh901318_platform,
1639                 .coherent_dma_mask = ~0,
1640         },
1641 };
1642
1643 static struct platform_device pinmux_device = {
1644         .name = "pinmux-u300",
1645         .id = -1,
1646         .num_resources = ARRAY_SIZE(pinmux_resources),
1647         .resource = pinmux_resources,
1648 };
1649
1650 /* Pinmux settings */
1651 static struct pinmux_map u300_pinmux_map[] = {
1652         /* anonymous maps for chip power and EMIFs */
1653         PINMUX_MAP_PRIMARY_SYS_HOG("POWER", "power"),
1654         PINMUX_MAP_PRIMARY_SYS_HOG("EMIF0", "emif0"),
1655         PINMUX_MAP_PRIMARY_SYS_HOG("EMIF1", "emif1"),
1656         /* per-device maps for MMC/SD, SPI and UART */
1657         PINMUX_MAP_PRIMARY("MMCSD", "mmc0", "mmci"),
1658         PINMUX_MAP_PRIMARY("SPI", "spi0", "pl022"),
1659         PINMUX_MAP_PRIMARY("UART0", "uart0", "uart0"),
1660 };
1661
1662 struct u300_mux_hog {
1663         const char *name;
1664         struct device *dev;
1665         struct pinmux *pmx;
1666 };
1667
1668 static struct u300_mux_hog u300_mux_hogs[] = {
1669         {
1670                 .name = "uart0",
1671                 .dev = &uart0_device.dev,
1672         },
1673         {
1674                 .name = "spi0",
1675                 .dev = &pl022_device.dev,
1676         },
1677         {
1678                 .name = "mmc0",
1679                 .dev = &mmcsd_device.dev,
1680         },
1681 };
1682
1683 static int __init u300_pinmux_fetch(void)
1684 {
1685         int i;
1686
1687         for (i = 0; i < ARRAY_SIZE(u300_mux_hogs); i++) {
1688                 struct pinmux *pmx;
1689                 int ret;
1690
1691                 pmx = pinmux_get(u300_mux_hogs[i].dev, NULL);
1692                 if (IS_ERR(pmx)) {
1693                         pr_err("u300: could not get pinmux hog %s\n",
1694                                u300_mux_hogs[i].name);
1695                         continue;
1696                 }
1697                 ret = pinmux_enable(pmx);
1698                 if (ret) {
1699                         pr_err("u300: could enable pinmux hog %s\n",
1700                                u300_mux_hogs[i].name);
1701                         continue;
1702                 }
1703                 u300_mux_hogs[i].pmx = pmx;
1704         }
1705         return 0;
1706 }
1707 subsys_initcall(u300_pinmux_fetch);
1708
1709 /*
1710  * Notice that AMBA devices are initialized before platform devices.
1711  *
1712  */
1713 static struct platform_device *platform_devs[] __initdata = {
1714         &dma_device,
1715         &i2c0_device,
1716         &i2c1_device,
1717         &keypad_device,
1718         &rtc_device,
1719         &gpio_device,
1720         &nand_device,
1721         &wdog_device,
1722         &ave_device,
1723         &pinmux_device,
1724 };
1725
1726 /*
1727  * Interrupts: the U300 platforms have two pl190 ARM PrimeCells connected
1728  * together so some interrupts are connected to the first one and some
1729  * to the second one.
1730  */
1731 void __init u300_init_irq(void)
1732 {
1733         u32 mask[2] = {0, 0};
1734         struct clk *clk;
1735         int i;
1736
1737         /* initialize clocking early, we want to clock the INTCON */
1738         u300_clock_init();
1739
1740         /* Clock the interrupt controller */
1741         clk = clk_get_sys("intcon", NULL);
1742         BUG_ON(IS_ERR(clk));
1743         clk_enable(clk);
1744
1745         for (i = 0; i < NR_IRQS; i++)
1746                 set_bit(i, (unsigned long *) &mask[0]);
1747         vic_init((void __iomem *) U300_INTCON0_VBASE, 0, mask[0], mask[0]);
1748         vic_init((void __iomem *) U300_INTCON1_VBASE, 32, mask[1], mask[1]);
1749 }
1750
1751
1752 /*
1753  * U300 platforms peripheral handling
1754  */
1755 struct db_chip {
1756         u16 chipid;
1757         const char *name;
1758 };
1759
1760 /*
1761  * This is a list of the Digital Baseband chips used in the U300 platform.
1762  */
1763 static struct db_chip db_chips[] __initdata = {
1764         {
1765                 .chipid = 0xb800,
1766                 .name = "DB3000",
1767         },
1768         {
1769                 .chipid = 0xc000,
1770                 .name = "DB3100",
1771         },
1772         {
1773                 .chipid = 0xc800,
1774                 .name = "DB3150",
1775         },
1776         {
1777                 .chipid = 0xd800,
1778                 .name = "DB3200",
1779         },
1780         {
1781                 .chipid = 0xe000,
1782                 .name = "DB3250",
1783         },
1784         {
1785                 .chipid = 0xe800,
1786                 .name = "DB3210",
1787         },
1788         {
1789                 .chipid = 0xf000,
1790                 .name = "DB3350 P1x",
1791         },
1792         {
1793                 .chipid = 0xf100,
1794                 .name = "DB3350 P2x",
1795         },
1796         {
1797                 .chipid = 0x0000, /* List terminator */
1798                 .name = NULL,
1799         }
1800 };
1801
1802 static void __init u300_init_check_chip(void)
1803 {
1804
1805         u16 val;
1806         struct db_chip *chip;
1807         const char *chipname;
1808         const char unknown[] = "UNKNOWN";
1809
1810         /* Read out and print chip ID */
1811         val = readw(U300_SYSCON_VBASE + U300_SYSCON_CIDR);
1812         /* This is in funky bigendian order... */
1813         val = (val & 0xFFU) << 8 | (val >> 8);
1814         chip = db_chips;
1815         chipname = unknown;
1816
1817         for ( ; chip->chipid; chip++) {
1818                 if (chip->chipid == (val & 0xFF00U)) {
1819                         chipname = chip->name;
1820                         break;
1821                 }
1822         }
1823         printk(KERN_INFO "Initializing U300 system on %s baseband chip " \
1824                "(chip ID 0x%04x)\n", chipname, val);
1825
1826 #ifdef CONFIG_MACH_U300_BS330
1827         if ((val & 0xFF00U) != 0xd800) {
1828                 printk(KERN_ERR "Platform configured for BS330 " \
1829                        "with DB3200 but %s detected, expect problems!",
1830                        chipname);
1831         }
1832 #endif
1833 #ifdef CONFIG_MACH_U300_BS335
1834         if ((val & 0xFF00U) != 0xf000 && (val & 0xFF00U) != 0xf100) {
1835                 printk(KERN_ERR "Platform configured for BS335 " \
1836                        " with DB3350 but %s detected, expect problems!",
1837                        chipname);
1838         }
1839 #endif
1840 #ifdef CONFIG_MACH_U300_BS365
1841         if ((val & 0xFF00U) != 0xe800) {
1842                 printk(KERN_ERR "Platform configured for BS365 " \
1843                        "with DB3210 but %s detected, expect problems!",
1844                        chipname);
1845         }
1846 #endif
1847
1848
1849 }
1850
1851 /*
1852  * Some devices and their resources require reserved physical memory from
1853  * the end of the available RAM. This function traverses the list of devices
1854  * and assigns actual addresses to these.
1855  */
1856 static void __init u300_assign_physmem(void)
1857 {
1858         unsigned long curr_start = __pa(high_memory);
1859         int i, j;
1860
1861         for (i = 0; i < ARRAY_SIZE(platform_devs); i++) {
1862                 for (j = 0; j < platform_devs[i]->num_resources; j++) {
1863                         struct resource *const res =
1864                           &platform_devs[i]->resource[j];
1865
1866                         if (IORESOURCE_MEM == res->flags &&
1867                                      0 == res->start) {
1868                                 res->start  = curr_start;
1869                                 res->end   += curr_start;
1870                                 curr_start += resource_size(res);
1871
1872                                 printk(KERN_INFO "core.c: Mapping RAM " \
1873                                        "%#x-%#x to device %s:%s\n",
1874                                         res->start, res->end,
1875                                        platform_devs[i]->name, res->name);
1876                         }
1877                 }
1878         }
1879 }
1880
1881 void __init u300_init_devices(void)
1882 {
1883         int i;
1884         u16 val;
1885
1886         /* Check what platform we run and print some status information */
1887         u300_init_check_chip();
1888
1889         /* Set system to run at PLL208, max performance, a known state. */
1890         val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
1891         val &= ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK;
1892         writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
1893         /* Wait for the PLL208 to lock if not locked in yet */
1894         while (!(readw(U300_SYSCON_VBASE + U300_SYSCON_CSR) &
1895                  U300_SYSCON_CSR_PLL208_LOCK_IND));
1896         /* Initialize SPI device with some board specifics */
1897         u300_spi_init(&pl022_device);
1898
1899         /* Register the AMBA devices in the AMBA bus abstraction layer */
1900         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
1901                 struct amba_device *d = amba_devs[i];
1902                 amba_device_register(d, &iomem_resource);
1903         }
1904
1905         u300_assign_physmem();
1906
1907         /* Initialize pinmuxing */
1908         pinmux_register_mappings(u300_pinmux_map,
1909                                  ARRAY_SIZE(u300_pinmux_map));
1910
1911         /* Register subdevices on the I2C buses */
1912         u300_i2c_register_board_devices();
1913
1914         /* Register the platform devices */
1915         platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
1916
1917         /* Register subdevices on the SPI bus */
1918         u300_spi_register_board_devices();
1919
1920 #ifndef CONFIG_MACH_U300_SEMI_IS_SHARED
1921         /*
1922          * Enable SEMI self refresh. Self-refresh of the SDRAM is entered when
1923          * both subsystems are requesting this mode.
1924          * If we not share the Acc SDRAM, this is never the case. Therefore
1925          * enable it here from the App side.
1926          */
1927         val = readw(U300_SYSCON_VBASE + U300_SYSCON_SMCR) |
1928                 U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE;
1929         writew(val, U300_SYSCON_VBASE + U300_SYSCON_SMCR);
1930 #endif /* CONFIG_MACH_U300_SEMI_IS_SHARED */
1931 }
1932
1933 static int core_module_init(void)
1934 {
1935         /*
1936          * This needs to be initialized later: it needs the input framework
1937          * to be initialized first.
1938          */
1939         return mmc_init(&mmcsd_device);
1940 }
1941 module_init(core_module_init);