arch/arm/mach-u300/core.c

   1 /*
   2  *
   3  * arch/arm/mach-u300/core.c
   4  *
   5  *
   6  * Copyright (C) 2007-2010 ST-Ericsson AB
   7  * License terms: GNU General Public License (GPL) version 2
   8  * Core platform support, IRQ handling and device definitions.
   9  * Author: Linus Walleij <linus.walleij@stericsson.com>
  10  */
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/spinlock.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/bitops.h>
  16 #include <linux/device.h>
  17 #include <linux/mm.h>
  18 #include <linux/termios.h>
  19 #include <linux/amba/bus.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/gpio.h>
  22 #include <linux/clk.h>
  23 #include <linux/err.h>
  24 #include <mach/coh901318.h>
  25
  26 #include <asm/types.h>
  27 #include <asm/setup.h>
  28 #include <asm/memory.h>
  29 #include <asm/hardware/vic.h>
  30 #include <asm/mach/map.h>
  31 #include <asm/mach/irq.h>
  32
  33 #include <mach/hardware.h>
  34 #include <mach/syscon.h>
  35 #include <mach/dma_channels.h>
  36
  37 #include "clock.h"
  38 #include "mmc.h"
  39 #include "spi.h"
  40 #include "i2c.h"
  41
  42 /*
  43  * Static I/O mappings that are needed for booting the U300 platforms. The
  44  * only things we need are the areas where we find the timer, syscon and
  45  * intcon, since the remaining device drivers will map their own memory
  46  * physical to virtual as the need arise.
  47  */
  48 static struct map_desc u300_io_desc[] __initdata = {
  49         {
  50                 .virtual        = U300_SLOW_PER_VIRT_BASE,
  51                 .pfn            = __phys_to_pfn(U300_SLOW_PER_PHYS_BASE),
  52                 .length         = SZ_64K,
  53                 .type           = MT_DEVICE,
  54         },
  55         {
  56                 .virtual        = U300_AHB_PER_VIRT_BASE,
  57                 .pfn            = __phys_to_pfn(U300_AHB_PER_PHYS_BASE),
  58                 .length         = SZ_32K,
  59                 .type           = MT_DEVICE,
  60         },
  61         {
  62                 .virtual        = U300_FAST_PER_VIRT_BASE,
  63                 .pfn            = __phys_to_pfn(U300_FAST_PER_PHYS_BASE),
  64                 .length         = SZ_32K,
  65                 .type           = MT_DEVICE,
  66         },
  67         {
  68                 .virtual        = 0xffff2000, /* TCM memory */
  69                 .pfn            = __phys_to_pfn(0xffff2000),
  70                 .length         = SZ_16K,
  71                 .type           = MT_DEVICE,
  72         },
  73
  74         /*
  75          * This overlaps with the IRQ vectors etc at 0xffff0000, so these
  76          * may have to be moved to 0x00000000 in order to use the ROM.
  77          */
  78         /*
  79         {
  80                 .virtual        = U300_BOOTROM_VIRT_BASE,
  81                 .pfn            = __phys_to_pfn(U300_BOOTROM_PHYS_BASE),
  82                 .length         = SZ_64K,
  83                 .type           = MT_ROM,
  84         },
  85         */
  86 };
  87
  88 void __init u300_map_io(void)
  89 {
  90         iotable_init(u300_io_desc, ARRAY_SIZE(u300_io_desc));
  91 }
  92
  93 /*
  94  * Declaration of devices found on the U300 board and
  95  * their respective memory locations.
  96  */
  97 static struct amba_device uart0_device = {
  98         .dev = {
  99                 .init_name = "uart0", /* Slow device at 0x3000 offset */
 100                 .platform_data = NULL,
 101         },
 102         .res = {
 103                 .start = U300_UART0_BASE,
 104                 .end   = U300_UART0_BASE + SZ_4K - 1,
 105                 .flags = IORESOURCE_MEM,
 106         },
 107         .irq = { IRQ_U300_UART0, NO_IRQ },
 108 };
 109
 110 /* The U335 have an additional UART1 on the APP CPU */
 111 #ifdef CONFIG_MACH_U300_BS335
 112 static struct amba_device uart1_device = {
 113         .dev = {
 114                 .init_name = "uart1", /* Fast device at 0x7000 offset */
 115                 .platform_data = NULL,
 116         },
 117         .res = {
 118                 .start = U300_UART1_BASE,
 119                 .end   = U300_UART1_BASE + SZ_4K - 1,
 120                 .flags = IORESOURCE_MEM,
 121         },
 122         .irq = { IRQ_U300_UART1, NO_IRQ },
 123 };
 124 #endif
 125
 126 static struct amba_device pl172_device = {
 127         .dev = {
 128                 .init_name = "pl172", /* AHB device at 0x4000 offset */
 129                 .platform_data = NULL,
 130         },
 131         .res = {
 132                 .start = U300_EMIF_CFG_BASE,
 133                 .end   = U300_EMIF_CFG_BASE + SZ_4K - 1,
 134                 .flags = IORESOURCE_MEM,
 135         },
 136 };
 137
 138
 139 /*
 140  * Everything within this next ifdef deals with external devices connected to
 141  * the APP SPI bus.
 142  */
 143 static struct amba_device pl022_device = {
 144         .dev = {
 145                 .coherent_dma_mask = ~0,
 146                 .init_name = "pl022", /* Fast device at 0x6000 offset */
 147         },
 148         .res = {
 149                 .start = U300_SPI_BASE,
 150                 .end   = U300_SPI_BASE + SZ_4K - 1,
 151                 .flags = IORESOURCE_MEM,
 152         },
 153         .irq = {IRQ_U300_SPI, NO_IRQ },
 154         /*
 155          * This device has a DMA channel but the Linux driver does not use
 156          * it currently.
 157          */
 158 };
 159
 160 static struct amba_device mmcsd_device = {
 161         .dev = {
 162                 .init_name = "mmci", /* Fast device at 0x1000 offset */
 163                 .platform_data = NULL, /* Added later */
 164         },
 165         .res = {
 166                 .start = U300_MMCSD_BASE,
 167                 .end   = U300_MMCSD_BASE + SZ_4K - 1,
 168                 .flags = IORESOURCE_MEM,
 169         },
 170         .irq = {IRQ_U300_MMCSD_MCIINTR0, IRQ_U300_MMCSD_MCIINTR1 },
 171         /*
 172          * This device has a DMA channel but the Linux driver does not use
 173          * it currently.
 174          */
 175 };
 176
 177 /*
 178  * The order of device declaration may be important, since some devices
 179  * have dependencies on other devices being initialized first.
 180  */
 181 static struct amba_device *amba_devs[] __initdata = {
 182         &uart0_device,
 183 #ifdef CONFIG_MACH_U300_BS335
 184         &uart1_device,
 185 #endif
 186         &pl022_device,
 187         &pl172_device,
 188         &mmcsd_device,
 189 };
 190
 191 /* Here follows a list of all hw resources that the platform devices
 192  * allocate. Note, clock dependencies are not included
 193  */
 194
 195 static struct resource gpio_resources[] = {
 196         {
 197                 .start = U300_GPIO_BASE,
 198                 .end   = (U300_GPIO_BASE + SZ_4K - 1),
 199                 .flags = IORESOURCE_MEM,
 200         },
 201         {
 202                 .name  = "gpio0",
 203                 .start = IRQ_U300_GPIO_PORT0,
 204                 .end   = IRQ_U300_GPIO_PORT0,
 205                 .flags = IORESOURCE_IRQ,
 206         },
 207         {
 208                 .name  = "gpio1",
 209                 .start = IRQ_U300_GPIO_PORT1,
 210                 .end   = IRQ_U300_GPIO_PORT1,
 211                 .flags = IORESOURCE_IRQ,
 212         },
 213         {
 214                 .name  = "gpio2",
 215                 .start = IRQ_U300_GPIO_PORT2,
 216                 .end   = IRQ_U300_GPIO_PORT2,
 217                 .flags = IORESOURCE_IRQ,
 218         },
 219 #ifdef U300_COH901571_3
 220         {
 221                 .name  = "gpio3",
 222                 .start = IRQ_U300_GPIO_PORT3,
 223                 .end   = IRQ_U300_GPIO_PORT3,
 224                 .flags = IORESOURCE_IRQ,
 225         },
 226         {
 227                 .name  = "gpio4",
 228                 .start = IRQ_U300_GPIO_PORT4,
 229                 .end   = IRQ_U300_GPIO_PORT4,
 230                 .flags = IORESOURCE_IRQ,
 231         },
 232 #ifdef CONFIG_MACH_U300_BS335
 233         {
 234                 .name  = "gpio5",
 235                 .start = IRQ_U300_GPIO_PORT5,
 236                 .end   = IRQ_U300_GPIO_PORT5,
 237                 .flags = IORESOURCE_IRQ,
 238         },
 239         {
 240                 .name  = "gpio6",
 241                 .start = IRQ_U300_GPIO_PORT6,
 242                 .end   = IRQ_U300_GPIO_PORT6,
 243                 .flags = IORESOURCE_IRQ,
 244         },
 245 #endif /* CONFIG_MACH_U300_BS335 */
 246 #endif /* U300_COH901571_3 */
 247 };
 248
 249 static struct resource keypad_resources[] = {
 250         {
 251                 .start = U300_KEYPAD_BASE,
 252                 .end   = U300_KEYPAD_BASE + SZ_4K - 1,
 253                 .flags = IORESOURCE_MEM,
 254         },
 255         {
 256                 .name  = "coh901461-press",
 257                 .start = IRQ_U300_KEYPAD_KEYBF,
 258                 .end   = IRQ_U300_KEYPAD_KEYBF,
 259                 .flags = IORESOURCE_IRQ,
 260         },
 261         {
 262                 .name  = "coh901461-release",
 263                 .start = IRQ_U300_KEYPAD_KEYBR,
 264                 .end   = IRQ_U300_KEYPAD_KEYBR,
 265                 .flags = IORESOURCE_IRQ,
 266         },
 267 };
 268
 269 static struct resource rtc_resources[] = {
 270         {
 271                 .start = U300_RTC_BASE,
 272                 .end   = U300_RTC_BASE + SZ_4K - 1,
 273                 .flags = IORESOURCE_MEM,
 274         },
 275         {
 276                 .start = IRQ_U300_RTC,
 277                 .end   = IRQ_U300_RTC,
 278                 .flags = IORESOURCE_IRQ,
 279         },
 280 };
 281
 282 /*
 283  * Fsmc does have IRQs: #43 and #44 (NFIF and NFIF2)
 284  * but these are not yet used by the driver.
 285  */
 286 static struct resource fsmc_resources[] = {
 287         {
 288                 .start = U300_NAND_IF_PHYS_BASE,
 289                 .end   = U300_NAND_IF_PHYS_BASE + SZ_4K - 1,
 290                 .flags = IORESOURCE_MEM,
 291         },
 292 };
 293
 294 static struct resource i2c0_resources[] = {
 295         {
 296                 .start = U300_I2C0_BASE,
 297                 .end   = U300_I2C0_BASE + SZ_4K - 1,
 298                 .flags = IORESOURCE_MEM,
 299         },
 300         {
 301                 .start = IRQ_U300_I2C0,
 302                 .end   = IRQ_U300_I2C0,
 303                 .flags = IORESOURCE_IRQ,
 304         },
 305 };
 306
 307 static struct resource i2c1_resources[] = {
 308         {
 309                 .start = U300_I2C1_BASE,
 310                 .end   = U300_I2C1_BASE + SZ_4K - 1,
 311                 .flags = IORESOURCE_MEM,
 312         },
 313         {
 314                 .start = IRQ_U300_I2C1,
 315                 .end   = IRQ_U300_I2C1,
 316                 .flags = IORESOURCE_IRQ,
 317         },
 318
 319 };
 320
 321 static struct resource wdog_resources[] = {
 322         {
 323                 .start = U300_WDOG_BASE,
 324                 .end   = U300_WDOG_BASE + SZ_4K - 1,
 325                 .flags = IORESOURCE_MEM,
 326         },
 327         {
 328                 .start = IRQ_U300_WDOG,
 329                 .end   = IRQ_U300_WDOG,
 330                 .flags = IORESOURCE_IRQ,
 331         }
 332 };
 333
 334 /* TODO: These should be protected by suitable #ifdef's */
 335 static struct resource ave_resources[] = {
 336         {
 337                 .name  = "AVE3e I/O Area",
 338                 .start = U300_VIDEOENC_BASE,
 339                 .end   = U300_VIDEOENC_BASE + SZ_512K - 1,
 340                 .flags = IORESOURCE_MEM,
 341         },
 342         {
 343                 .name  = "AVE3e IRQ0",
 344                 .start = IRQ_U300_VIDEO_ENC_0,
 345                 .end   = IRQ_U300_VIDEO_ENC_0,
 346                 .flags = IORESOURCE_IRQ,
 347         },
 348         {
 349                 .name  = "AVE3e IRQ1",
 350                 .start = IRQ_U300_VIDEO_ENC_1,
 351                 .end   = IRQ_U300_VIDEO_ENC_1,
 352                 .flags = IORESOURCE_IRQ,
 353         },
 354         {
 355                 .name  = "AVE3e Physmem Area",
 356                 .start = 0, /* 0 will be remapped to reserved memory */
 357                 .end   = SZ_1M - 1,
 358                 .flags = IORESOURCE_MEM,
 359         },
 360         /*
 361          * The AVE3e requires two regions of 256MB that it considers
 362          * "invisible". The hardware will not be able to access these
 363          * addresses, so they should never point to system RAM.
 364          */
 365         {
 366                 .name  = "AVE3e Reserved 0",
 367                 .start = 0xd0000000,
 368                 .end   = 0xd0000000 + SZ_256M - 1,
 369                 .flags = IORESOURCE_MEM,
 370         },
 371         {
 372                 .name  = "AVE3e Reserved 1",
 373                 .start = 0xe0000000,
 374                 .end   = 0xe0000000 + SZ_256M - 1,
 375                 .flags = IORESOURCE_MEM,
 376         },
 377 };
 378
 379 static struct resource dma_resource[] = {
 380         {
 381                 .start = U300_DMAC_BASE,
 382                 .end = U300_DMAC_BASE + PAGE_SIZE - 1,
 383                 .flags =  IORESOURCE_MEM,
 384         },
 385         {
 386                 .start = IRQ_U300_DMA,
 387                 .end = IRQ_U300_DMA,
 388                 .flags =  IORESOURCE_IRQ,
 389         }
 390 };
 391
 392 #ifdef CONFIG_MACH_U300_BS335
 393 /* points out all dma slave channels.
 394  * Syntax is [A1, B1, A2, B2, .... ,-1,-1]
 395  * Select all channels from A to B, end of list is marked with -1,-1
 396  */
 397 static int dma_slave_channels[] = {
 398         U300_DMA_MSL_TX_0, U300_DMA_SPI_RX,
 399         U300_DMA_UART1_TX, U300_DMA_UART1_RX, -1, -1};
 400
 401 /* points out all dma memcpy channels. */
 402 static int dma_memcpy_channels[] = {
 403         U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_8, -1, -1};
 404
 405 #else /* CONFIG_MACH_U300_BS335 */
 406
 407 static int dma_slave_channels[] = {U300_DMA_MSL_TX_0, U300_DMA_SPI_RX, -1, -1};
 408 static int dma_memcpy_channels[] = {
 409         U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_10, -1, -1};
 410
 411 #endif
 412
 413 /** register dma for memory access
 414  *
 415  * active  1 means dma intends to access memory
 416  *         0 means dma wont access memory
 417  */
 418 static void coh901318_access_memory_state(struct device *dev, bool active)
 419 {
 420 }
 421
 422 #define flags_memcpy_config (COH901318_CX_CFG_CH_DISABLE | \
 423                         COH901318_CX_CFG_RM_MEMORY_TO_MEMORY | \
 424                         COH901318_CX_CFG_LCR_DISABLE | \
 425                         COH901318_CX_CFG_TC_IRQ_ENABLE | \
 426                         COH901318_CX_CFG_BE_IRQ_ENABLE)
 427 #define flags_memcpy_lli_chained (COH901318_CX_CTRL_TC_ENABLE | \
 428                         COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
 429                         COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
 430                         COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
 431                         COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
 432                         COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
 433                         COH901318_CX_CTRL_MASTER_MODE_M1RW | \
 434                         COH901318_CX_CTRL_TCP_DISABLE | \
 435                         COH901318_CX_CTRL_TC_IRQ_DISABLE | \
 436                         COH901318_CX_CTRL_HSP_DISABLE | \
 437                         COH901318_CX_CTRL_HSS_DISABLE | \
 438                         COH901318_CX_CTRL_DDMA_LEGACY | \
 439                         COH901318_CX_CTRL_PRDD_SOURCE)
 440 #define flags_memcpy_lli (COH901318_CX_CTRL_TC_ENABLE | \
 441                         COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
 442                         COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
 443                         COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
 444                         COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
 445                         COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
 446                         COH901318_CX_CTRL_MASTER_MODE_M1RW | \
 447                         COH901318_CX_CTRL_TCP_DISABLE | \
 448                         COH901318_CX_CTRL_TC_IRQ_DISABLE | \
 449                         COH901318_CX_CTRL_HSP_DISABLE | \
 450                         COH901318_CX_CTRL_HSS_DISABLE | \
 451                         COH901318_CX_CTRL_DDMA_LEGACY | \
 452                         COH901318_CX_CTRL_PRDD_SOURCE)
 453 #define flags_memcpy_lli_last (COH901318_CX_CTRL_TC_ENABLE | \
 454                         COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
 455                         COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
 456                         COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
 457                         COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
 458                         COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
 459                         COH901318_CX_CTRL_MASTER_MODE_M1RW | \
 460                         COH901318_CX_CTRL_TCP_DISABLE | \
 461                         COH901318_CX_CTRL_TC_IRQ_ENABLE | \
 462                         COH901318_CX_CTRL_HSP_DISABLE | \
 463                         COH901318_CX_CTRL_HSS_DISABLE | \
 464                         COH901318_CX_CTRL_DDMA_LEGACY | \
 465                         COH901318_CX_CTRL_PRDD_SOURCE)
 466
 467 const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
 468         {
 469                 .number = U300_DMA_MSL_TX_0,
 470                 .name = "MSL TX 0",
 471                 .priority_high = 0,
 472                 .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x20,
 473         },
 474         {
 475                 .number = U300_DMA_MSL_TX_1,
 476                 .name = "MSL TX 1",
 477                 .priority_high = 0,
 478                 .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x20,
 479                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 480                                 COH901318_CX_CFG_LCR_DISABLE |
 481                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 482                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 483                 .param.ctrl_lli_chained = 0 |
 484                                 COH901318_CX_CTRL_TC_ENABLE |
 485                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 486                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 487                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 488                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 489                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 490                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 491                                 COH901318_CX_CTRL_TCP_DISABLE |
 492                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 493                                 COH901318_CX_CTRL_HSP_ENABLE |
 494                                 COH901318_CX_CTRL_HSS_DISABLE |
 495                                 COH901318_CX_CTRL_DDMA_LEGACY |
 496                                 COH901318_CX_CTRL_PRDD_SOURCE,
 497                 .param.ctrl_lli = 0 |
 498                                 COH901318_CX_CTRL_TC_ENABLE |
 499                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 500                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 501                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 502                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 503                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 504                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 505                                 COH901318_CX_CTRL_TCP_ENABLE |
 506                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 507                                 COH901318_CX_CTRL_HSP_ENABLE |
 508                                 COH901318_CX_CTRL_HSS_DISABLE |
 509                                 COH901318_CX_CTRL_DDMA_LEGACY |
 510                                 COH901318_CX_CTRL_PRDD_SOURCE,
 511                 .param.ctrl_lli_last = 0 |
 512                                 COH901318_CX_CTRL_TC_ENABLE |
 513                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 514                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 515                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 516                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 517                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 518                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 519                                 COH901318_CX_CTRL_TCP_ENABLE |
 520                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 521                                 COH901318_CX_CTRL_HSP_ENABLE |
 522                                 COH901318_CX_CTRL_HSS_DISABLE |
 523                                 COH901318_CX_CTRL_DDMA_LEGACY |
 524                                 COH901318_CX_CTRL_PRDD_SOURCE,
 525         },
 526         {
 527                 .number = U300_DMA_MSL_TX_2,
 528                 .name = "MSL TX 2",
 529                 .priority_high = 0,
 530                 .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x20,
 531                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 532                                 COH901318_CX_CFG_LCR_DISABLE |
 533                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 534                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 535                 .param.ctrl_lli_chained = 0 |
 536                                 COH901318_CX_CTRL_TC_ENABLE |
 537                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 538                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 539                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 540                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 541                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 542                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 543                                 COH901318_CX_CTRL_TCP_DISABLE |
 544                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 545                                 COH901318_CX_CTRL_HSP_ENABLE |
 546                                 COH901318_CX_CTRL_HSS_DISABLE |
 547                                 COH901318_CX_CTRL_DDMA_LEGACY |
 548                                 COH901318_CX_CTRL_PRDD_SOURCE,
 549                 .param.ctrl_lli = 0 |
 550                                 COH901318_CX_CTRL_TC_ENABLE |
 551                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 552                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 553                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 554                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 555                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 556                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 557                                 COH901318_CX_CTRL_TCP_ENABLE |
 558                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 559                                 COH901318_CX_CTRL_HSP_ENABLE |
 560                                 COH901318_CX_CTRL_HSS_DISABLE |
 561                                 COH901318_CX_CTRL_DDMA_LEGACY |
 562                                 COH901318_CX_CTRL_PRDD_SOURCE,
 563                 .param.ctrl_lli_last = 0 |
 564                                 COH901318_CX_CTRL_TC_ENABLE |
 565                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 566                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 567                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 568                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 569                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 570                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 571                                 COH901318_CX_CTRL_TCP_ENABLE |
 572                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 573                                 COH901318_CX_CTRL_HSP_ENABLE |
 574                                 COH901318_CX_CTRL_HSS_DISABLE |
 575                                 COH901318_CX_CTRL_DDMA_LEGACY |
 576                                 COH901318_CX_CTRL_PRDD_SOURCE,
 577                 .desc_nbr_max = 10,
 578         },
 579         {
 580                 .number = U300_DMA_MSL_TX_3,
 581                 .name = "MSL TX 3",
 582                 .priority_high = 0,
 583                 .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x20,
 584                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 585                                 COH901318_CX_CFG_LCR_DISABLE |
 586                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 587                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 588                 .param.ctrl_lli_chained = 0 |
 589                                 COH901318_CX_CTRL_TC_ENABLE |
 590                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 591                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 592                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 593                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 594                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 595                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 596                                 COH901318_CX_CTRL_TCP_DISABLE |
 597                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 598                                 COH901318_CX_CTRL_HSP_ENABLE |
 599                                 COH901318_CX_CTRL_HSS_DISABLE |
 600                                 COH901318_CX_CTRL_DDMA_LEGACY |
 601                                 COH901318_CX_CTRL_PRDD_SOURCE,
 602                 .param.ctrl_lli = 0 |
 603                                 COH901318_CX_CTRL_TC_ENABLE |
 604                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 605                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 606                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 607                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 608                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 609                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 610                                 COH901318_CX_CTRL_TCP_ENABLE |
 611                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 612                                 COH901318_CX_CTRL_HSP_ENABLE |
 613                                 COH901318_CX_CTRL_HSS_DISABLE |
 614                                 COH901318_CX_CTRL_DDMA_LEGACY |
 615                                 COH901318_CX_CTRL_PRDD_SOURCE,
 616                 .param.ctrl_lli_last = 0 |
 617                                 COH901318_CX_CTRL_TC_ENABLE |
 618                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 619                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 620                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 621                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 622                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 623                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 624                                 COH901318_CX_CTRL_TCP_ENABLE |
 625                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 626                                 COH901318_CX_CTRL_HSP_ENABLE |
 627                                 COH901318_CX_CTRL_HSS_DISABLE |
 628                                 COH901318_CX_CTRL_DDMA_LEGACY |
 629                                 COH901318_CX_CTRL_PRDD_SOURCE,
 630         },
 631         {
 632                 .number = U300_DMA_MSL_TX_4,
 633                 .name = "MSL TX 4",
 634                 .priority_high = 0,
 635                 .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x20,
 636                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 637                                 COH901318_CX_CFG_LCR_DISABLE |
 638                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 639                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 640                 .param.ctrl_lli_chained = 0 |
 641                                 COH901318_CX_CTRL_TC_ENABLE |
 642                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 643                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 644                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 645                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 646                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 647                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 648                                 COH901318_CX_CTRL_TCP_DISABLE |
 649                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 650                                 COH901318_CX_CTRL_HSP_ENABLE |
 651                                 COH901318_CX_CTRL_HSS_DISABLE |
 652                                 COH901318_CX_CTRL_DDMA_LEGACY |
 653                                 COH901318_CX_CTRL_PRDD_SOURCE,
 654                 .param.ctrl_lli = 0 |
 655                                 COH901318_CX_CTRL_TC_ENABLE |
 656                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 657                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 658                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 659                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 660                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 661                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 662                                 COH901318_CX_CTRL_TCP_ENABLE |
 663                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 664                                 COH901318_CX_CTRL_HSP_ENABLE |
 665                                 COH901318_CX_CTRL_HSS_DISABLE |
 666                                 COH901318_CX_CTRL_DDMA_LEGACY |
 667                                 COH901318_CX_CTRL_PRDD_SOURCE,
 668                 .param.ctrl_lli_last = 0 |
 669                                 COH901318_CX_CTRL_TC_ENABLE |
 670                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 671                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 672                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 673                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 674                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 675                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 676                                 COH901318_CX_CTRL_TCP_ENABLE |
 677                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 678                                 COH901318_CX_CTRL_HSP_ENABLE |
 679                                 COH901318_CX_CTRL_HSS_DISABLE |
 680                                 COH901318_CX_CTRL_DDMA_LEGACY |
 681                                 COH901318_CX_CTRL_PRDD_SOURCE,
 682         },
 683         {
 684                 .number = U300_DMA_MSL_TX_5,
 685                 .name = "MSL TX 5",
 686                 .priority_high = 0,
 687                 .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x20,
 688         },
 689         {
 690                 .number = U300_DMA_MSL_TX_6,
 691                 .name = "MSL TX 6",
 692                 .priority_high = 0,
 693                 .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x20,
 694         },
 695         {
 696                 .number = U300_DMA_MSL_RX_0,
 697                 .name = "MSL RX 0",
 698                 .priority_high = 0,
 699                 .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x220,
 700         },
 701         {
 702                 .number = U300_DMA_MSL_RX_1,
 703                 .name = "MSL RX 1",
 704                 .priority_high = 0,
 705                 .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x220,
 706                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 707                                 COH901318_CX_CFG_LCR_DISABLE |
 708                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 709                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 710                 .param.ctrl_lli_chained = 0 |
 711                                 COH901318_CX_CTRL_TC_ENABLE |
 712                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 713                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 714                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 715                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 716                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 717                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 718                                 COH901318_CX_CTRL_TCP_DISABLE |
 719                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 720                                 COH901318_CX_CTRL_HSP_ENABLE |
 721                                 COH901318_CX_CTRL_HSS_DISABLE |
 722                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 723                                 COH901318_CX_CTRL_PRDD_DEST,
 724                 .param.ctrl_lli = 0,
 725                 .param.ctrl_lli_last = 0 |
 726                                 COH901318_CX_CTRL_TC_ENABLE |
 727                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 728                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 729                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 730                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 731                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 732                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 733                                 COH901318_CX_CTRL_TCP_DISABLE |
 734                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 735                                 COH901318_CX_CTRL_HSP_ENABLE |
 736                                 COH901318_CX_CTRL_HSS_DISABLE |
 737                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 738                                 COH901318_CX_CTRL_PRDD_DEST,
 739         },
 740         {
 741                 .number = U300_DMA_MSL_RX_2,
 742                 .name = "MSL RX 2",
 743                 .priority_high = 0,
 744                 .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x220,
 745                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 746                                 COH901318_CX_CFG_LCR_DISABLE |
 747                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 748                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 749                 .param.ctrl_lli_chained = 0 |
 750                                 COH901318_CX_CTRL_TC_ENABLE |
 751                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 752                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 753                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 754                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 755                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 756                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 757                                 COH901318_CX_CTRL_TCP_DISABLE |
 758                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 759                                 COH901318_CX_CTRL_HSP_ENABLE |
 760                                 COH901318_CX_CTRL_HSS_DISABLE |
 761                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 762                                 COH901318_CX_CTRL_PRDD_DEST,
 763                 .param.ctrl_lli = 0 |
 764                                 COH901318_CX_CTRL_TC_ENABLE |
 765                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 766                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 767                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 768                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 769                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 770                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 771                                 COH901318_CX_CTRL_TCP_DISABLE |
 772                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 773                                 COH901318_CX_CTRL_HSP_ENABLE |
 774                                 COH901318_CX_CTRL_HSS_DISABLE |
 775                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 776                                 COH901318_CX_CTRL_PRDD_DEST,
 777                 .param.ctrl_lli_last = 0 |
 778                                 COH901318_CX_CTRL_TC_ENABLE |
 779                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 780                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 781                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 782                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 783                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 784                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 785                                 COH901318_CX_CTRL_TCP_DISABLE |
 786                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 787                                 COH901318_CX_CTRL_HSP_ENABLE |
 788                                 COH901318_CX_CTRL_HSS_DISABLE |
 789                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 790                                 COH901318_CX_CTRL_PRDD_DEST,
 791         },
 792         {
 793                 .number = U300_DMA_MSL_RX_3,
 794                 .name = "MSL RX 3",
 795                 .priority_high = 0,
 796                 .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x220,
 797                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 798                                 COH901318_CX_CFG_LCR_DISABLE |
 799                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 800                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 801                 .param.ctrl_lli_chained = 0 |
 802                                 COH901318_CX_CTRL_TC_ENABLE |
 803                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 804                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 805                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 806                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 807                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 808                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 809                                 COH901318_CX_CTRL_TCP_DISABLE |
 810                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 811                                 COH901318_CX_CTRL_HSP_ENABLE |
 812                                 COH901318_CX_CTRL_HSS_DISABLE |
 813                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 814                                 COH901318_CX_CTRL_PRDD_DEST,
 815                 .param.ctrl_lli = 0 |
 816                                 COH901318_CX_CTRL_TC_ENABLE |
 817                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 818                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 819                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 820                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 821                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 822                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 823                                 COH901318_CX_CTRL_TCP_DISABLE |
 824                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 825                                 COH901318_CX_CTRL_HSP_ENABLE |
 826                                 COH901318_CX_CTRL_HSS_DISABLE |
 827                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 828                                 COH901318_CX_CTRL_PRDD_DEST,
 829                 .param.ctrl_lli_last = 0 |
 830                                 COH901318_CX_CTRL_TC_ENABLE |
 831                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 832                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 833                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 834                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 835                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 836                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 837                                 COH901318_CX_CTRL_TCP_DISABLE |
 838                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 839                                 COH901318_CX_CTRL_HSP_ENABLE |
 840                                 COH901318_CX_CTRL_HSS_DISABLE |
 841                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 842                                 COH901318_CX_CTRL_PRDD_DEST,
 843         },
 844         {
 845                 .number = U300_DMA_MSL_RX_4,
 846                 .name = "MSL RX 4",
 847                 .priority_high = 0,
 848                 .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x220,
 849                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 850                                 COH901318_CX_CFG_LCR_DISABLE |
 851                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 852                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 853                 .param.ctrl_lli_chained = 0 |
 854                                 COH901318_CX_CTRL_TC_ENABLE |
 855                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 856                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 857                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 858                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 859                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 860                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 861                                 COH901318_CX_CTRL_TCP_DISABLE |
 862                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 863                                 COH901318_CX_CTRL_HSP_ENABLE |
 864                                 COH901318_CX_CTRL_HSS_DISABLE |
 865                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 866                                 COH901318_CX_CTRL_PRDD_DEST,
 867                 .param.ctrl_lli = 0 |
 868                                 COH901318_CX_CTRL_TC_ENABLE |
 869                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 870                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 871                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 872                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 873                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 874                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 875                                 COH901318_CX_CTRL_TCP_DISABLE |
 876                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 877                                 COH901318_CX_CTRL_HSP_ENABLE |
 878                                 COH901318_CX_CTRL_HSS_DISABLE |
 879                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 880                                 COH901318_CX_CTRL_PRDD_DEST,
 881                 .param.ctrl_lli_last = 0 |
 882                                 COH901318_CX_CTRL_TC_ENABLE |
 883                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 884                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 885                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 886                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 887                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 888                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 889                                 COH901318_CX_CTRL_TCP_DISABLE |
 890                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 891                                 COH901318_CX_CTRL_HSP_ENABLE |
 892                                 COH901318_CX_CTRL_HSS_DISABLE |
 893                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 894                                 COH901318_CX_CTRL_PRDD_DEST,
 895         },
 896         {
 897                 .number = U300_DMA_MSL_RX_5,
 898                 .name = "MSL RX 5",
 899                 .priority_high = 0,
 900                 .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x220,
 901                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 902                                 COH901318_CX_CFG_LCR_DISABLE |
 903                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 904                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 905                 .param.ctrl_lli_chained = 0 |
 906                                 COH901318_CX_CTRL_TC_ENABLE |
 907                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 908                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 909                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 910                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 911                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 912                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 913                                 COH901318_CX_CTRL_TCP_DISABLE |
 914                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 915                                 COH901318_CX_CTRL_HSP_ENABLE |
 916                                 COH901318_CX_CTRL_HSS_DISABLE |
 917                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 918                                 COH901318_CX_CTRL_PRDD_DEST,
 919                 .param.ctrl_lli = 0 |
 920                                 COH901318_CX_CTRL_TC_ENABLE |
 921                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 922                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 923                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 924                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 925                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 926                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 927                                 COH901318_CX_CTRL_TCP_DISABLE |
 928                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 929                                 COH901318_CX_CTRL_HSP_ENABLE |
 930                                 COH901318_CX_CTRL_HSS_DISABLE |
 931                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 932                                 COH901318_CX_CTRL_PRDD_DEST,
 933                 .param.ctrl_lli_last = 0 |
 934                                 COH901318_CX_CTRL_TC_ENABLE |
 935                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 936                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 937                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 938                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 939                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 940                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 941                                 COH901318_CX_CTRL_TCP_DISABLE |
 942                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 943                                 COH901318_CX_CTRL_HSP_ENABLE |
 944                                 COH901318_CX_CTRL_HSS_DISABLE |
 945                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 946                                 COH901318_CX_CTRL_PRDD_DEST,
 947         },
 948         {
 949                 .number = U300_DMA_MSL_RX_6,
 950                 .name = "MSL RX 6",
 951                 .priority_high = 0,
 952                 .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x220,
 953         },
 954         {
 955                 .number = U300_DMA_MMCSD_RX_TX,
 956                 .name = "MMCSD RX TX",
 957                 .priority_high = 0,
 958                 .dev_addr =  U300_MMCSD_BASE + 0x080,
 959                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 960                                 COH901318_CX_CFG_LCR_DISABLE |
 961                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 962                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 963                 .param.ctrl_lli_chained = 0 |
 964                                 COH901318_CX_CTRL_TC_ENABLE |
 965                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 966                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 967                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 968                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
 969                                 COH901318_CX_CTRL_TCP_ENABLE |
 970                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 971                                 COH901318_CX_CTRL_HSP_ENABLE |
 972                                 COH901318_CX_CTRL_HSS_DISABLE |
 973                                 COH901318_CX_CTRL_DDMA_LEGACY,
 974                 .param.ctrl_lli = 0 |
 975                                 COH901318_CX_CTRL_TC_ENABLE |
 976                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 977                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 978                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 979                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
 980                                 COH901318_CX_CTRL_TCP_ENABLE |
 981                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 982                                 COH901318_CX_CTRL_HSP_ENABLE |
 983                                 COH901318_CX_CTRL_HSS_DISABLE |
 984                                 COH901318_CX_CTRL_DDMA_LEGACY,
 985                 .param.ctrl_lli_last = 0 |
 986                                 COH901318_CX_CTRL_TC_ENABLE |
 987                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 988                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 989                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 990                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
 991                                 COH901318_CX_CTRL_TCP_DISABLE |
 992                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 993                                 COH901318_CX_CTRL_HSP_ENABLE |
 994                                 COH901318_CX_CTRL_HSS_DISABLE |
 995                                 COH901318_CX_CTRL_DDMA_LEGACY,
 996
 997         },
 998         {
 999                 .number = U300_DMA_MSPRO_TX,
1000                 .name = "MSPRO TX",
1001                 .priority_high = 0,
1002         },
1003         {
1004                 .number = U300_DMA_MSPRO_RX,
1005                 .name = "MSPRO RX",
1006                 .priority_high = 0,
1007         },
1008         {
1009                 .number = U300_DMA_UART0_TX,
1010                 .name = "UART0 TX",
1011                 .priority_high = 0,
1012         },
1013         {
1014                 .number = U300_DMA_UART0_RX,
1015                 .name = "UART0 RX",
1016                 .priority_high = 0,
1017         },
1018         {
1019                 .number = U300_DMA_APEX_TX,
1020                 .name = "APEX TX",
1021                 .priority_high = 0,
1022         },
1023         {
1024                 .number = U300_DMA_APEX_RX,
1025                 .name = "APEX RX",
1026                 .priority_high = 0,
1027         },
1028         {
1029                 .number = U300_DMA_PCM_I2S0_TX,
1030                 .name = "PCM I2S0 TX",
1031                 .priority_high = 1,
1032                 .dev_addr = U300_PCM_I2S0_BASE + 0x14,
1033                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1034                                 COH901318_CX_CFG_LCR_DISABLE |
1035                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1036                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1037                 .param.ctrl_lli_chained = 0 |
1038                                 COH901318_CX_CTRL_TC_ENABLE |
1039                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1040                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1041                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1042                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1043                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1044                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1045                                 COH901318_CX_CTRL_TCP_DISABLE |
1046                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1047                                 COH901318_CX_CTRL_HSP_ENABLE |
1048                                 COH901318_CX_CTRL_HSS_DISABLE |
1049                                 COH901318_CX_CTRL_DDMA_LEGACY |
1050                                 COH901318_CX_CTRL_PRDD_SOURCE,
1051                 .param.ctrl_lli = 0 |
1052                                 COH901318_CX_CTRL_TC_ENABLE |
1053                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1054                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1055                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1056                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1057                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1058                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1059                                 COH901318_CX_CTRL_TCP_ENABLE |
1060                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1061                                 COH901318_CX_CTRL_HSP_ENABLE |
1062                                 COH901318_CX_CTRL_HSS_DISABLE |
1063                                 COH901318_CX_CTRL_DDMA_LEGACY |
1064                                 COH901318_CX_CTRL_PRDD_SOURCE,
1065                 .param.ctrl_lli_last = 0 |
1066                                 COH901318_CX_CTRL_TC_ENABLE |
1067                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1068                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1069                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1070                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1071                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1072                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1073                                 COH901318_CX_CTRL_TCP_ENABLE |
1074                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1075                                 COH901318_CX_CTRL_HSP_ENABLE |
1076                                 COH901318_CX_CTRL_HSS_DISABLE |
1077                                 COH901318_CX_CTRL_DDMA_LEGACY |
1078                                 COH901318_CX_CTRL_PRDD_SOURCE,
1079         },
1080         {
1081                 .number = U300_DMA_PCM_I2S0_RX,
1082                 .name = "PCM I2S0 RX",
1083                 .priority_high = 1,
1084                 .dev_addr = U300_PCM_I2S0_BASE + 0x10,
1085                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1086                                 COH901318_CX_CFG_LCR_DISABLE |
1087                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1088                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1089                 .param.ctrl_lli_chained = 0 |
1090                                 COH901318_CX_CTRL_TC_ENABLE |
1091                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1092                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1093                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1094                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1095                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1096                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1097                                 COH901318_CX_CTRL_TCP_DISABLE |
1098                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1099                                 COH901318_CX_CTRL_HSP_ENABLE |
1100                                 COH901318_CX_CTRL_HSS_DISABLE |
1101                                 COH901318_CX_CTRL_DDMA_LEGACY |
1102                                 COH901318_CX_CTRL_PRDD_DEST,
1103                 .param.ctrl_lli = 0 |
1104                                 COH901318_CX_CTRL_TC_ENABLE |
1105                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1106                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1107                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1108                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1109                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1110                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1111                                 COH901318_CX_CTRL_TCP_ENABLE |
1112                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1113                                 COH901318_CX_CTRL_HSP_ENABLE |
1114                                 COH901318_CX_CTRL_HSS_DISABLE |
1115                                 COH901318_CX_CTRL_DDMA_LEGACY |
1116                                 COH901318_CX_CTRL_PRDD_DEST,
1117                 .param.ctrl_lli_last = 0 |
1118                                 COH901318_CX_CTRL_TC_ENABLE |
1119                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1120                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1121                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1122                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1123                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1124                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1125                                 COH901318_CX_CTRL_TCP_ENABLE |
1126                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1127                                 COH901318_CX_CTRL_HSP_ENABLE |
1128                                 COH901318_CX_CTRL_HSS_DISABLE |
1129                                 COH901318_CX_CTRL_DDMA_LEGACY |
1130                                 COH901318_CX_CTRL_PRDD_DEST,
1131         },
1132         {
1133                 .number = U300_DMA_PCM_I2S1_TX,
1134                 .name = "PCM I2S1 TX",
1135                 .priority_high = 1,
1136                 .dev_addr =  U300_PCM_I2S1_BASE + 0x14,
1137                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1138                                 COH901318_CX_CFG_LCR_DISABLE |
1139                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1140                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1141                 .param.ctrl_lli_chained = 0 |
1142                                 COH901318_CX_CTRL_TC_ENABLE |
1143                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1144                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1145                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1146                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1147                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1148                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1149                                 COH901318_CX_CTRL_TCP_DISABLE |
1150                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1151                                 COH901318_CX_CTRL_HSP_ENABLE |
1152                                 COH901318_CX_CTRL_HSS_DISABLE |
1153                                 COH901318_CX_CTRL_DDMA_LEGACY |
1154                                 COH901318_CX_CTRL_PRDD_SOURCE,
1155                 .param.ctrl_lli = 0 |
1156                                 COH901318_CX_CTRL_TC_ENABLE |
1157                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1158                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1159                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1160                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1161                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1162                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1163                                 COH901318_CX_CTRL_TCP_ENABLE |
1164                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1165                                 COH901318_CX_CTRL_HSP_ENABLE |
1166                                 COH901318_CX_CTRL_HSS_DISABLE |
1167                                 COH901318_CX_CTRL_DDMA_LEGACY |
1168                                 COH901318_CX_CTRL_PRDD_SOURCE,
1169                 .param.ctrl_lli_last = 0 |
1170                                 COH901318_CX_CTRL_TC_ENABLE |
1171                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1172                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1173                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1174                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1175                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1176                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1177                                 COH901318_CX_CTRL_TCP_ENABLE |
1178                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1179                                 COH901318_CX_CTRL_HSP_ENABLE |
1180                                 COH901318_CX_CTRL_HSS_DISABLE |
1181                                 COH901318_CX_CTRL_DDMA_LEGACY |
1182                                 COH901318_CX_CTRL_PRDD_SOURCE,
1183         },
1184         {
1185                 .number = U300_DMA_PCM_I2S1_RX,
1186                 .name = "PCM I2S1 RX",
1187                 .priority_high = 1,
1188                 .dev_addr = U300_PCM_I2S1_BASE + 0x10,
1189                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1190                                 COH901318_CX_CFG_LCR_DISABLE |
1191                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1192                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1193                 .param.ctrl_lli_chained = 0 |
1194                                 COH901318_CX_CTRL_TC_ENABLE |
1195                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1196                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1197                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1198                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1199                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1200                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1201                                 COH901318_CX_CTRL_TCP_DISABLE |
1202                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1203                                 COH901318_CX_CTRL_HSP_ENABLE |
1204                                 COH901318_CX_CTRL_HSS_DISABLE |
1205                                 COH901318_CX_CTRL_DDMA_LEGACY |
1206                                 COH901318_CX_CTRL_PRDD_DEST,
1207                 .param.ctrl_lli = 0 |
1208                                 COH901318_CX_CTRL_TC_ENABLE |
1209                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1210                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1211                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1212                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1213                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1214                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1215                                 COH901318_CX_CTRL_TCP_ENABLE |
1216                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1217                                 COH901318_CX_CTRL_HSP_ENABLE |
1218                                 COH901318_CX_CTRL_HSS_DISABLE |
1219                                 COH901318_CX_CTRL_DDMA_LEGACY |
1220                                 COH901318_CX_CTRL_PRDD_DEST,
1221                 .param.ctrl_lli_last = 0 |
1222                                 COH901318_CX_CTRL_TC_ENABLE |
1223                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1224                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1225                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1226                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1227                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1228                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1229                                 COH901318_CX_CTRL_TCP_ENABLE |
1230                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1231                                 COH901318_CX_CTRL_HSP_ENABLE |
1232                                 COH901318_CX_CTRL_HSS_DISABLE |
1233                                 COH901318_CX_CTRL_DDMA_LEGACY |
1234                                 COH901318_CX_CTRL_PRDD_DEST,
1235         },
1236         {
1237                 .number = U300_DMA_XGAM_CDI,
1238                 .name = "XGAM CDI",
1239                 .priority_high = 0,
1240         },
1241         {
1242                 .number = U300_DMA_XGAM_PDI,
1243                 .name = "XGAM PDI",
1244                 .priority_high = 0,
1245         },
1246         {
1247                 .number = U300_DMA_SPI_TX,
1248                 .name = "SPI TX",
1249                 .priority_high = 0,
1250         },
1251         {
1252                 .number = U300_DMA_SPI_RX,
1253                 .name = "SPI RX",
1254                 .priority_high = 0,
1255         },
1256         {
1257                 .number = U300_DMA_GENERAL_PURPOSE_0,
1258                 .name = "GENERAL 00",
1259                 .priority_high = 0,
1260
1261                 .param.config = flags_memcpy_config,
1262                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1263                 .param.ctrl_lli = flags_memcpy_lli,
1264                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1265         },
1266         {
1267                 .number = U300_DMA_GENERAL_PURPOSE_1,
1268                 .name = "GENERAL 01",
1269                 .priority_high = 0,
1270
1271                 .param.config = flags_memcpy_config,
1272                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1273                 .param.ctrl_lli = flags_memcpy_lli,
1274                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1275         },
1276         {
1277                 .number = U300_DMA_GENERAL_PURPOSE_2,
1278                 .name = "GENERAL 02",
1279                 .priority_high = 0,
1280
1281                 .param.config = flags_memcpy_config,
1282                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1283                 .param.ctrl_lli = flags_memcpy_lli,
1284                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1285         },
1286         {
1287                 .number = U300_DMA_GENERAL_PURPOSE_3,
1288                 .name = "GENERAL 03",
1289                 .priority_high = 0,
1290
1291                 .param.config = flags_memcpy_config,
1292                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1293                 .param.ctrl_lli = flags_memcpy_lli,
1294                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1295         },
1296         {
1297                 .number = U300_DMA_GENERAL_PURPOSE_4,
1298                 .name = "GENERAL 04",
1299                 .priority_high = 0,
1300
1301                 .param.config = flags_memcpy_config,
1302                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1303                 .param.ctrl_lli = flags_memcpy_lli,
1304                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1305         },
1306         {
1307                 .number = U300_DMA_GENERAL_PURPOSE_5,
1308                 .name = "GENERAL 05",
1309                 .priority_high = 0,
1310
1311                 .param.config = flags_memcpy_config,
1312                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1313                 .param.ctrl_lli = flags_memcpy_lli,
1314                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1315         },
1316         {
1317                 .number = U300_DMA_GENERAL_PURPOSE_6,
1318                 .name = "GENERAL 06",
1319                 .priority_high = 0,
1320
1321                 .param.config = flags_memcpy_config,
1322                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1323                 .param.ctrl_lli = flags_memcpy_lli,
1324                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1325         },
1326         {
1327                 .number = U300_DMA_GENERAL_PURPOSE_7,
1328                 .name = "GENERAL 07",
1329                 .priority_high = 0,
1330
1331                 .param.config = flags_memcpy_config,
1332                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1333                 .param.ctrl_lli = flags_memcpy_lli,
1334                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1335         },
1336         {
1337                 .number = U300_DMA_GENERAL_PURPOSE_8,
1338                 .name = "GENERAL 08",
1339                 .priority_high = 0,
1340
1341                 .param.config = flags_memcpy_config,
1342                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1343                 .param.ctrl_lli = flags_memcpy_lli,
1344                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1345         },
1346 #ifdef CONFIG_MACH_U300_BS335
1347         {
1348                 .number = U300_DMA_UART1_TX,
1349                 .name = "UART1 TX",
1350                 .priority_high = 0,
1351         },
1352         {
1353                 .number = U300_DMA_UART1_RX,
1354                 .name = "UART1 RX",
1355                 .priority_high = 0,
1356         }
1357 #else
1358         {
1359                 .number = U300_DMA_GENERAL_PURPOSE_9,
1360                 .name = "GENERAL 09",
1361                 .priority_high = 0,
1362
1363                 .param.config = flags_memcpy_config,
1364                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1365                 .param.ctrl_lli = flags_memcpy_lli,
1366                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1367         },
1368         {
1369                 .number = U300_DMA_GENERAL_PURPOSE_10,
1370                 .name = "GENERAL 10",
1371                 .priority_high = 0,
1372
1373                 .param.config = flags_memcpy_config,
1374                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1375                 .param.ctrl_lli = flags_memcpy_lli,
1376                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1377         }
1378 #endif
1379 };
1380
1381
1382 static struct coh901318_platform coh901318_platform = {
1383         .chans_slave = dma_slave_channels,
1384         .chans_memcpy = dma_memcpy_channels,
1385         .access_memory_state = coh901318_access_memory_state,
1386         .chan_conf = chan_config,
1387         .max_channels = U300_DMA_CHANNELS,
1388 };
1389
1390 static struct platform_device wdog_device = {
1391         .name = "coh901327_wdog",
1392         .id = -1,
1393         .num_resources = ARRAY_SIZE(wdog_resources),
1394         .resource = wdog_resources,
1395 };
1396
1397 static struct platform_device i2c0_device = {
1398         .name = "stu300",
1399         .id = 0,
1400         .num_resources = ARRAY_SIZE(i2c0_resources),
1401         .resource = i2c0_resources,
1402 };
1403
1404 static struct platform_device i2c1_device = {
1405         .name = "stu300",
1406         .id = 1,
1407         .num_resources = ARRAY_SIZE(i2c1_resources),
1408         .resource = i2c1_resources,
1409 };
1410
1411 static struct platform_device gpio_device = {
1412         .name = "u300-gpio",
1413         .id = -1,
1414         .num_resources = ARRAY_SIZE(gpio_resources),
1415         .resource = gpio_resources,
1416 };
1417
1418 static struct platform_device keypad_device = {
1419         .name = "keypad",
1420         .id = -1,
1421         .num_resources = ARRAY_SIZE(keypad_resources),
1422         .resource = keypad_resources,
1423 };
1424
1425 static struct platform_device rtc_device = {
1426         .name = "rtc-coh901331",
1427         .id = -1,
1428         .num_resources = ARRAY_SIZE(rtc_resources),
1429         .resource = rtc_resources,
1430 };
1431
1432 static struct platform_device fsmc_device = {
1433         .name = "nandif",
1434         .id = -1,
1435         .num_resources = ARRAY_SIZE(fsmc_resources),
1436         .resource = fsmc_resources,
1437 };
1438
1439 static struct platform_device ave_device = {
1440         .name = "video_enc",
1441         .id = -1,
1442         .num_resources = ARRAY_SIZE(ave_resources),
1443         .resource = ave_resources,
1444 };
1445
1446 static struct platform_device dma_device = {
1447         .name           = "coh901318",
1448         .id             = -1,
1449         .resource       = dma_resource,
1450         .num_resources  = ARRAY_SIZE(dma_resource),
1451         .dev = {
1452                 .platform_data = &coh901318_platform,
1453                 .coherent_dma_mask = ~0,
1454         },
1455 };
1456
1457 /*
1458  * Notice that AMBA devices are initialized before platform devices.
1459  *
1460  */
1461 static struct platform_device *platform_devs[] __initdata = {
1462         &dma_device,
1463         &i2c0_device,
1464         &i2c1_device,
1465         &keypad_device,
1466         &rtc_device,
1467         &gpio_device,
1468         &fsmc_device,
1469         &wdog_device,
1470         &ave_device
1471 };
1472
1473
1474 /*
1475  * Interrupts: the U300 platforms have two pl190 ARM PrimeCells connected
1476  * together so some interrupts are connected to the first one and some
1477  * to the second one.
1478  */
1479 void __init u300_init_irq(void)
1480 {
1481         u32 mask[2] = {0, 0};
1482         struct clk *clk;
1483         int i;
1484
1485         /* initialize clocking early, we want to clock the INTCON */
1486         u300_clock_init();
1487
1488         /* Clock the interrupt controller */
1489         clk = clk_get_sys("intcon", NULL);
1490         BUG_ON(IS_ERR(clk));
1491         clk_enable(clk);
1492
1493         for (i = 0; i < NR_IRQS; i++)
1494                 set_bit(i, (unsigned long *) &mask[0]);
1495         vic_init((void __iomem *) U300_INTCON0_VBASE, 0, mask[0], mask[0]);
1496         vic_init((void __iomem *) U300_INTCON1_VBASE, 32, mask[1], mask[1]);
1497 }
1498
1499
1500 /*
1501  * U300 platforms peripheral handling
1502  */
1503 struct db_chip {
1504         u16 chipid;
1505         const char *name;
1506 };
1507
1508 /*
1509  * This is a list of the Digital Baseband chips used in the U300 platform.
1510  */
1511 static struct db_chip db_chips[] __initdata = {
1512         {
1513                 .chipid = 0xb800,
1514                 .name = "DB3000",
1515         },
1516         {
1517                 .chipid = 0xc000,
1518                 .name = "DB3100",
1519         },
1520         {
1521                 .chipid = 0xc800,
1522                 .name = "DB3150",
1523         },
1524         {
1525                 .chipid = 0xd800,
1526                 .name = "DB3200",
1527         },
1528         {
1529                 .chipid = 0xe000,
1530                 .name = "DB3250",
1531         },
1532         {
1533                 .chipid = 0xe800,
1534                 .name = "DB3210",
1535         },
1536         {
1537                 .chipid = 0xf000,
1538                 .name = "DB3350 P1x",
1539         },
1540         {
1541                 .chipid = 0xf100,
1542                 .name = "DB3350 P2x",
1543         },
1544         {
1545                 .chipid = 0x0000, /* List terminator */
1546                 .name = NULL,
1547         }
1548 };
1549
1550 static void __init u300_init_check_chip(void)
1551 {
1552
1553         u16 val;
1554         struct db_chip *chip;
1555         const char *chipname;
1556         const char unknown[] = "UNKNOWN";
1557
1558         /* Read out and print chip ID */
1559         val = readw(U300_SYSCON_VBASE + U300_SYSCON_CIDR);
1560         /* This is in funky bigendian order... */
1561         val = (val & 0xFFU) << 8 | (val >> 8);
1562         chip = db_chips;
1563         chipname = unknown;
1564
1565         for ( ; chip->chipid; chip++) {
1566                 if (chip->chipid == (val & 0xFF00U)) {
1567                         chipname = chip->name;
1568                         break;
1569                 }
1570         }
1571         printk(KERN_INFO "Initializing U300 system on %s baseband chip " \
1572                "(chip ID 0x%04x)\n", chipname, val);
1573
1574 #ifdef CONFIG_MACH_U300_BS330
1575         if ((val & 0xFF00U) != 0xd800) {
1576                 printk(KERN_ERR "Platform configured for BS330 " \
1577                        "with DB3200 but %s detected, expect problems!",
1578                        chipname);
1579         }
1580 #endif
1581 #ifdef CONFIG_MACH_U300_BS335
1582         if ((val & 0xFF00U) != 0xf000 && (val & 0xFF00U) != 0xf100) {
1583                 printk(KERN_ERR "Platform configured for BS365 " \
1584                        " with DB3350 but %s detected, expect problems!",
1585                        chipname);
1586         }
1587 #endif
1588 #ifdef CONFIG_MACH_U300_BS365
1589         if ((val & 0xFF00U) != 0xe800) {
1590                 printk(KERN_ERR "Platform configured for BS365 " \
1591                        "with DB3210 but %s detected, expect problems!",
1592                        chipname);
1593         }
1594 #endif
1595
1596
1597 }
1598
1599 /*
1600  * Some devices and their resources require reserved physical memory from
1601  * the end of the available RAM. This function traverses the list of devices
1602  * and assigns actual addresses to these.
1603  */
1604 static void __init u300_assign_physmem(void)
1605 {
1606         unsigned long curr_start = __pa(high_memory);
1607         int i, j;
1608
1609         for (i = 0; i < ARRAY_SIZE(platform_devs); i++) {
1610                 for (j = 0; j < platform_devs[i]->num_resources; j++) {
1611                         struct resource *const res =
1612                           &platform_devs[i]->resource[j];
1613
1614                         if (IORESOURCE_MEM == res->flags &&
1615                                      0 == res->start) {
1616                                 res->start  = curr_start;
1617                                 res->end   += curr_start;
1618                                 curr_start += (res->end - res->start + 1);
1619
1620                                 printk(KERN_INFO "core.c: Mapping RAM " \
1621                                        "%#x-%#x to device %s:%s\n",
1622                                         res->start, res->end,
1623                                        platform_devs[i]->name, res->name);
1624                         }
1625                 }
1626         }
1627 }
1628
1629 void __init u300_init_devices(void)
1630 {
1631         int i;
1632         u16 val;
1633
1634         /* Check what platform we run and print some status information */
1635         u300_init_check_chip();
1636
1637         /* Set system to run at PLL208, max performance, a known state. */
1638         val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
1639         val &= ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK;
1640         writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
1641         /* Wait for the PLL208 to lock if not locked in yet */
1642         while (!(readw(U300_SYSCON_VBASE + U300_SYSCON_CSR) &
1643                  U300_SYSCON_CSR_PLL208_LOCK_IND));
1644         /* Initialize SPI device with some board specifics */
1645         u300_spi_init(&pl022_device);
1646
1647         /* Register the AMBA devices in the AMBA bus abstraction layer */
1648         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
1649                 struct amba_device *d = amba_devs[i];
1650                 amba_device_register(d, &iomem_resource);
1651         }
1652
1653         u300_assign_physmem();
1654
1655         /* Register subdevices on the I2C buses */
1656         u300_i2c_register_board_devices();
1657
1658         /* Register subdevices on the SPI bus */
1659         u300_spi_register_board_devices();
1660
1661         /* Register the platform devices */
1662         platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
1663
1664 #ifndef CONFIG_MACH_U300_SEMI_IS_SHARED
1665         /*
1666          * Enable SEMI self refresh. Self-refresh of the SDRAM is entered when
1667          * both subsystems are requesting this mode.
1668          * If we not share the Acc SDRAM, this is never the case. Therefore
1669          * enable it here from the App side.
1670          */
1671         val = readw(U300_SYSCON_VBASE + U300_SYSCON_SMCR) |
1672                 U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE;
1673         writew(val, U300_SYSCON_VBASE + U300_SYSCON_SMCR);
1674 #endif /* CONFIG_MACH_U300_SEMI_IS_SHARED */
1675 }
1676
1677 static int core_module_init(void)
1678 {
1679         /*
1680          * This needs to be initialized later: it needs the input framework
1681          * to be initialized first.
1682          */
1683         return mmc_init(&mmcsd_device);
1684 }
1685 module_init(core_module_init);