arch/arm/mach-u300/core.c

   1 /*
   2  *
   3  * arch/arm/mach-u300/core.c
   4  *
   5  *
   6  * Copyright (C) 2007-2010 ST-Ericsson SA
   7  * License terms: GNU General Public License (GPL) version 2
   8  * Core platform support, IRQ handling and device definitions.
   9  * Author: Linus Walleij <linus.walleij@stericsson.com>
  10  */
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/spinlock.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/bitops.h>
  16 #include <linux/device.h>
  17 #include <linux/mm.h>
  18 #include <linux/termios.h>
  19 #include <linux/dmaengine.h>
  20 #include <linux/amba/bus.h>
  21 #include <linux/amba/serial.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/gpio.h>
  24 #include <linux/clk.h>
  25 #include <linux/err.h>
  26 #include <linux/mtd/nand.h>
  27 #include <linux/mtd/fsmc.h>
  28 #include <linux/dma-mapping.h>
  29
  30 #include <asm/types.h>
  31 #include <asm/setup.h>
  32 #include <asm/memory.h>
  33 #include <asm/hardware/vic.h>
  34 #include <asm/mach/map.h>
  35 #include <asm/mach/irq.h>
  36
  37 #include <mach/coh901318.h>
  38 #include <mach/hardware.h>
  39 #include <mach/syscon.h>
  40 #include <mach/dma_channels.h>
  41 #include <mach/gpio-u300.h>
  42
  43 #include "clock.h"
  44 #include "mmc.h"
  45 #include "spi.h"
  46 #include "i2c.h"
  47
  48 /*
  49  * Static I/O mappings that are needed for booting the U300 platforms. The
  50  * only things we need are the areas where we find the timer, syscon and
  51  * intcon, since the remaining device drivers will map their own memory
  52  * physical to virtual as the need arise.
  53  */
  54 static struct map_desc u300_io_desc[] __initdata = {
  55         {
  56                 .virtual        = U300_SLOW_PER_VIRT_BASE,
  57                 .pfn            = __phys_to_pfn(U300_SLOW_PER_PHYS_BASE),
  58                 .length         = SZ_64K,
  59                 .type           = MT_DEVICE,
  60         },
  61         {
  62                 .virtual        = U300_AHB_PER_VIRT_BASE,
  63                 .pfn            = __phys_to_pfn(U300_AHB_PER_PHYS_BASE),
  64                 .length         = SZ_32K,
  65                 .type           = MT_DEVICE,
  66         },
  67         {
  68                 .virtual        = U300_FAST_PER_VIRT_BASE,
  69                 .pfn            = __phys_to_pfn(U300_FAST_PER_PHYS_BASE),
  70                 .length         = SZ_32K,
  71                 .type           = MT_DEVICE,
  72         },
  73         {
  74                 .virtual        = 0xffff2000, /* TCM memory */
  75                 .pfn            = __phys_to_pfn(0xffff2000),
  76                 .length         = SZ_16K,
  77                 .type           = MT_DEVICE,
  78         },
  79
  80         /*
  81          * This overlaps with the IRQ vectors etc at 0xffff0000, so these
  82          * may have to be moved to 0x00000000 in order to use the ROM.
  83          */
  84         /*
  85         {
  86                 .virtual        = U300_BOOTROM_VIRT_BASE,
  87                 .pfn            = __phys_to_pfn(U300_BOOTROM_PHYS_BASE),
  88                 .length         = SZ_64K,
  89                 .type           = MT_ROM,
  90         },
  91         */
  92 };
  93
  94 void __init u300_map_io(void)
  95 {
  96         iotable_init(u300_io_desc, ARRAY_SIZE(u300_io_desc));
  97         /* We enable a real big DMA buffer if need be. */
  98         init_consistent_dma_size(SZ_4M);
  99 }
 100
 101 /*
 102  * Declaration of devices found on the U300 board and
 103  * their respective memory locations.
 104  */
 105
 106 static struct amba_pl011_data uart0_plat_data = {
 107 #ifdef CONFIG_COH901318
 108         .dma_filter = coh901318_filter_id,
 109         .dma_rx_param = (void *) U300_DMA_UART0_RX,
 110         .dma_tx_param = (void *) U300_DMA_UART0_TX,
 111 #endif
 112 };
 113
 114 static struct amba_device uart0_device = {
 115         .dev = {
 116                 .coherent_dma_mask = ~0,
 117                 .init_name = "uart0", /* Slow device at 0x3000 offset */
 118                 .platform_data = &uart0_plat_data,
 119         },
 120         .res = {
 121                 .start = U300_UART0_BASE,
 122                 .end   = U300_UART0_BASE + SZ_4K - 1,
 123                 .flags = IORESOURCE_MEM,
 124         },
 125         .irq = { IRQ_U300_UART0, NO_IRQ },
 126 };
 127
 128 /* The U335 have an additional UART1 on the APP CPU */
 129 #ifdef CONFIG_MACH_U300_BS335
 130 static struct amba_pl011_data uart1_plat_data = {
 131 #ifdef CONFIG_COH901318
 132         .dma_filter = coh901318_filter_id,
 133         .dma_rx_param = (void *) U300_DMA_UART1_RX,
 134         .dma_tx_param = (void *) U300_DMA_UART1_TX,
 135 #endif
 136 };
 137
 138 static struct amba_device uart1_device = {
 139         .dev = {
 140                 .coherent_dma_mask = ~0,
 141                 .init_name = "uart1", /* Fast device at 0x7000 offset */
 142                 .platform_data = &uart1_plat_data,
 143         },
 144         .res = {
 145                 .start = U300_UART1_BASE,
 146                 .end   = U300_UART1_BASE + SZ_4K - 1,
 147                 .flags = IORESOURCE_MEM,
 148         },
 149         .irq = { IRQ_U300_UART1, NO_IRQ },
 150 };
 151 #endif
 152
 153 static struct amba_device pl172_device = {
 154         .dev = {
 155                 .init_name = "pl172", /* AHB device at 0x4000 offset */
 156                 .platform_data = NULL,
 157         },
 158         .res = {
 159                 .start = U300_EMIF_CFG_BASE,
 160                 .end   = U300_EMIF_CFG_BASE + SZ_4K - 1,
 161                 .flags = IORESOURCE_MEM,
 162         },
 163 };
 164
 165
 166 /*
 167  * Everything within this next ifdef deals with external devices connected to
 168  * the APP SPI bus.
 169  */
 170 static struct amba_device pl022_device = {
 171         .dev = {
 172                 .coherent_dma_mask = ~0,
 173                 .init_name = "pl022", /* Fast device at 0x6000 offset */
 174         },
 175         .res = {
 176                 .start = U300_SPI_BASE,
 177                 .end   = U300_SPI_BASE + SZ_4K - 1,
 178                 .flags = IORESOURCE_MEM,
 179         },
 180         .irq = {IRQ_U300_SPI, NO_IRQ },
 181         /*
 182          * This device has a DMA channel but the Linux driver does not use
 183          * it currently.
 184          */
 185 };
 186
 187 static struct amba_device mmcsd_device = {
 188         .dev = {
 189                 .init_name = "mmci", /* Fast device at 0x1000 offset */
 190                 .platform_data = NULL, /* Added later */
 191         },
 192         .res = {
 193                 .start = U300_MMCSD_BASE,
 194                 .end   = U300_MMCSD_BASE + SZ_4K - 1,
 195                 .flags = IORESOURCE_MEM,
 196         },
 197         .irq = {IRQ_U300_MMCSD_MCIINTR0, IRQ_U300_MMCSD_MCIINTR1 },
 198         /*
 199          * This device has a DMA channel but the Linux driver does not use
 200          * it currently.
 201          */
 202 };
 203
 204 /*
 205  * The order of device declaration may be important, since some devices
 206  * have dependencies on other devices being initialized first.
 207  */
 208 static struct amba_device *amba_devs[] __initdata = {
 209         &uart0_device,
 210 #ifdef CONFIG_MACH_U300_BS335
 211         &uart1_device,
 212 #endif
 213         &pl022_device,
 214         &pl172_device,
 215         &mmcsd_device,
 216 };
 217
 218 /* Here follows a list of all hw resources that the platform devices
 219  * allocate. Note, clock dependencies are not included
 220  */
 221
 222 static struct resource gpio_resources[] = {
 223         {
 224                 .start = U300_GPIO_BASE,
 225                 .end   = (U300_GPIO_BASE + SZ_4K - 1),
 226                 .flags = IORESOURCE_MEM,
 227         },
 228         {
 229                 .name  = "gpio0",
 230                 .start = IRQ_U300_GPIO_PORT0,
 231                 .end   = IRQ_U300_GPIO_PORT0,
 232                 .flags = IORESOURCE_IRQ,
 233         },
 234         {
 235                 .name  = "gpio1",
 236                 .start = IRQ_U300_GPIO_PORT1,
 237                 .end   = IRQ_U300_GPIO_PORT1,
 238                 .flags = IORESOURCE_IRQ,
 239         },
 240         {
 241                 .name  = "gpio2",
 242                 .start = IRQ_U300_GPIO_PORT2,
 243                 .end   = IRQ_U300_GPIO_PORT2,
 244                 .flags = IORESOURCE_IRQ,
 245         },
 246 #if defined(CONFIG_MACH_U300_BS365) || defined(CONFIG_MACH_U300_BS335)
 247         {
 248                 .name  = "gpio3",
 249                 .start = IRQ_U300_GPIO_PORT3,
 250                 .end   = IRQ_U300_GPIO_PORT3,
 251                 .flags = IORESOURCE_IRQ,
 252         },
 253         {
 254                 .name  = "gpio4",
 255                 .start = IRQ_U300_GPIO_PORT4,
 256                 .end   = IRQ_U300_GPIO_PORT4,
 257                 .flags = IORESOURCE_IRQ,
 258         },
 259 #endif
 260 #ifdef CONFIG_MACH_U300_BS335
 261         {
 262                 .name  = "gpio5",
 263                 .start = IRQ_U300_GPIO_PORT5,
 264                 .end   = IRQ_U300_GPIO_PORT5,
 265                 .flags = IORESOURCE_IRQ,
 266         },
 267         {
 268                 .name  = "gpio6",
 269                 .start = IRQ_U300_GPIO_PORT6,
 270                 .end   = IRQ_U300_GPIO_PORT6,
 271                 .flags = IORESOURCE_IRQ,
 272         },
 273 #endif /* CONFIG_MACH_U300_BS335 */
 274 };
 275
 276 static struct resource keypad_resources[] = {
 277         {
 278                 .start = U300_KEYPAD_BASE,
 279                 .end   = U300_KEYPAD_BASE + SZ_4K - 1,
 280                 .flags = IORESOURCE_MEM,
 281         },
 282         {
 283                 .name  = "coh901461-press",
 284                 .start = IRQ_U300_KEYPAD_KEYBF,
 285                 .end   = IRQ_U300_KEYPAD_KEYBF,
 286                 .flags = IORESOURCE_IRQ,
 287         },
 288         {
 289                 .name  = "coh901461-release",
 290                 .start = IRQ_U300_KEYPAD_KEYBR,
 291                 .end   = IRQ_U300_KEYPAD_KEYBR,
 292                 .flags = IORESOURCE_IRQ,
 293         },
 294 };
 295
 296 static struct resource rtc_resources[] = {
 297         {
 298                 .start = U300_RTC_BASE,
 299                 .end   = U300_RTC_BASE + SZ_4K - 1,
 300                 .flags = IORESOURCE_MEM,
 301         },
 302         {
 303                 .start = IRQ_U300_RTC,
 304                 .end   = IRQ_U300_RTC,
 305                 .flags = IORESOURCE_IRQ,
 306         },
 307 };
 308
 309 /*
 310  * Fsmc does have IRQs: #43 and #44 (NFIF and NFIF2)
 311  * but these are not yet used by the driver.
 312  */
 313 static struct resource fsmc_resources[] = {
 314         {
 315                 .name  = "nand_data",
 316                 .start = U300_NAND_CS0_PHYS_BASE,
 317                 .end   = U300_NAND_CS0_PHYS_BASE + SZ_16K - 1,
 318                 .flags = IORESOURCE_MEM,
 319         },
 320         {
 321                 .name  = "fsmc_regs",
 322                 .start = U300_NAND_IF_PHYS_BASE,
 323                 .end   = U300_NAND_IF_PHYS_BASE + SZ_4K - 1,
 324                 .flags = IORESOURCE_MEM,
 325         },
 326 };
 327
 328 static struct resource i2c0_resources[] = {
 329         {
 330                 .start = U300_I2C0_BASE,
 331                 .end   = U300_I2C0_BASE + SZ_4K - 1,
 332                 .flags = IORESOURCE_MEM,
 333         },
 334         {
 335                 .start = IRQ_U300_I2C0,
 336                 .end   = IRQ_U300_I2C0,
 337                 .flags = IORESOURCE_IRQ,
 338         },
 339 };
 340
 341 static struct resource i2c1_resources[] = {
 342         {
 343                 .start = U300_I2C1_BASE,
 344                 .end   = U300_I2C1_BASE + SZ_4K - 1,
 345                 .flags = IORESOURCE_MEM,
 346         },
 347         {
 348                 .start = IRQ_U300_I2C1,
 349                 .end   = IRQ_U300_I2C1,
 350                 .flags = IORESOURCE_IRQ,
 351         },
 352
 353 };
 354
 355 static struct resource wdog_resources[] = {
 356         {
 357                 .start = U300_WDOG_BASE,
 358                 .end   = U300_WDOG_BASE + SZ_4K - 1,
 359                 .flags = IORESOURCE_MEM,
 360         },
 361         {
 362                 .start = IRQ_U300_WDOG,
 363                 .end   = IRQ_U300_WDOG,
 364                 .flags = IORESOURCE_IRQ,
 365         }
 366 };
 367
 368 /* TODO: These should be protected by suitable #ifdef's */
 369 static struct resource ave_resources[] = {
 370         {
 371                 .name  = "AVE3e I/O Area",
 372                 .start = U300_VIDEOENC_BASE,
 373                 .end   = U300_VIDEOENC_BASE + SZ_512K - 1,
 374                 .flags = IORESOURCE_MEM,
 375         },
 376         {
 377                 .name  = "AVE3e IRQ0",
 378                 .start = IRQ_U300_VIDEO_ENC_0,
 379                 .end   = IRQ_U300_VIDEO_ENC_0,
 380                 .flags = IORESOURCE_IRQ,
 381         },
 382         {
 383                 .name  = "AVE3e IRQ1",
 384                 .start = IRQ_U300_VIDEO_ENC_1,
 385                 .end   = IRQ_U300_VIDEO_ENC_1,
 386                 .flags = IORESOURCE_IRQ,
 387         },
 388         {
 389                 .name  = "AVE3e Physmem Area",
 390                 .start = 0, /* 0 will be remapped to reserved memory */
 391                 .end   = SZ_1M - 1,
 392                 .flags = IORESOURCE_MEM,
 393         },
 394         /*
 395          * The AVE3e requires two regions of 256MB that it considers
 396          * "invisible". The hardware will not be able to access these
 397          * addresses, so they should never point to system RAM.
 398          */
 399         {
 400                 .name  = "AVE3e Reserved 0",
 401                 .start = 0xd0000000,
 402                 .end   = 0xd0000000 + SZ_256M - 1,
 403                 .flags = IORESOURCE_MEM,
 404         },
 405         {
 406                 .name  = "AVE3e Reserved 1",
 407                 .start = 0xe0000000,
 408                 .end   = 0xe0000000 + SZ_256M - 1,
 409                 .flags = IORESOURCE_MEM,
 410         },
 411 };
 412
 413 static struct resource dma_resource[] = {
 414         {
 415                 .start = U300_DMAC_BASE,
 416                 .end = U300_DMAC_BASE + PAGE_SIZE - 1,
 417                 .flags =  IORESOURCE_MEM,
 418         },
 419         {
 420                 .start = IRQ_U300_DMA,
 421                 .end = IRQ_U300_DMA,
 422                 .flags =  IORESOURCE_IRQ,
 423         }
 424 };
 425
 426 #ifdef CONFIG_MACH_U300_BS335
 427 /* points out all dma slave channels.
 428  * Syntax is [A1, B1, A2, B2, .... ,-1,-1]
 429  * Select all channels from A to B, end of list is marked with -1,-1
 430  */
 431 static int dma_slave_channels[] = {
 432         U300_DMA_MSL_TX_0, U300_DMA_SPI_RX,
 433         U300_DMA_UART1_TX, U300_DMA_UART1_RX, -1, -1};
 434
 435 /* points out all dma memcpy channels. */
 436 static int dma_memcpy_channels[] = {
 437         U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_8, -1, -1};
 438
 439 #else /* CONFIG_MACH_U300_BS335 */
 440
 441 static int dma_slave_channels[] = {U300_DMA_MSL_TX_0, U300_DMA_SPI_RX, -1, -1};
 442 static int dma_memcpy_channels[] = {
 443         U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_10, -1, -1};
 444
 445 #endif
 446
 447 /** register dma for memory access
 448  *
 449  * active  1 means dma intends to access memory
 450  *         0 means dma wont access memory
 451  */
 452 static void coh901318_access_memory_state(struct device *dev, bool active)
 453 {
 454 }
 455
 456 #define flags_memcpy_config (COH901318_CX_CFG_CH_DISABLE | \
 457                         COH901318_CX_CFG_RM_MEMORY_TO_MEMORY | \
 458                         COH901318_CX_CFG_LCR_DISABLE | \
 459                         COH901318_CX_CFG_TC_IRQ_ENABLE | \
 460                         COH901318_CX_CFG_BE_IRQ_ENABLE)
 461 #define flags_memcpy_lli_chained (COH901318_CX_CTRL_TC_ENABLE | \
 462                         COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
 463                         COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
 464                         COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
 465                         COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
 466                         COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
 467                         COH901318_CX_CTRL_MASTER_MODE_M1RW | \
 468                         COH901318_CX_CTRL_TCP_DISABLE | \
 469                         COH901318_CX_CTRL_TC_IRQ_DISABLE | \
 470                         COH901318_CX_CTRL_HSP_DISABLE | \
 471                         COH901318_CX_CTRL_HSS_DISABLE | \
 472                         COH901318_CX_CTRL_DDMA_LEGACY | \
 473                         COH901318_CX_CTRL_PRDD_SOURCE)
 474 #define flags_memcpy_lli (COH901318_CX_CTRL_TC_ENABLE | \
 475                         COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
 476                         COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
 477                         COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
 478                         COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
 479                         COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
 480                         COH901318_CX_CTRL_MASTER_MODE_M1RW | \
 481                         COH901318_CX_CTRL_TCP_DISABLE | \
 482                         COH901318_CX_CTRL_TC_IRQ_DISABLE | \
 483                         COH901318_CX_CTRL_HSP_DISABLE | \
 484                         COH901318_CX_CTRL_HSS_DISABLE | \
 485                         COH901318_CX_CTRL_DDMA_LEGACY | \
 486                         COH901318_CX_CTRL_PRDD_SOURCE)
 487 #define flags_memcpy_lli_last (COH901318_CX_CTRL_TC_ENABLE | \
 488                         COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
 489                         COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
 490                         COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
 491                         COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
 492                         COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
 493                         COH901318_CX_CTRL_MASTER_MODE_M1RW | \
 494                         COH901318_CX_CTRL_TCP_DISABLE | \
 495                         COH901318_CX_CTRL_TC_IRQ_ENABLE | \
 496                         COH901318_CX_CTRL_HSP_DISABLE | \
 497                         COH901318_CX_CTRL_HSS_DISABLE | \
 498                         COH901318_CX_CTRL_DDMA_LEGACY | \
 499                         COH901318_CX_CTRL_PRDD_SOURCE)
 500
 501 const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
 502         {
 503                 .number = U300_DMA_MSL_TX_0,
 504                 .name = "MSL TX 0",
 505                 .priority_high = 0,
 506                 .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x20,
 507         },
 508         {
 509                 .number = U300_DMA_MSL_TX_1,
 510                 .name = "MSL TX 1",
 511                 .priority_high = 0,
 512                 .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x20,
 513                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 514                                 COH901318_CX_CFG_LCR_DISABLE |
 515                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 516                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 517                 .param.ctrl_lli_chained = 0 |
 518                                 COH901318_CX_CTRL_TC_ENABLE |
 519                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 520                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 521                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 522                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 523                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 524                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 525                                 COH901318_CX_CTRL_TCP_DISABLE |
 526                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 527                                 COH901318_CX_CTRL_HSP_ENABLE |
 528                                 COH901318_CX_CTRL_HSS_DISABLE |
 529                                 COH901318_CX_CTRL_DDMA_LEGACY |
 530                                 COH901318_CX_CTRL_PRDD_SOURCE,
 531                 .param.ctrl_lli = 0 |
 532                                 COH901318_CX_CTRL_TC_ENABLE |
 533                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 534                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 535                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 536                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 537                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 538                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 539                                 COH901318_CX_CTRL_TCP_ENABLE |
 540                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 541                                 COH901318_CX_CTRL_HSP_ENABLE |
 542                                 COH901318_CX_CTRL_HSS_DISABLE |
 543                                 COH901318_CX_CTRL_DDMA_LEGACY |
 544                                 COH901318_CX_CTRL_PRDD_SOURCE,
 545                 .param.ctrl_lli_last = 0 |
 546                                 COH901318_CX_CTRL_TC_ENABLE |
 547                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 548                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 549                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 550                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 551                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 552                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 553                                 COH901318_CX_CTRL_TCP_ENABLE |
 554                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 555                                 COH901318_CX_CTRL_HSP_ENABLE |
 556                                 COH901318_CX_CTRL_HSS_DISABLE |
 557                                 COH901318_CX_CTRL_DDMA_LEGACY |
 558                                 COH901318_CX_CTRL_PRDD_SOURCE,
 559         },
 560         {
 561                 .number = U300_DMA_MSL_TX_2,
 562                 .name = "MSL TX 2",
 563                 .priority_high = 0,
 564                 .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x20,
 565                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 566                                 COH901318_CX_CFG_LCR_DISABLE |
 567                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 568                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 569                 .param.ctrl_lli_chained = 0 |
 570                                 COH901318_CX_CTRL_TC_ENABLE |
 571                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 572                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 573                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 574                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 575                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 576                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 577                                 COH901318_CX_CTRL_TCP_DISABLE |
 578                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 579                                 COH901318_CX_CTRL_HSP_ENABLE |
 580                                 COH901318_CX_CTRL_HSS_DISABLE |
 581                                 COH901318_CX_CTRL_DDMA_LEGACY |
 582                                 COH901318_CX_CTRL_PRDD_SOURCE,
 583                 .param.ctrl_lli = 0 |
 584                                 COH901318_CX_CTRL_TC_ENABLE |
 585                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 586                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 587                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 588                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 589                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 590                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 591                                 COH901318_CX_CTRL_TCP_ENABLE |
 592                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 593                                 COH901318_CX_CTRL_HSP_ENABLE |
 594                                 COH901318_CX_CTRL_HSS_DISABLE |
 595                                 COH901318_CX_CTRL_DDMA_LEGACY |
 596                                 COH901318_CX_CTRL_PRDD_SOURCE,
 597                 .param.ctrl_lli_last = 0 |
 598                                 COH901318_CX_CTRL_TC_ENABLE |
 599                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 600                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 601                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 602                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 603                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 604                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 605                                 COH901318_CX_CTRL_TCP_ENABLE |
 606                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 607                                 COH901318_CX_CTRL_HSP_ENABLE |
 608                                 COH901318_CX_CTRL_HSS_DISABLE |
 609                                 COH901318_CX_CTRL_DDMA_LEGACY |
 610                                 COH901318_CX_CTRL_PRDD_SOURCE,
 611                 .desc_nbr_max = 10,
 612         },
 613         {
 614                 .number = U300_DMA_MSL_TX_3,
 615                 .name = "MSL TX 3",
 616                 .priority_high = 0,
 617                 .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x20,
 618                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 619                                 COH901318_CX_CFG_LCR_DISABLE |
 620                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 621                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 622                 .param.ctrl_lli_chained = 0 |
 623                                 COH901318_CX_CTRL_TC_ENABLE |
 624                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 625                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 626                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 627                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 628                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 629                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 630                                 COH901318_CX_CTRL_TCP_DISABLE |
 631                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 632                                 COH901318_CX_CTRL_HSP_ENABLE |
 633                                 COH901318_CX_CTRL_HSS_DISABLE |
 634                                 COH901318_CX_CTRL_DDMA_LEGACY |
 635                                 COH901318_CX_CTRL_PRDD_SOURCE,
 636                 .param.ctrl_lli = 0 |
 637                                 COH901318_CX_CTRL_TC_ENABLE |
 638                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 639                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 640                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 641                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 642                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 643                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 644                                 COH901318_CX_CTRL_TCP_ENABLE |
 645                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 646                                 COH901318_CX_CTRL_HSP_ENABLE |
 647                                 COH901318_CX_CTRL_HSS_DISABLE |
 648                                 COH901318_CX_CTRL_DDMA_LEGACY |
 649                                 COH901318_CX_CTRL_PRDD_SOURCE,
 650                 .param.ctrl_lli_last = 0 |
 651                                 COH901318_CX_CTRL_TC_ENABLE |
 652                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 653                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 654                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 655                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 656                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 657                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 658                                 COH901318_CX_CTRL_TCP_ENABLE |
 659                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 660                                 COH901318_CX_CTRL_HSP_ENABLE |
 661                                 COH901318_CX_CTRL_HSS_DISABLE |
 662                                 COH901318_CX_CTRL_DDMA_LEGACY |
 663                                 COH901318_CX_CTRL_PRDD_SOURCE,
 664         },
 665         {
 666                 .number = U300_DMA_MSL_TX_4,
 667                 .name = "MSL TX 4",
 668                 .priority_high = 0,
 669                 .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x20,
 670                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 671                                 COH901318_CX_CFG_LCR_DISABLE |
 672                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 673                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 674                 .param.ctrl_lli_chained = 0 |
 675                                 COH901318_CX_CTRL_TC_ENABLE |
 676                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 677                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 678                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 679                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 680                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 681                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 682                                 COH901318_CX_CTRL_TCP_DISABLE |
 683                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 684                                 COH901318_CX_CTRL_HSP_ENABLE |
 685                                 COH901318_CX_CTRL_HSS_DISABLE |
 686                                 COH901318_CX_CTRL_DDMA_LEGACY |
 687                                 COH901318_CX_CTRL_PRDD_SOURCE,
 688                 .param.ctrl_lli = 0 |
 689                                 COH901318_CX_CTRL_TC_ENABLE |
 690                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 691                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 692                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 693                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 694                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 695                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 696                                 COH901318_CX_CTRL_TCP_ENABLE |
 697                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 698                                 COH901318_CX_CTRL_HSP_ENABLE |
 699                                 COH901318_CX_CTRL_HSS_DISABLE |
 700                                 COH901318_CX_CTRL_DDMA_LEGACY |
 701                                 COH901318_CX_CTRL_PRDD_SOURCE,
 702                 .param.ctrl_lli_last = 0 |
 703                                 COH901318_CX_CTRL_TC_ENABLE |
 704                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 705                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 706                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
 707                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 708                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
 709                                 COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
 710                                 COH901318_CX_CTRL_TCP_ENABLE |
 711                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 712                                 COH901318_CX_CTRL_HSP_ENABLE |
 713                                 COH901318_CX_CTRL_HSS_DISABLE |
 714                                 COH901318_CX_CTRL_DDMA_LEGACY |
 715                                 COH901318_CX_CTRL_PRDD_SOURCE,
 716         },
 717         {
 718                 .number = U300_DMA_MSL_TX_5,
 719                 .name = "MSL TX 5",
 720                 .priority_high = 0,
 721                 .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x20,
 722         },
 723         {
 724                 .number = U300_DMA_MSL_TX_6,
 725                 .name = "MSL TX 6",
 726                 .priority_high = 0,
 727                 .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x20,
 728         },
 729         {
 730                 .number = U300_DMA_MSL_RX_0,
 731                 .name = "MSL RX 0",
 732                 .priority_high = 0,
 733                 .dev_addr = U300_MSL_BASE + 0 * 0x40 + 0x220,
 734         },
 735         {
 736                 .number = U300_DMA_MSL_RX_1,
 737                 .name = "MSL RX 1",
 738                 .priority_high = 0,
 739                 .dev_addr = U300_MSL_BASE + 1 * 0x40 + 0x220,
 740                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 741                                 COH901318_CX_CFG_LCR_DISABLE |
 742                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 743                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 744                 .param.ctrl_lli_chained = 0 |
 745                                 COH901318_CX_CTRL_TC_ENABLE |
 746                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 747                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 748                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 749                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 750                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 751                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 752                                 COH901318_CX_CTRL_TCP_DISABLE |
 753                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 754                                 COH901318_CX_CTRL_HSP_ENABLE |
 755                                 COH901318_CX_CTRL_HSS_DISABLE |
 756                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 757                                 COH901318_CX_CTRL_PRDD_DEST,
 758                 .param.ctrl_lli = 0,
 759                 .param.ctrl_lli_last = 0 |
 760                                 COH901318_CX_CTRL_TC_ENABLE |
 761                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 762                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 763                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 764                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 765                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 766                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 767                                 COH901318_CX_CTRL_TCP_DISABLE |
 768                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 769                                 COH901318_CX_CTRL_HSP_ENABLE |
 770                                 COH901318_CX_CTRL_HSS_DISABLE |
 771                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 772                                 COH901318_CX_CTRL_PRDD_DEST,
 773         },
 774         {
 775                 .number = U300_DMA_MSL_RX_2,
 776                 .name = "MSL RX 2",
 777                 .priority_high = 0,
 778                 .dev_addr = U300_MSL_BASE + 2 * 0x40 + 0x220,
 779                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 780                                 COH901318_CX_CFG_LCR_DISABLE |
 781                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 782                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 783                 .param.ctrl_lli_chained = 0 |
 784                                 COH901318_CX_CTRL_TC_ENABLE |
 785                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 786                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 787                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 788                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 789                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 790                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 791                                 COH901318_CX_CTRL_TCP_DISABLE |
 792                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 793                                 COH901318_CX_CTRL_HSP_ENABLE |
 794                                 COH901318_CX_CTRL_HSS_DISABLE |
 795                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 796                                 COH901318_CX_CTRL_PRDD_DEST,
 797                 .param.ctrl_lli = 0 |
 798                                 COH901318_CX_CTRL_TC_ENABLE |
 799                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 800                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 801                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 802                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 803                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 804                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 805                                 COH901318_CX_CTRL_TCP_DISABLE |
 806                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 807                                 COH901318_CX_CTRL_HSP_ENABLE |
 808                                 COH901318_CX_CTRL_HSS_DISABLE |
 809                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 810                                 COH901318_CX_CTRL_PRDD_DEST,
 811                 .param.ctrl_lli_last = 0 |
 812                                 COH901318_CX_CTRL_TC_ENABLE |
 813                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 814                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 815                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 816                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 817                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 818                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 819                                 COH901318_CX_CTRL_TCP_DISABLE |
 820                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 821                                 COH901318_CX_CTRL_HSP_ENABLE |
 822                                 COH901318_CX_CTRL_HSS_DISABLE |
 823                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 824                                 COH901318_CX_CTRL_PRDD_DEST,
 825         },
 826         {
 827                 .number = U300_DMA_MSL_RX_3,
 828                 .name = "MSL RX 3",
 829                 .priority_high = 0,
 830                 .dev_addr = U300_MSL_BASE + 3 * 0x40 + 0x220,
 831                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 832                                 COH901318_CX_CFG_LCR_DISABLE |
 833                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 834                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 835                 .param.ctrl_lli_chained = 0 |
 836                                 COH901318_CX_CTRL_TC_ENABLE |
 837                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 838                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 839                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 840                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 841                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 842                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 843                                 COH901318_CX_CTRL_TCP_DISABLE |
 844                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 845                                 COH901318_CX_CTRL_HSP_ENABLE |
 846                                 COH901318_CX_CTRL_HSS_DISABLE |
 847                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 848                                 COH901318_CX_CTRL_PRDD_DEST,
 849                 .param.ctrl_lli = 0 |
 850                                 COH901318_CX_CTRL_TC_ENABLE |
 851                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 852                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 853                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 854                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 855                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 856                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 857                                 COH901318_CX_CTRL_TCP_DISABLE |
 858                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 859                                 COH901318_CX_CTRL_HSP_ENABLE |
 860                                 COH901318_CX_CTRL_HSS_DISABLE |
 861                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 862                                 COH901318_CX_CTRL_PRDD_DEST,
 863                 .param.ctrl_lli_last = 0 |
 864                                 COH901318_CX_CTRL_TC_ENABLE |
 865                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 866                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 867                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 868                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 869                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 870                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 871                                 COH901318_CX_CTRL_TCP_DISABLE |
 872                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 873                                 COH901318_CX_CTRL_HSP_ENABLE |
 874                                 COH901318_CX_CTRL_HSS_DISABLE |
 875                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 876                                 COH901318_CX_CTRL_PRDD_DEST,
 877         },
 878         {
 879                 .number = U300_DMA_MSL_RX_4,
 880                 .name = "MSL RX 4",
 881                 .priority_high = 0,
 882                 .dev_addr = U300_MSL_BASE + 4 * 0x40 + 0x220,
 883                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 884                                 COH901318_CX_CFG_LCR_DISABLE |
 885                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 886                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 887                 .param.ctrl_lli_chained = 0 |
 888                                 COH901318_CX_CTRL_TC_ENABLE |
 889                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 890                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 891                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 892                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 893                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 894                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 895                                 COH901318_CX_CTRL_TCP_DISABLE |
 896                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 897                                 COH901318_CX_CTRL_HSP_ENABLE |
 898                                 COH901318_CX_CTRL_HSS_DISABLE |
 899                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 900                                 COH901318_CX_CTRL_PRDD_DEST,
 901                 .param.ctrl_lli = 0 |
 902                                 COH901318_CX_CTRL_TC_ENABLE |
 903                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 904                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 905                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 906                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 907                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 908                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 909                                 COH901318_CX_CTRL_TCP_DISABLE |
 910                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 911                                 COH901318_CX_CTRL_HSP_ENABLE |
 912                                 COH901318_CX_CTRL_HSS_DISABLE |
 913                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 914                                 COH901318_CX_CTRL_PRDD_DEST,
 915                 .param.ctrl_lli_last = 0 |
 916                                 COH901318_CX_CTRL_TC_ENABLE |
 917                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 918                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 919                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 920                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 921                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 922                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 923                                 COH901318_CX_CTRL_TCP_DISABLE |
 924                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 925                                 COH901318_CX_CTRL_HSP_ENABLE |
 926                                 COH901318_CX_CTRL_HSS_DISABLE |
 927                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 928                                 COH901318_CX_CTRL_PRDD_DEST,
 929         },
 930         {
 931                 .number = U300_DMA_MSL_RX_5,
 932                 .name = "MSL RX 5",
 933                 .priority_high = 0,
 934                 .dev_addr = U300_MSL_BASE + 5 * 0x40 + 0x220,
 935                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 936                                 COH901318_CX_CFG_LCR_DISABLE |
 937                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
 938                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
 939                 .param.ctrl_lli_chained = 0 |
 940                                 COH901318_CX_CTRL_TC_ENABLE |
 941                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 942                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 943                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 944                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 945                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 946                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 947                                 COH901318_CX_CTRL_TCP_DISABLE |
 948                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
 949                                 COH901318_CX_CTRL_HSP_ENABLE |
 950                                 COH901318_CX_CTRL_HSS_DISABLE |
 951                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 952                                 COH901318_CX_CTRL_PRDD_DEST,
 953                 .param.ctrl_lli = 0 |
 954                                 COH901318_CX_CTRL_TC_ENABLE |
 955                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 956                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 957                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 958                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 959                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 960                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 961                                 COH901318_CX_CTRL_TCP_DISABLE |
 962                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 963                                 COH901318_CX_CTRL_HSP_ENABLE |
 964                                 COH901318_CX_CTRL_HSS_DISABLE |
 965                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 966                                 COH901318_CX_CTRL_PRDD_DEST,
 967                 .param.ctrl_lli_last = 0 |
 968                                 COH901318_CX_CTRL_TC_ENABLE |
 969                                 COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
 970                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
 971                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
 972                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 973                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
 974                                 COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
 975                                 COH901318_CX_CTRL_TCP_DISABLE |
 976                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
 977                                 COH901318_CX_CTRL_HSP_ENABLE |
 978                                 COH901318_CX_CTRL_HSS_DISABLE |
 979                                 COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
 980                                 COH901318_CX_CTRL_PRDD_DEST,
 981         },
 982         {
 983                 .number = U300_DMA_MSL_RX_6,
 984                 .name = "MSL RX 6",
 985                 .priority_high = 0,
 986                 .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x220,
 987         },
 988         /*
 989          * Don't set up device address, burst count or size of src
 990          * or dst bus for this peripheral - handled by PrimeCell
 991          * DMA extension.
 992          */
 993         {
 994                 .number = U300_DMA_MMCSD_RX_TX,
 995                 .name = "MMCSD RX TX",
 996                 .priority_high = 0,
 997                 .param.config = COH901318_CX_CFG_CH_DISABLE |
 998                                 COH901318_CX_CFG_LCR_DISABLE |
 999                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1000                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1001                 .param.ctrl_lli_chained = 0 |
1002                                 COH901318_CX_CTRL_TC_ENABLE |
1003                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1004                                 COH901318_CX_CTRL_TCP_ENABLE |
1005                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1006                                 COH901318_CX_CTRL_HSP_ENABLE |
1007                                 COH901318_CX_CTRL_HSS_DISABLE |
1008                                 COH901318_CX_CTRL_DDMA_LEGACY,
1009                 .param.ctrl_lli = 0 |
1010                                 COH901318_CX_CTRL_TC_ENABLE |
1011                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1012                                 COH901318_CX_CTRL_TCP_ENABLE |
1013                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1014                                 COH901318_CX_CTRL_HSP_ENABLE |
1015                                 COH901318_CX_CTRL_HSS_DISABLE |
1016                                 COH901318_CX_CTRL_DDMA_LEGACY,
1017                 .param.ctrl_lli_last = 0 |
1018                                 COH901318_CX_CTRL_TC_ENABLE |
1019                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1020                                 COH901318_CX_CTRL_TCP_DISABLE |
1021                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1022                                 COH901318_CX_CTRL_HSP_ENABLE |
1023                                 COH901318_CX_CTRL_HSS_DISABLE |
1024                                 COH901318_CX_CTRL_DDMA_LEGACY,
1025
1026         },
1027         {
1028                 .number = U300_DMA_MSPRO_TX,
1029                 .name = "MSPRO TX",
1030                 .priority_high = 0,
1031         },
1032         {
1033                 .number = U300_DMA_MSPRO_RX,
1034                 .name = "MSPRO RX",
1035                 .priority_high = 0,
1036         },
1037         /*
1038          * Don't set up device address, burst count or size of src
1039          * or dst bus for this peripheral - handled by PrimeCell
1040          * DMA extension.
1041          */
1042         {
1043                 .number = U300_DMA_UART0_TX,
1044                 .name = "UART0 TX",
1045                 .priority_high = 0,
1046                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1047                                 COH901318_CX_CFG_LCR_DISABLE |
1048                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1049                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1050                 .param.ctrl_lli_chained = 0 |
1051                                 COH901318_CX_CTRL_TC_ENABLE |
1052                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1053                                 COH901318_CX_CTRL_TCP_ENABLE |
1054                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1055                                 COH901318_CX_CTRL_HSP_ENABLE |
1056                                 COH901318_CX_CTRL_HSS_DISABLE |
1057                                 COH901318_CX_CTRL_DDMA_LEGACY,
1058                 .param.ctrl_lli = 0 |
1059                                 COH901318_CX_CTRL_TC_ENABLE |
1060                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1061                                 COH901318_CX_CTRL_TCP_ENABLE |
1062                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1063                                 COH901318_CX_CTRL_HSP_ENABLE |
1064                                 COH901318_CX_CTRL_HSS_DISABLE |
1065                                 COH901318_CX_CTRL_DDMA_LEGACY,
1066                 .param.ctrl_lli_last = 0 |
1067                                 COH901318_CX_CTRL_TC_ENABLE |
1068                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1069                                 COH901318_CX_CTRL_TCP_ENABLE |
1070                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1071                                 COH901318_CX_CTRL_HSP_ENABLE |
1072                                 COH901318_CX_CTRL_HSS_DISABLE |
1073                                 COH901318_CX_CTRL_DDMA_LEGACY,
1074         },
1075         {
1076                 .number = U300_DMA_UART0_RX,
1077                 .name = "UART0 RX",
1078                 .priority_high = 0,
1079                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1080                                 COH901318_CX_CFG_LCR_DISABLE |
1081                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1082                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1083                 .param.ctrl_lli_chained = 0 |
1084                                 COH901318_CX_CTRL_TC_ENABLE |
1085                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1086                                 COH901318_CX_CTRL_TCP_ENABLE |
1087                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1088                                 COH901318_CX_CTRL_HSP_ENABLE |
1089                                 COH901318_CX_CTRL_HSS_DISABLE |
1090                                 COH901318_CX_CTRL_DDMA_LEGACY,
1091                 .param.ctrl_lli = 0 |
1092                                 COH901318_CX_CTRL_TC_ENABLE |
1093                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1094                                 COH901318_CX_CTRL_TCP_ENABLE |
1095                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1096                                 COH901318_CX_CTRL_HSP_ENABLE |
1097                                 COH901318_CX_CTRL_HSS_DISABLE |
1098                                 COH901318_CX_CTRL_DDMA_LEGACY,
1099                 .param.ctrl_lli_last = 0 |
1100                                 COH901318_CX_CTRL_TC_ENABLE |
1101                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1102                                 COH901318_CX_CTRL_TCP_ENABLE |
1103                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1104                                 COH901318_CX_CTRL_HSP_ENABLE |
1105                                 COH901318_CX_CTRL_HSS_DISABLE |
1106                                 COH901318_CX_CTRL_DDMA_LEGACY,
1107         },
1108         {
1109                 .number = U300_DMA_APEX_TX,
1110                 .name = "APEX TX",
1111                 .priority_high = 0,
1112         },
1113         {
1114                 .number = U300_DMA_APEX_RX,
1115                 .name = "APEX RX",
1116                 .priority_high = 0,
1117         },
1118         {
1119                 .number = U300_DMA_PCM_I2S0_TX,
1120                 .name = "PCM I2S0 TX",
1121                 .priority_high = 1,
1122                 .dev_addr = U300_PCM_I2S0_BASE + 0x14,
1123                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1124                                 COH901318_CX_CFG_LCR_DISABLE |
1125                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1126                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1127                 .param.ctrl_lli_chained = 0 |
1128                                 COH901318_CX_CTRL_TC_ENABLE |
1129                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1130                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1131                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1132                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1133                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1134                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1135                                 COH901318_CX_CTRL_TCP_DISABLE |
1136                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1137                                 COH901318_CX_CTRL_HSP_ENABLE |
1138                                 COH901318_CX_CTRL_HSS_DISABLE |
1139                                 COH901318_CX_CTRL_DDMA_LEGACY |
1140                                 COH901318_CX_CTRL_PRDD_SOURCE,
1141                 .param.ctrl_lli = 0 |
1142                                 COH901318_CX_CTRL_TC_ENABLE |
1143                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1144                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1145                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1146                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1147                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1148                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1149                                 COH901318_CX_CTRL_TCP_ENABLE |
1150                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1151                                 COH901318_CX_CTRL_HSP_ENABLE |
1152                                 COH901318_CX_CTRL_HSS_DISABLE |
1153                                 COH901318_CX_CTRL_DDMA_LEGACY |
1154                                 COH901318_CX_CTRL_PRDD_SOURCE,
1155                 .param.ctrl_lli_last = 0 |
1156                                 COH901318_CX_CTRL_TC_ENABLE |
1157                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1158                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1159                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1160                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1161                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1162                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1163                                 COH901318_CX_CTRL_TCP_ENABLE |
1164                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1165                                 COH901318_CX_CTRL_HSP_ENABLE |
1166                                 COH901318_CX_CTRL_HSS_DISABLE |
1167                                 COH901318_CX_CTRL_DDMA_LEGACY |
1168                                 COH901318_CX_CTRL_PRDD_SOURCE,
1169         },
1170         {
1171                 .number = U300_DMA_PCM_I2S0_RX,
1172                 .name = "PCM I2S0 RX",
1173                 .priority_high = 1,
1174                 .dev_addr = U300_PCM_I2S0_BASE + 0x10,
1175                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1176                                 COH901318_CX_CFG_LCR_DISABLE |
1177                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1178                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1179                 .param.ctrl_lli_chained = 0 |
1180                                 COH901318_CX_CTRL_TC_ENABLE |
1181                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1182                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1183                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1184                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1185                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1186                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1187                                 COH901318_CX_CTRL_TCP_DISABLE |
1188                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1189                                 COH901318_CX_CTRL_HSP_ENABLE |
1190                                 COH901318_CX_CTRL_HSS_DISABLE |
1191                                 COH901318_CX_CTRL_DDMA_LEGACY |
1192                                 COH901318_CX_CTRL_PRDD_DEST,
1193                 .param.ctrl_lli = 0 |
1194                                 COH901318_CX_CTRL_TC_ENABLE |
1195                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1196                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1197                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1198                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1199                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1200                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1201                                 COH901318_CX_CTRL_TCP_ENABLE |
1202                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1203                                 COH901318_CX_CTRL_HSP_ENABLE |
1204                                 COH901318_CX_CTRL_HSS_DISABLE |
1205                                 COH901318_CX_CTRL_DDMA_LEGACY |
1206                                 COH901318_CX_CTRL_PRDD_DEST,
1207                 .param.ctrl_lli_last = 0 |
1208                                 COH901318_CX_CTRL_TC_ENABLE |
1209                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1210                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1211                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1212                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1213                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1214                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1215                                 COH901318_CX_CTRL_TCP_ENABLE |
1216                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1217                                 COH901318_CX_CTRL_HSP_ENABLE |
1218                                 COH901318_CX_CTRL_HSS_DISABLE |
1219                                 COH901318_CX_CTRL_DDMA_LEGACY |
1220                                 COH901318_CX_CTRL_PRDD_DEST,
1221         },
1222         {
1223                 .number = U300_DMA_PCM_I2S1_TX,
1224                 .name = "PCM I2S1 TX",
1225                 .priority_high = 1,
1226                 .dev_addr =  U300_PCM_I2S1_BASE + 0x14,
1227                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1228                                 COH901318_CX_CFG_LCR_DISABLE |
1229                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1230                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1231                 .param.ctrl_lli_chained = 0 |
1232                                 COH901318_CX_CTRL_TC_ENABLE |
1233                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1234                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1235                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1236                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1237                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1238                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1239                                 COH901318_CX_CTRL_TCP_DISABLE |
1240                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1241                                 COH901318_CX_CTRL_HSP_ENABLE |
1242                                 COH901318_CX_CTRL_HSS_DISABLE |
1243                                 COH901318_CX_CTRL_DDMA_LEGACY |
1244                                 COH901318_CX_CTRL_PRDD_SOURCE,
1245                 .param.ctrl_lli = 0 |
1246                                 COH901318_CX_CTRL_TC_ENABLE |
1247                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1248                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1249                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1250                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1251                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1252                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1253                                 COH901318_CX_CTRL_TCP_ENABLE |
1254                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1255                                 COH901318_CX_CTRL_HSP_ENABLE |
1256                                 COH901318_CX_CTRL_HSS_DISABLE |
1257                                 COH901318_CX_CTRL_DDMA_LEGACY |
1258                                 COH901318_CX_CTRL_PRDD_SOURCE,
1259                 .param.ctrl_lli_last = 0 |
1260                                 COH901318_CX_CTRL_TC_ENABLE |
1261                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1262                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1263                                 COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
1264                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1265                                 COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
1266                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1267                                 COH901318_CX_CTRL_TCP_ENABLE |
1268                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1269                                 COH901318_CX_CTRL_HSP_ENABLE |
1270                                 COH901318_CX_CTRL_HSS_DISABLE |
1271                                 COH901318_CX_CTRL_DDMA_LEGACY |
1272                                 COH901318_CX_CTRL_PRDD_SOURCE,
1273         },
1274         {
1275                 .number = U300_DMA_PCM_I2S1_RX,
1276                 .name = "PCM I2S1 RX",
1277                 .priority_high = 1,
1278                 .dev_addr = U300_PCM_I2S1_BASE + 0x10,
1279                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1280                                 COH901318_CX_CFG_LCR_DISABLE |
1281                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1282                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1283                 .param.ctrl_lli_chained = 0 |
1284                                 COH901318_CX_CTRL_TC_ENABLE |
1285                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1286                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1287                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1288                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1289                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1290                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1291                                 COH901318_CX_CTRL_TCP_DISABLE |
1292                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1293                                 COH901318_CX_CTRL_HSP_ENABLE |
1294                                 COH901318_CX_CTRL_HSS_DISABLE |
1295                                 COH901318_CX_CTRL_DDMA_LEGACY |
1296                                 COH901318_CX_CTRL_PRDD_DEST,
1297                 .param.ctrl_lli = 0 |
1298                                 COH901318_CX_CTRL_TC_ENABLE |
1299                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1300                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1301                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1302                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1303                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1304                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1305                                 COH901318_CX_CTRL_TCP_ENABLE |
1306                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1307                                 COH901318_CX_CTRL_HSP_ENABLE |
1308                                 COH901318_CX_CTRL_HSS_DISABLE |
1309                                 COH901318_CX_CTRL_DDMA_LEGACY |
1310                                 COH901318_CX_CTRL_PRDD_DEST,
1311                 .param.ctrl_lli_last = 0 |
1312                                 COH901318_CX_CTRL_TC_ENABLE |
1313                                 COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
1314                                 COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
1315                                 COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
1316                                 COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
1317                                 COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
1318                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1319                                 COH901318_CX_CTRL_TCP_ENABLE |
1320                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1321                                 COH901318_CX_CTRL_HSP_ENABLE |
1322                                 COH901318_CX_CTRL_HSS_DISABLE |
1323                                 COH901318_CX_CTRL_DDMA_LEGACY |
1324                                 COH901318_CX_CTRL_PRDD_DEST,
1325         },
1326         {
1327                 .number = U300_DMA_XGAM_CDI,
1328                 .name = "XGAM CDI",
1329                 .priority_high = 0,
1330         },
1331         {
1332                 .number = U300_DMA_XGAM_PDI,
1333                 .name = "XGAM PDI",
1334                 .priority_high = 0,
1335         },
1336         /*
1337          * Don't set up device address, burst count or size of src
1338          * or dst bus for this peripheral - handled by PrimeCell
1339          * DMA extension.
1340          */
1341         {
1342                 .number = U300_DMA_SPI_TX,
1343                 .name = "SPI TX",
1344                 .priority_high = 0,
1345                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1346                                 COH901318_CX_CFG_LCR_DISABLE |
1347                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1348                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1349                 .param.ctrl_lli_chained = 0 |
1350                                 COH901318_CX_CTRL_TC_ENABLE |
1351                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1352                                 COH901318_CX_CTRL_TCP_DISABLE |
1353                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1354                                 COH901318_CX_CTRL_HSP_ENABLE |
1355                                 COH901318_CX_CTRL_HSS_DISABLE |
1356                                 COH901318_CX_CTRL_DDMA_LEGACY,
1357                 .param.ctrl_lli = 0 |
1358                                 COH901318_CX_CTRL_TC_ENABLE |
1359                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1360                                 COH901318_CX_CTRL_TCP_DISABLE |
1361                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1362                                 COH901318_CX_CTRL_HSP_ENABLE |
1363                                 COH901318_CX_CTRL_HSS_DISABLE |
1364                                 COH901318_CX_CTRL_DDMA_LEGACY,
1365                 .param.ctrl_lli_last = 0 |
1366                                 COH901318_CX_CTRL_TC_ENABLE |
1367                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1368                                 COH901318_CX_CTRL_TCP_DISABLE |
1369                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1370                                 COH901318_CX_CTRL_HSP_ENABLE |
1371                                 COH901318_CX_CTRL_HSS_DISABLE |
1372                                 COH901318_CX_CTRL_DDMA_LEGACY,
1373         },
1374         {
1375                 .number = U300_DMA_SPI_RX,
1376                 .name = "SPI RX",
1377                 .priority_high = 0,
1378                 .param.config = COH901318_CX_CFG_CH_DISABLE |
1379                                 COH901318_CX_CFG_LCR_DISABLE |
1380                                 COH901318_CX_CFG_TC_IRQ_ENABLE |
1381                                 COH901318_CX_CFG_BE_IRQ_ENABLE,
1382                 .param.ctrl_lli_chained = 0 |
1383                                 COH901318_CX_CTRL_TC_ENABLE |
1384                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1385                                 COH901318_CX_CTRL_TCP_DISABLE |
1386                                 COH901318_CX_CTRL_TC_IRQ_DISABLE |
1387                                 COH901318_CX_CTRL_HSP_ENABLE |
1388                                 COH901318_CX_CTRL_HSS_DISABLE |
1389                                 COH901318_CX_CTRL_DDMA_LEGACY,
1390                 .param.ctrl_lli = 0 |
1391                                 COH901318_CX_CTRL_TC_ENABLE |
1392                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1393                                 COH901318_CX_CTRL_TCP_DISABLE |
1394                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1395                                 COH901318_CX_CTRL_HSP_ENABLE |
1396                                 COH901318_CX_CTRL_HSS_DISABLE |
1397                                 COH901318_CX_CTRL_DDMA_LEGACY,
1398                 .param.ctrl_lli_last = 0 |
1399                                 COH901318_CX_CTRL_TC_ENABLE |
1400                                 COH901318_CX_CTRL_MASTER_MODE_M1RW |
1401                                 COH901318_CX_CTRL_TCP_DISABLE |
1402                                 COH901318_CX_CTRL_TC_IRQ_ENABLE |
1403                                 COH901318_CX_CTRL_HSP_ENABLE |
1404                                 COH901318_CX_CTRL_HSS_DISABLE |
1405                                 COH901318_CX_CTRL_DDMA_LEGACY,
1406
1407         },
1408         {
1409                 .number = U300_DMA_GENERAL_PURPOSE_0,
1410                 .name = "GENERAL 00",
1411                 .priority_high = 0,
1412
1413                 .param.config = flags_memcpy_config,
1414                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1415                 .param.ctrl_lli = flags_memcpy_lli,
1416                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1417         },
1418         {
1419                 .number = U300_DMA_GENERAL_PURPOSE_1,
1420                 .name = "GENERAL 01",
1421                 .priority_high = 0,
1422
1423                 .param.config = flags_memcpy_config,
1424                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1425                 .param.ctrl_lli = flags_memcpy_lli,
1426                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1427         },
1428         {
1429                 .number = U300_DMA_GENERAL_PURPOSE_2,
1430                 .name = "GENERAL 02",
1431                 .priority_high = 0,
1432
1433                 .param.config = flags_memcpy_config,
1434                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1435                 .param.ctrl_lli = flags_memcpy_lli,
1436                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1437         },
1438         {
1439                 .number = U300_DMA_GENERAL_PURPOSE_3,
1440                 .name = "GENERAL 03",
1441                 .priority_high = 0,
1442
1443                 .param.config = flags_memcpy_config,
1444                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1445                 .param.ctrl_lli = flags_memcpy_lli,
1446                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1447         },
1448         {
1449                 .number = U300_DMA_GENERAL_PURPOSE_4,
1450                 .name = "GENERAL 04",
1451                 .priority_high = 0,
1452
1453                 .param.config = flags_memcpy_config,
1454                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1455                 .param.ctrl_lli = flags_memcpy_lli,
1456                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1457         },
1458         {
1459                 .number = U300_DMA_GENERAL_PURPOSE_5,
1460                 .name = "GENERAL 05",
1461                 .priority_high = 0,
1462
1463                 .param.config = flags_memcpy_config,
1464                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1465                 .param.ctrl_lli = flags_memcpy_lli,
1466                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1467         },
1468         {
1469                 .number = U300_DMA_GENERAL_PURPOSE_6,
1470                 .name = "GENERAL 06",
1471                 .priority_high = 0,
1472
1473                 .param.config = flags_memcpy_config,
1474                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1475                 .param.ctrl_lli = flags_memcpy_lli,
1476                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1477         },
1478         {
1479                 .number = U300_DMA_GENERAL_PURPOSE_7,
1480                 .name = "GENERAL 07",
1481                 .priority_high = 0,
1482
1483                 .param.config = flags_memcpy_config,
1484                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1485                 .param.ctrl_lli = flags_memcpy_lli,
1486                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1487         },
1488         {
1489                 .number = U300_DMA_GENERAL_PURPOSE_8,
1490                 .name = "GENERAL 08",
1491                 .priority_high = 0,
1492
1493                 .param.config = flags_memcpy_config,
1494                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1495                 .param.ctrl_lli = flags_memcpy_lli,
1496                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1497         },
1498 #ifdef CONFIG_MACH_U300_BS335
1499         {
1500                 .number = U300_DMA_UART1_TX,
1501                 .name = "UART1 TX",
1502                 .priority_high = 0,
1503         },
1504         {
1505                 .number = U300_DMA_UART1_RX,
1506                 .name = "UART1 RX",
1507                 .priority_high = 0,
1508         }
1509 #else
1510         {
1511                 .number = U300_DMA_GENERAL_PURPOSE_9,
1512                 .name = "GENERAL 09",
1513                 .priority_high = 0,
1514
1515                 .param.config = flags_memcpy_config,
1516                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1517                 .param.ctrl_lli = flags_memcpy_lli,
1518                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1519         },
1520         {
1521                 .number = U300_DMA_GENERAL_PURPOSE_10,
1522                 .name = "GENERAL 10",
1523                 .priority_high = 0,
1524
1525                 .param.config = flags_memcpy_config,
1526                 .param.ctrl_lli_chained = flags_memcpy_lli_chained,
1527                 .param.ctrl_lli = flags_memcpy_lli,
1528                 .param.ctrl_lli_last = flags_memcpy_lli_last,
1529         }
1530 #endif
1531 };
1532
1533
1534 static struct coh901318_platform coh901318_platform = {
1535         .chans_slave = dma_slave_channels,
1536         .chans_memcpy = dma_memcpy_channels,
1537         .access_memory_state = coh901318_access_memory_state,
1538         .chan_conf = chan_config,
1539         .max_channels = U300_DMA_CHANNELS,
1540 };
1541
1542 static struct platform_device wdog_device = {
1543         .name = "coh901327_wdog",
1544         .id = -1,
1545         .num_resources = ARRAY_SIZE(wdog_resources),
1546         .resource = wdog_resources,
1547 };
1548
1549 static struct platform_device i2c0_device = {
1550         .name = "stu300",
1551         .id = 0,
1552         .num_resources = ARRAY_SIZE(i2c0_resources),
1553         .resource = i2c0_resources,
1554 };
1555
1556 static struct platform_device i2c1_device = {
1557         .name = "stu300",
1558         .id = 1,
1559         .num_resources = ARRAY_SIZE(i2c1_resources),
1560         .resource = i2c1_resources,
1561 };
1562
1563 /*
1564  * The different variants have a few different versions of the
1565  * GPIO block, with different number of ports.
1566  */
1567 static struct u300_gpio_platform u300_gpio_plat = {
1568 #if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
1569         .variant = U300_GPIO_COH901335,
1570         .ports = 3,
1571 #endif
1572 #ifdef CONFIG_MACH_U300_BS335
1573         .variant = U300_GPIO_COH901571_3_BS335,
1574         .ports = 7,
1575 #endif
1576 #ifdef CONFIG_MACH_U300_BS365
1577         .variant = U300_GPIO_COH901571_3_BS365,
1578         .ports = 5,
1579 #endif
1580         .gpio_base = 0,
1581         .gpio_irq_base = IRQ_U300_GPIO_BASE,
1582 };
1583
1584 static struct platform_device gpio_device = {
1585         .name = "u300-gpio",
1586         .id = -1,
1587         .num_resources = ARRAY_SIZE(gpio_resources),
1588         .resource = gpio_resources,
1589         .dev = {
1590                 .platform_data = &u300_gpio_plat,
1591         },
1592 };
1593
1594 static struct platform_device keypad_device = {
1595         .name = "keypad",
1596         .id = -1,
1597         .num_resources = ARRAY_SIZE(keypad_resources),
1598         .resource = keypad_resources,
1599 };
1600
1601 static struct platform_device rtc_device = {
1602         .name = "rtc-coh901331",
1603         .id = -1,
1604         .num_resources = ARRAY_SIZE(rtc_resources),
1605         .resource = rtc_resources,
1606 };
1607
1608 static struct mtd_partition u300_partitions[] = {
1609         {
1610                 .name = "bootrecords",
1611                 .offset = 0,
1612                 .size = SZ_128K,
1613         },
1614         {
1615                 .name = "free",
1616                 .offset = SZ_128K,
1617                 .size = 8064 * SZ_1K,
1618         },
1619         {
1620                 .name = "platform",
1621                 .offset = 8192 * SZ_1K,
1622                 .size = 253952 * SZ_1K,
1623         },
1624 };
1625
1626 static struct fsmc_nand_platform_data nand_platform_data = {
1627         .partitions = u300_partitions,
1628         .nr_partitions = ARRAY_SIZE(u300_partitions),
1629         .options = NAND_SKIP_BBTSCAN,
1630         .width = FSMC_NAND_BW8,
1631 };
1632
1633 static struct platform_device nand_device = {
1634         .name = "fsmc-nand",
1635         .id = -1,
1636         .resource = fsmc_resources,
1637         .num_resources = ARRAY_SIZE(fsmc_resources),
1638         .dev = {
1639                 .platform_data = &nand_platform_data,
1640         },
1641 };
1642
1643 static struct platform_device ave_device = {
1644         .name = "video_enc",
1645         .id = -1,
1646         .num_resources = ARRAY_SIZE(ave_resources),
1647         .resource = ave_resources,
1648 };
1649
1650 static struct platform_device dma_device = {
1651         .name           = "coh901318",
1652         .id             = -1,
1653         .resource       = dma_resource,
1654         .num_resources  = ARRAY_SIZE(dma_resource),
1655         .dev = {
1656                 .platform_data = &coh901318_platform,
1657                 .coherent_dma_mask = ~0,
1658         },
1659 };
1660
1661 /*
1662  * Notice that AMBA devices are initialized before platform devices.
1663  *
1664  */
1665 static struct platform_device *platform_devs[] __initdata = {
1666         &dma_device,
1667         &i2c0_device,
1668         &i2c1_device,
1669         &keypad_device,
1670         &rtc_device,
1671         &gpio_device,
1672         &nand_device,
1673         &wdog_device,
1674         &ave_device
1675 };
1676
1677
1678 /*
1679  * Interrupts: the U300 platforms have two pl190 ARM PrimeCells connected
1680  * together so some interrupts are connected to the first one and some
1681  * to the second one.
1682  */
1683 void __init u300_init_irq(void)
1684 {
1685         u32 mask[2] = {0, 0};
1686         struct clk *clk;
1687         int i;
1688
1689         /* initialize clocking early, we want to clock the INTCON */
1690         u300_clock_init();
1691
1692         /* Clock the interrupt controller */
1693         clk = clk_get_sys("intcon", NULL);
1694         BUG_ON(IS_ERR(clk));
1695         clk_enable(clk);
1696
1697         for (i = 0; i < U300_VIC_IRQS_END; i++)
1698                 set_bit(i, (unsigned long *) &mask[0]);
1699         vic_init((void __iomem *) U300_INTCON0_VBASE, 0, mask[0], mask[0]);
1700         vic_init((void __iomem *) U300_INTCON1_VBASE, 32, mask[1], mask[1]);
1701 }
1702
1703
1704 /*
1705  * U300 platforms peripheral handling
1706  */
1707 struct db_chip {
1708         u16 chipid;
1709         const char *name;
1710 };
1711
1712 /*
1713  * This is a list of the Digital Baseband chips used in the U300 platform.
1714  */
1715 static struct db_chip db_chips[] __initdata = {
1716         {
1717                 .chipid = 0xb800,
1718                 .name = "DB3000",
1719         },
1720         {
1721                 .chipid = 0xc000,
1722                 .name = "DB3100",
1723         },
1724         {
1725                 .chipid = 0xc800,
1726                 .name = "DB3150",
1727         },
1728         {
1729                 .chipid = 0xd800,
1730                 .name = "DB3200",
1731         },
1732         {
1733                 .chipid = 0xe000,
1734                 .name = "DB3250",
1735         },
1736         {
1737                 .chipid = 0xe800,
1738                 .name = "DB3210",
1739         },
1740         {
1741                 .chipid = 0xf000,
1742                 .name = "DB3350 P1x",
1743         },
1744         {
1745                 .chipid = 0xf100,
1746                 .name = "DB3350 P2x",
1747         },
1748         {
1749                 .chipid = 0x0000, /* List terminator */
1750                 .name = NULL,
1751         }
1752 };
1753
1754 static void __init u300_init_check_chip(void)
1755 {
1756
1757         u16 val;
1758         struct db_chip *chip;
1759         const char *chipname;
1760         const char unknown[] = "UNKNOWN";
1761
1762         /* Read out and print chip ID */
1763         val = readw(U300_SYSCON_VBASE + U300_SYSCON_CIDR);
1764         /* This is in funky bigendian order... */
1765         val = (val & 0xFFU) << 8 | (val >> 8);
1766         chip = db_chips;
1767         chipname = unknown;
1768
1769         for ( ; chip->chipid; chip++) {
1770                 if (chip->chipid == (val & 0xFF00U)) {
1771                         chipname = chip->name;
1772                         break;
1773                 }
1774         }
1775         printk(KERN_INFO "Initializing U300 system on %s baseband chip " \
1776                "(chip ID 0x%04x)\n", chipname, val);
1777
1778 #ifdef CONFIG_MACH_U300_BS330
1779         if ((val & 0xFF00U) != 0xd800) {
1780                 printk(KERN_ERR "Platform configured for BS330 " \
1781                        "with DB3200 but %s detected, expect problems!",
1782                        chipname);
1783         }
1784 #endif
1785 #ifdef CONFIG_MACH_U300_BS335
1786         if ((val & 0xFF00U) != 0xf000 && (val & 0xFF00U) != 0xf100) {
1787                 printk(KERN_ERR "Platform configured for BS335 " \
1788                        " with DB3350 but %s detected, expect problems!",
1789                        chipname);
1790         }
1791 #endif
1792 #ifdef CONFIG_MACH_U300_BS365
1793         if ((val & 0xFF00U) != 0xe800) {
1794                 printk(KERN_ERR "Platform configured for BS365 " \
1795                        "with DB3210 but %s detected, expect problems!",
1796                        chipname);
1797         }
1798 #endif
1799
1800
1801 }
1802
1803 /*
1804  * Some devices and their resources require reserved physical memory from
1805  * the end of the available RAM. This function traverses the list of devices
1806  * and assigns actual addresses to these.
1807  */
1808 static void __init u300_assign_physmem(void)
1809 {
1810         unsigned long curr_start = __pa(high_memory);
1811         int i, j;
1812
1813         for (i = 0; i < ARRAY_SIZE(platform_devs); i++) {
1814                 for (j = 0; j < platform_devs[i]->num_resources; j++) {
1815                         struct resource *const res =
1816                           &platform_devs[i]->resource[j];
1817
1818                         if (IORESOURCE_MEM == res->flags &&
1819                                      0 == res->start) {
1820                                 res->start  = curr_start;
1821                                 res->end   += curr_start;
1822                                 curr_start += resource_size(res);
1823
1824                                 printk(KERN_INFO "core.c: Mapping RAM " \
1825                                        "%#x-%#x to device %s:%s\n",
1826                                         res->start, res->end,
1827                                        platform_devs[i]->name, res->name);
1828                         }
1829                 }
1830         }
1831 }
1832
1833 void __init u300_init_devices(void)
1834 {
1835         int i;
1836         u16 val;
1837
1838         /* Check what platform we run and print some status information */
1839         u300_init_check_chip();
1840
1841         /* Set system to run at PLL208, max performance, a known state. */
1842         val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
1843         val &= ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK;
1844         writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
1845         /* Wait for the PLL208 to lock if not locked in yet */
1846         while (!(readw(U300_SYSCON_VBASE + U300_SYSCON_CSR) &
1847                  U300_SYSCON_CSR_PLL208_LOCK_IND));
1848         /* Initialize SPI device with some board specifics */
1849         u300_spi_init(&pl022_device);
1850
1851         /* Register the AMBA devices in the AMBA bus abstraction layer */
1852         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
1853                 struct amba_device *d = amba_devs[i];
1854                 amba_device_register(d, &iomem_resource);
1855         }
1856
1857         u300_assign_physmem();
1858
1859         /* Register subdevices on the I2C buses */
1860         u300_i2c_register_board_devices();
1861
1862         /* Register the platform devices */
1863         platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
1864
1865         /* Register subdevices on the SPI bus */
1866         u300_spi_register_board_devices();
1867
1868 #ifndef CONFIG_MACH_U300_SEMI_IS_SHARED
1869         /*
1870          * Enable SEMI self refresh. Self-refresh of the SDRAM is entered when
1871          * both subsystems are requesting this mode.
1872          * If we not share the Acc SDRAM, this is never the case. Therefore
1873          * enable it here from the App side.
1874          */
1875         val = readw(U300_SYSCON_VBASE + U300_SYSCON_SMCR) |
1876                 U300_SYSCON_SMCR_SEMI_SREFREQ_ENABLE;
1877         writew(val, U300_SYSCON_VBASE + U300_SYSCON_SMCR);
1878 #endif /* CONFIG_MACH_U300_SEMI_IS_SHARED */
1879 }
1880
1881 static int core_module_init(void)
1882 {
1883         /*
1884          * This needs to be initialized later: it needs the input framework
1885          * to be initialized first.
1886          */
1887         return mmc_init(&mmcsd_device);
1888 }
1889 module_init(core_module_init);