arch/arm/mach-spear3xx/spear310.c

   1 /*
   2  * arch/arm/mach-spear3xx/spear310.c
   3  *
   4  * SPEAr310 machine source file
   5  *
   6  * Copyright (C) 2009 ST Microelectronics
   7  * Viresh Kumar<viresh.kumar@st.com>
   8  *
   9  * This file is licensed under the terms of the GNU General Public
  10  * License version 2. This program is licensed "as is" without any
  11  * warranty of any kind, whether express or implied.
  12  */
  13
  14 #include <linux/ptrace.h>
  15 #include <asm/irq.h>
  16 #include <plat/shirq.h>
  17 #include <mach/generic.h>
  18 #include <mach/hardware.h>
  19
  20 /* pad multiplexing support */
  21 /* muxing registers */
  22 #define PAD_MUX_CONFIG_REG      0x08
  23
  24 /* devices */
  25 struct pmx_dev_mode pmx_emi_cs_0_1_4_5_modes[] = {
  26         {
  27                 .ids = 0x00,
  28                 .mask = PMX_TIMER_3_4_MASK,
  29         },
  30 };
  31
  32 struct pmx_dev pmx_emi_cs_0_1_4_5 = {
  33         .name = "emi_cs_0_1_4_5",
  34         .modes = pmx_emi_cs_0_1_4_5_modes,
  35         .mode_count = ARRAY_SIZE(pmx_emi_cs_0_1_4_5_modes),
  36         .enb_on_reset = 1,
  37 };
  38
  39 struct pmx_dev_mode pmx_emi_cs_2_3_modes[] = {
  40         {
  41                 .ids = 0x00,
  42                 .mask = PMX_TIMER_1_2_MASK,
  43         },
  44 };
  45
  46 struct pmx_dev pmx_emi_cs_2_3 = {
  47         .name = "emi_cs_2_3",
  48         .modes = pmx_emi_cs_2_3_modes,
  49         .mode_count = ARRAY_SIZE(pmx_emi_cs_2_3_modes),
  50         .enb_on_reset = 1,
  51 };
  52
  53 struct pmx_dev_mode pmx_uart1_modes[] = {
  54         {
  55                 .ids = 0x00,
  56                 .mask = PMX_FIRDA_MASK,
  57         },
  58 };
  59
  60 struct pmx_dev pmx_uart1 = {
  61         .name = "uart1",
  62         .modes = pmx_uart1_modes,
  63         .mode_count = ARRAY_SIZE(pmx_uart1_modes),
  64         .enb_on_reset = 1,
  65 };
  66
  67 struct pmx_dev_mode pmx_uart2_modes[] = {
  68         {
  69                 .ids = 0x00,
  70                 .mask = PMX_TIMER_1_2_MASK,
  71         },
  72 };
  73
  74 struct pmx_dev pmx_uart2 = {
  75         .name = "uart2",
  76         .modes = pmx_uart2_modes,
  77         .mode_count = ARRAY_SIZE(pmx_uart2_modes),
  78         .enb_on_reset = 1,
  79 };
  80
  81 struct pmx_dev_mode pmx_uart3_4_5_modes[] = {
  82         {
  83                 .ids = 0x00,
  84                 .mask = PMX_UART0_MODEM_MASK,
  85         },
  86 };
  87
  88 struct pmx_dev pmx_uart3_4_5 = {
  89         .name = "uart3_4_5",
  90         .modes = pmx_uart3_4_5_modes,
  91         .mode_count = ARRAY_SIZE(pmx_uart3_4_5_modes),
  92         .enb_on_reset = 1,
  93 };
  94
  95 struct pmx_dev_mode pmx_fsmc_modes[] = {
  96         {
  97                 .ids = 0x00,
  98                 .mask = PMX_SSP_CS_MASK,
  99         },
 100 };
 101
 102 struct pmx_dev pmx_fsmc = {
 103         .name = "fsmc",
 104         .modes = pmx_fsmc_modes,
 105         .mode_count = ARRAY_SIZE(pmx_fsmc_modes),
 106         .enb_on_reset = 1,
 107 };
 108
 109 struct pmx_dev_mode pmx_rs485_0_1_modes[] = {
 110         {
 111                 .ids = 0x00,
 112                 .mask = PMX_MII_MASK,
 113         },
 114 };
 115
 116 struct pmx_dev pmx_rs485_0_1 = {
 117         .name = "rs485_0_1",
 118         .modes = pmx_rs485_0_1_modes,
 119         .mode_count = ARRAY_SIZE(pmx_rs485_0_1_modes),
 120         .enb_on_reset = 1,
 121 };
 122
 123 struct pmx_dev_mode pmx_tdm0_modes[] = {
 124         {
 125                 .ids = 0x00,
 126                 .mask = PMX_MII_MASK,
 127         },
 128 };
 129
 130 struct pmx_dev pmx_tdm0 = {
 131         .name = "tdm0",
 132         .modes = pmx_tdm0_modes,
 133         .mode_count = ARRAY_SIZE(pmx_tdm0_modes),
 134         .enb_on_reset = 1,
 135 };
 136
 137 /* pmx driver structure */
 138 struct pmx_driver pmx_driver = {
 139         .mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
 140 };
 141
 142 /* spear3xx shared irq */
 143 struct shirq_dev_config shirq_ras1_config[] = {
 144         {
 145                 .virq = VIRQ_SMII0,
 146                 .status_mask = SMII0_IRQ_MASK,
 147         }, {
 148                 .virq = VIRQ_SMII1,
 149                 .status_mask = SMII1_IRQ_MASK,
 150         }, {
 151                 .virq = VIRQ_SMII2,
 152                 .status_mask = SMII2_IRQ_MASK,
 153         }, {
 154                 .virq = VIRQ_SMII3,
 155                 .status_mask = SMII3_IRQ_MASK,
 156         }, {
 157                 .virq = VIRQ_WAKEUP_SMII0,
 158                 .status_mask = WAKEUP_SMII0_IRQ_MASK,
 159         }, {
 160                 .virq = VIRQ_WAKEUP_SMII1,
 161                 .status_mask = WAKEUP_SMII1_IRQ_MASK,
 162         }, {
 163                 .virq = VIRQ_WAKEUP_SMII2,
 164                 .status_mask = WAKEUP_SMII2_IRQ_MASK,
 165         }, {
 166                 .virq = VIRQ_WAKEUP_SMII3,
 167                 .status_mask = WAKEUP_SMII3_IRQ_MASK,
 168         },
 169 };
 170
 171 struct spear_shirq shirq_ras1 = {
 172         .irq = IRQ_GEN_RAS_1,
 173         .dev_config = shirq_ras1_config,
 174         .dev_count = ARRAY_SIZE(shirq_ras1_config),
 175         .regs = {
 176                 .enb_reg = -1,
 177                 .status_reg = INT_STS_MASK_REG,
 178                 .status_reg_mask = SHIRQ_RAS1_MASK,
 179                 .clear_reg = -1,
 180         },
 181 };
 182
 183 struct shirq_dev_config shirq_ras2_config[] = {
 184         {
 185                 .virq = VIRQ_UART1,
 186                 .status_mask = UART1_IRQ_MASK,
 187         }, {
 188                 .virq = VIRQ_UART2,
 189                 .status_mask = UART2_IRQ_MASK,
 190         }, {
 191                 .virq = VIRQ_UART3,
 192                 .status_mask = UART3_IRQ_MASK,
 193         }, {
 194                 .virq = VIRQ_UART4,
 195                 .status_mask = UART4_IRQ_MASK,
 196         }, {
 197                 .virq = VIRQ_UART5,
 198                 .status_mask = UART5_IRQ_MASK,
 199         },
 200 };
 201
 202 struct spear_shirq shirq_ras2 = {
 203         .irq = IRQ_GEN_RAS_2,
 204         .dev_config = shirq_ras2_config,
 205         .dev_count = ARRAY_SIZE(shirq_ras2_config),
 206         .regs = {
 207                 .enb_reg = -1,
 208                 .status_reg = INT_STS_MASK_REG,
 209                 .status_reg_mask = SHIRQ_RAS2_MASK,
 210                 .clear_reg = -1,
 211         },
 212 };
 213
 214 struct shirq_dev_config shirq_ras3_config[] = {
 215         {
 216                 .virq = VIRQ_EMI,
 217                 .status_mask = EMI_IRQ_MASK,
 218         },
 219 };
 220
 221 struct spear_shirq shirq_ras3 = {
 222         .irq = IRQ_GEN_RAS_3,
 223         .dev_config = shirq_ras3_config,
 224         .dev_count = ARRAY_SIZE(shirq_ras3_config),
 225         .regs = {
 226                 .enb_reg = -1,
 227                 .status_reg = INT_STS_MASK_REG,
 228                 .status_reg_mask = SHIRQ_RAS3_MASK,
 229                 .clear_reg = -1,
 230         },
 231 };
 232
 233 struct shirq_dev_config shirq_intrcomm_ras_config[] = {
 234         {
 235                 .virq = VIRQ_TDM_HDLC,
 236                 .status_mask = TDM_HDLC_IRQ_MASK,
 237         }, {
 238                 .virq = VIRQ_RS485_0,
 239                 .status_mask = RS485_0_IRQ_MASK,
 240         }, {
 241                 .virq = VIRQ_RS485_1,
 242                 .status_mask = RS485_1_IRQ_MASK,
 243         },
 244 };
 245
 246 struct spear_shirq shirq_intrcomm_ras = {
 247         .irq = IRQ_INTRCOMM_RAS_ARM,
 248         .dev_config = shirq_intrcomm_ras_config,
 249         .dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config),
 250         .regs = {
 251                 .enb_reg = -1,
 252                 .status_reg = INT_STS_MASK_REG,
 253                 .status_reg_mask = SHIRQ_INTRCOMM_RAS_MASK,
 254                 .clear_reg = -1,
 255         },
 256 };
 257
 258 /* Add spear310 specific devices here */
 259
 260 /* spear310 routines */
 261 void __init spear310_init(void)
 262 {
 263         void __iomem *base;
 264         int ret = 0;
 265
 266         /* call spear3xx family common init function */
 267         spear3xx_init();
 268
 269         /* shared irq registration */
 270         base = ioremap(SPEAR310_SOC_CONFIG_BASE, SZ_4K);
 271         if (base) {
 272                 /* shirq 1 */
 273                 shirq_ras1.regs.base = base;
 274                 ret = spear_shirq_register(&shirq_ras1);
 275                 if (ret)
 276                         printk(KERN_ERR "Error registering Shared IRQ 1\n");
 277
 278                 /* shirq 2 */
 279                 shirq_ras2.regs.base = base;
 280                 ret = spear_shirq_register(&shirq_ras2);
 281                 if (ret)
 282                         printk(KERN_ERR "Error registering Shared IRQ 2\n");
 283
 284                 /* shirq 3 */
 285                 shirq_ras3.regs.base = base;
 286                 ret = spear_shirq_register(&shirq_ras3);
 287                 if (ret)
 288                         printk(KERN_ERR "Error registering Shared IRQ 3\n");
 289
 290                 /* shirq 4 */
 291                 shirq_intrcomm_ras.regs.base = base;
 292                 ret = spear_shirq_register(&shirq_intrcomm_ras);
 293                 if (ret)
 294                         printk(KERN_ERR "Error registering Shared IRQ 4\n");
 295         }
 296
 297         /* pmx initialization */
 298         pmx_driver.base = base;
 299         ret = pmx_register(&pmx_driver);
 300         if (ret)
 301                 printk(KERN_ERR "padmux: registeration failed. err no: %d\n",
 302                                 ret);
 303 }